#include <gpu_tlb.hh>

Inheritance diagram for X86ISA::GpuTLB:

Classes
struct	AccessInfo
	This hash map will use the virtual page address as a key and will keep track of total number of accesses per page. More...

class	CpuSidePort

class	MemSidePort
	MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected. More...

class	TLBEvent

class	Translation

struct	TranslationState
	TLB TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back. More...

Public Types
enum	tlbOutcome { TLB_HIT, TLB_MISS, PAGE_WALK, MISS_RETURN }

typedef X86GPUTLBParams	Params

typedef enum BaseTLB::Mode	Mode

typedef std::unordered_map< Addr, AccessInfo >	AccessPatternTable

Public Types inherited from ClockedObject
typedef ClockedObjectParams	Params
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
	GpuTLB (const Params *p)

	~GpuTLB ()

void	dumpAll ()

TlbEntry *	lookup (Addr va, bool update_lru=true)

void	setConfigAddress (uint32_t addr)

Walker *	getWalker ()

void	invalidateAll ()

void	invalidateNonGlobal ()

void	demapPage (Addr va, uint64_t asn)

void	regStats () override
	Callback to set stat parameters. More...

void	updatePageFootprint (Addr virt_page_addr)

void	printAccessPattern ()

Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode, int &latency)

void	translateTiming (const RequestPtr &req, ThreadContext tc, Translation translation, Mode mode, int &latency)

Tick	doMmuRegRead (ThreadContext tc, Packet pkt)

Tick	doMmuRegWrite (ThreadContext tc, Packet pkt)

TlbEntry *	insert (Addr vpn, TlbEntry &entry)

virtual void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

virtual void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

void	issueTranslation ()

bool	tlbLookup (const RequestPtr &req, ThreadContext *tc, bool update_stats)
	TLB_lookup will only perform a TLB lookup returning true on a TLB hit and false on a TLB miss. More...

void	handleTranslationReturn (Addr addr, tlbOutcome outcome, PacketPtr pkt)
	handleTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns. More...

void	handleFuncTranslationReturn (PacketPtr pkt, tlbOutcome outcome)
	handleFuncTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns. More...

void	pagingProtectionChecks (ThreadContext tc, PacketPtr pkt, TlbEntry tlb_entry, Mode mode)
	Do Paging protection checks. More...

void	updatePhysAddresses (Addr virt_page_addr, TlbEntry *tlb_entry, Addr phys_page_addr)

void	issueTLBLookup (PacketPtr pkt)
	Do the TLB lookup for this coalesced request and schedule another event <TLB access latency> cycles later. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index. More...

void	translationReturn (Addr virtPageAddr, tlbOutcome outcome, PacketPtr pkt)
	A TLBEvent is scheduled after the TLB lookup and helps us take the appropriate actions: (e.g., update TLB on a hit, send request to lower level TLB on a miss, or start a page walk if this was the last-level TLB). More...

void	cleanup ()

void	exitCallback ()

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams *p)

const Params *	params () const

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from SimObject
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Stats::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (Stats::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
int	hitLatency

int	missLatency1

int	missLatency2

Stats::Scalar	localNumTLBAccesses

Stats::Scalar	localNumTLBHits

Stats::Scalar	localNumTLBMisses

Stats::Formula	localTLBMissRate

Stats::Scalar	globalNumTLBAccesses

Stats::Scalar	globalNumTLBHits

Stats::Scalar	globalNumTLBMisses

Stats::Formula	globalTLBMissRate

Stats::Scalar	accessCycles

Stats::Scalar	pageTableCycles

Stats::Scalar	numUniquePages

Stats::Scalar	localCycles

Stats::Formula	localLatency

Stats::Scalar	avgReuseDistance

std::vector< CpuSidePort * >	cpuSidePort

std::vector< MemSidePort * >	memSidePort

int	maxCoalescedReqs

int	outstandingReqs

std::unordered_map< Addr, TLBEvent * >	translationReturnEvent

std::queue< Addr >	cleanupQueue

EventFunctionWrapper	cleanupEvent

AccessPatternTable	TLBFootprint

EventFunctionWrapper	exitEvent

Public Attributes inherited from ClockedObject
PowerState *	powerState

Protected Types
typedef std::list< TlbEntry * >	EntryList

Protected Member Functions
EntryList::iterator	lookupIt (Addr va, bool update_lru=true)

Fault	translateInt (bool read, const RequestPtr &req, ThreadContext *tc)

Fault	translate (const RequestPtr &req, ThreadContext tc, Translation translation, Mode mode, bool &delayedResponse, bool timing, int &latency)

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Protected Attributes
uint32_t	configAddress

Walker *	walker

int	size

int	assoc

int	numSets

bool	FA
	true if this is a fully-associative TLB More...

Addr	setMask

bool	allocationPolicy
	Allocation Policy: true if we always allocate on a hit, false otherwise. More...

bool	hasMemSidePort
	if true, then this is not the last level TLB More...

bool	accessDistance
	Print out accessDistance stats. More...

std::vector< TlbEntry >	tlb

std::vector< EntryList >	freeList

std::vector< EntryList >	entryList
	An entryList per set is the equivalent of an LRU stack; it's used to guide replacement decisions. More...

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Friends
class	Walker

Additional Inherited Members
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)
	Serializes all the SimObjects. More...

static void	unserializeGlobals (CheckpointIn &cp)

Detailed Description

Definition at line 63 of file gpu_tlb.hh.

Member Typedef Documentation

◆ AccessPatternTable

typedef std::unordered_map<Addr, AccessInfo> X86ISA::GpuTLB::AccessPatternTable

Definition at line 422 of file gpu_tlb.hh.

◆ EntryList

typedef std::list<TlbEntry*> X86ISA::GpuTLB::EntryList

protected

Definition at line 68 of file gpu_tlb.hh.

◆ Mode

typedef enum BaseTLB::Mode X86ISA::GpuTLB::Mode

Definition at line 77 of file gpu_tlb.hh.

◆ Params

typedef X86GPUTLBParams X86ISA::GpuTLB::Params

Definition at line 73 of file gpu_tlb.hh.

Member Enumeration Documentation

◆ tlbOutcome

enum X86ISA::GpuTLB::tlbOutcome

Enumerator
TLB_HIT
TLB_MISS
PAGE_WALK
MISS_RETURN

Definition at line 221 of file gpu_tlb.hh.

Constructor & Destructor Documentation

◆ GpuTLB()

X86ISA::GpuTLB::GpuTLB ( const Params * p )

Warning: : the set-associative version assumes you have a fixed page size of 4KB. If the page size is greather than 4KB (as defined in the TheISA::PageBytes), then there are various issues w/ the current implementation (you'd have the same 8KB page being replicated in different sets etc)

Definition at line 66 of file gpu_tlb.cc.

References cleanup().

◆ ~GpuTLB()

X86ISA::GpuTLB::~GpuTLB ( )

Definition at line 130 of file gpu_tlb.cc.

References translationReturnEvent.

Member Function Documentation

◆ cleanup()

void X86ISA::GpuTLB::cleanup ( )

the higher level coalescer should retry if it has any pending requests.

Definition at line 1366 of file gpu_tlb.cc.

References cleanupQueue, cpuSidePort, ArmISA::i, outstandingReqs, and translationReturnEvent.

Referenced by GpuTLB().

◆ demapPage()

void X86ISA::GpuTLB::demapPage	(	Addr	va,
		uint64_t	asn
	)

Definition at line 266 of file gpu_tlb.cc.

References entryList, freeList, lookupIt(), ArmISA::PageShift, setMask, and ArmISA::va.

◆ doMmuRegRead()

Tick X86ISA::GpuTLB::doMmuRegRead	(	ThreadContext *	tc,
		Packet *	pkt
	)

◆ doMmuRegWrite()

Tick X86ISA::GpuTLB::doMmuRegWrite	(	ThreadContext *	tc,
		Packet *	pkt
	)

◆ dumpAll()

void X86ISA::GpuTLB::dumpAll ( )

◆ exitCallback()

void X86ISA::GpuTLB::exitCallback ( )

Definition at line 1425 of file gpu_tlb.cc.

References accessDistance, avgReuseDistance, OutputDirectory::create(), ArmISA::i, SimObject::name(), simout, OutputStream::stream(), and TLBFootprint.

◆ getPort()

Port & X86ISA::GpuTLB::getPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from SimObject.

Definition at line 137 of file gpu_tlb.cc.

References cpuSidePort, hasMemSidePort, memSidePort, and panic.

◆ getWalker()

Walker * X86ISA::GpuTLB::getWalker ( )

Definition at line 646 of file gpu_tlb.cc.

References walker.

◆ handleFuncTranslationReturn()

void X86ISA::GpuTLB::handleFuncTranslationReturn	(	PacketPtr	pkt,
		tlbOutcome	tlb_outcome
	)

handleFuncTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns.

It updates LRU, inserts the TLB entry on a miss depending on the allocation policy and does the required protection checks. It does NOT create a new packet to update the packet's addr; this is done in hsail-gpu code.

We are returning either from a page walk or from a hit at a lower TLB level. The senderState should be "carrying" a pointer to the correct TLBEntry.

Do paging checks if it's a normal functional access. If it's for a prefetch, then sometimes you can try to prefetch something that won't pass protection. We don't actually want to fault becuase there is no demand access to deem this a violation. Just put it in the TLB and it will fault if indeed a future demand access touches it in violation.

This feature could be used to explore security issues around speculative memory accesses.

Definition at line 1132 of file gpu_tlb.cc.

References allocationPolicy, DPRINTF, insert(), ArmISA::mode, X86ISA::TlbEntry::paddr, ArmISA::PageBytes, pagingProtectionChecks(), X86ISA::GpuTLB::TranslationState::prefetch, Packet::req, roundDown(), Packet::senderState, X86ISA::TlbEntry::size(), X86ISA::GpuTLB::TranslationState::tc, TLB_HIT, X86ISA::GpuTLB::TranslationState::tlbEntry, X86ISA::GpuTLB::TranslationState::tlbMode, X86ISA::TlbEntry::uncacheable, Request::UNCACHEABLE, X86ISA::TlbEntry::vaddr, and MipsISA::vaddr.

◆ handleTranslationReturn()

void X86ISA::GpuTLB::handleTranslationReturn	(	Addr	virt_page_addr,
		tlbOutcome	tlb_outcome,
		PacketPtr	pkt
	)

handleTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns.

The latter calls handelHit with TLB miss as tlbOutcome.

We are returning either from a page walk or from a hit at a lower TLB level. The senderState should be "carrying" a pointer to the correct TLBEntry.

At this point the packet carries an up-to-date tlbEntry pointer in its senderState. Next step is to do the paging protection checks.

Definition at line 878 of file gpu_tlb.cc.

References allocationPolicy, cleanupEvent, cleanupQueue, cpuSidePort, curTick(), DPRINTF, insert(), Packet::isRequest(), Packet::makeTimingResponse(), ArmISA::mode, X86ISA::TlbEntry::paddr, pagingProtectionChecks(), Packet::req, EventManager::schedule(), Event::scheduled(), Packet::senderState, X86ISA::TlbEntry::size(), X86ISA::GpuTLB::TranslationState::tc, TLB_HIT, X86ISA::GpuTLB::TranslationState::tlbEntry, X86ISA::GpuTLB::TranslationState::tlbMode, X86ISA::TlbEntry::uncacheable, Request::UNCACHEABLE, X86ISA::TlbEntry::vaddr, and MipsISA::vaddr.

Referenced by translationReturn().

◆ insert()

TlbEntry * X86ISA::GpuTLB::insert	(	Addr	vpn,
		TlbEntry &	entry
	)

vpn holds the virtual page address The least significant bits are simply masked

Definition at line 159 of file gpu_tlb.cc.

References entryList, freeList, ArmISA::PageShift, setMask, and X86ISA::TlbEntry::vaddr.

Referenced by handleFuncTranslationReturn(), handleTranslationReturn(), and translate().

◆ invalidateAll()

void X86ISA::GpuTLB::invalidateAll ( )

Definition at line 228 of file gpu_tlb.cc.

References DPRINTF, entryList, freeList, ArmISA::i, and numSets.

◆ invalidateNonGlobal()

void X86ISA::GpuTLB::invalidateNonGlobal ( )

Definition at line 248 of file gpu_tlb.cc.

References DPRINTF, entryList, freeList, ArmISA::i, and numSets.

◆ issueTLBLookup()

void X86ISA::GpuTLB::issueTLBLookup ( PacketPtr pkt )

Do the TLB lookup for this coalesced request and schedule another event <TLB access latency> cycles later.

Definition at line 751 of file gpu_tlb.cc.

References accessCycles, curTick(), Clocked::cyclesToTicks(), DPRINTF, ThreadContext::getProcessPtr(), globalNumTLBAccesses, globalNumTLBHits, globalNumTLBMisses, hitLatency, X86ISA::GpuTLB::TranslationState::hitLevel, localCycles, lookup(), X86ISA::p, X86ISA::TlbEntry::paddr, ArmISA::PageBytes, panic, X86ISA::GpuTLB::TranslationState::prefetch, Packet::req, X86ISA::GpuTLB::TranslationState::reqCnt, roundDown(), EventManager::schedule(), Packet::senderState, X86ISA::GpuTLB::TranslationState::tc, TLB_HIT, TLB_MISS, X86ISA::GpuTLB::TranslationState::tlbEntry, tlbLookup(), translationReturnEvent, updatePageFootprint(), and X86ISA::TlbEntry::vaddr.

◆ issueTranslation()

void X86ISA::GpuTLB::issueTranslation ( )

◆ lookup()

TlbEntry * X86ISA::GpuTLB::lookup	(	Addr	va,
		bool	update_lru = `true`
	)

Definition at line 215 of file gpu_tlb.cc.

References entryList, lookupIt(), ArmISA::PageShift, setMask, and ArmISA::va.

Referenced by issueTLBLookup(), tlbLookup(), and translate().

◆ lookupIt()

GpuTLB::EntryList::iterator X86ISA::GpuTLB::lookupIt	(	Addr	va,
		bool	update_lru = `true`
	)

protected

Definition at line 185 of file gpu_tlb.cc.

References DPRINTF, entryList, FA, ArmISA::PageShift, setMask, and ArmISA::va.

Referenced by demapPage(), and lookup().

◆ pagingProtectionChecks()

void X86ISA::GpuTLB::pagingProtectionChecks	(	ThreadContext *	tc,
		PacketPtr	pkt,
		TlbEntry *	tlb_entry,
		Mode	mode
	)

Do Paging protection checks.

If we encounter a page fault, then an assertion is fired.

Definition at line 843 of file gpu_tlb.cc.

References X86ISA::CPL0FlagBit, X86ISA::FlagShift, X86ISA::MISCREG_CR0, X86ISA::MISCREG_M5_REG, ArmISA::mode, panic, ThreadContext::readMiscRegNoEffect(), Packet::req, X86ISA::StoreCheck, X86ISA::TlbEntry::user, X86ISA::TlbEntry::writable, and BaseTLB::Write.

Referenced by handleFuncTranslationReturn(), and handleTranslationReturn().

◆ printAccessPattern()

void X86ISA::GpuTLB::printAccessPattern ( )

◆ regStats()

void X86ISA::GpuTLB::regStats ( )

overridevirtual

Callback to set stat parameters.

This callback is typically used for complex stats (e.g., distributions) that need parameters in addition to a name and a description. Stat names and descriptions should typically be set from the constructor usingo from the constructor using the ADD_STAT macro.

Reimplemented from Stats::Group.

Definition at line 663 of file gpu_tlb.cc.

References accessCycles, avgReuseDistance, Stats::DataWrap< Derived, InfoProxyType >::desc(), globalNumTLBAccesses, globalNumTLBHits, globalNumTLBMisses, globalTLBMissRate, localCycles, localLatency, localNumTLBAccesses, localNumTLBHits, localNumTLBMisses, localTLBMissRate, SimObject::name(), Stats::DataWrap< Derived, InfoProxyType >::name(), numUniquePages, pageTableCycles, and Stats::Group::regStats().

◆ serialize()

void X86ISA::GpuTLB::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 653 of file gpu_tlb.cc.

◆ setConfigAddress()

void X86ISA::GpuTLB::setConfigAddress ( uint32_t addr )

Definition at line 242 of file gpu_tlb.cc.

References X86ISA::addr, and configAddress.

◆ tlbLookup()

bool X86ISA::GpuTLB::tlbLookup	(	const RequestPtr &	req,
		ThreadContext *	tc,
		bool	update_stats
	)

TLB_lookup will only perform a TLB lookup returning true on a TLB hit and false on a TLB miss.

Many of the checks about different modes have been converted to assertions, since these parts of the code are not really used. On a hit it will update the LRU stack.

Definition at line 370 of file gpu_tlb.cc.

References DPRINTF, localNumTLBAccesses, localNumTLBHits, localNumTLBMisses, lookup(), X86ISA::MISCREG_M5_REG, ThreadContext::readMiscRegNoEffect(), X86ISA::seg, X86ISA::SEGMENT_REG_MS, X86ISA::SegmentFlagMask, and MipsISA::vaddr.

Referenced by issueTLBLookup().

◆ translate()

Fault X86ISA::GpuTLB::translate	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		bool &	delayedResponse,
		bool	timing,
		int &	latency
	)

protected

Definition at line 419 of file gpu_tlb.cc.

References X86ISA::AddrSizeFlagBit, ArmISA::attr, X86ISA::base, bits(), ThreadContext::contextId(), X86ISA::CPL0FlagBit, DPRINTF, BaseTLB::Execute, X86ISA::expandDown, fatal, X86ISA::FlagShift, FullSystem, ThreadContext::getProcessPtr(), hitLatency, insert(), ThreadContext::instAddr(), X86ISA::limit, localNumTLBAccesses, localNumTLBHits, localNumTLBMisses, lookup(), X86ISA::MISCREG_APIC_BASE, X86ISA::MISCREG_CR0, X86ISA::MISCREG_CS_ATTR, X86ISA::MISCREG_M5_REG, X86ISA::MISCREG_SEG_ATTR(), X86ISA::MISCREG_SEG_BASE(), X86ISA::MISCREG_SEG_LIMIT(), X86ISA::MISCREG_SEG_SEL(), missLatency1, missLatency2, ArmISA::mode, NoFault, X86ISA::offset, X86ISA::p, EmulationPageTable::Entry::paddr, X86ISA::TlbEntry::paddr, X86ISA::PageBytes, BaseTLB::Read, ThreadContext::readMiscRegNoEffect(), X86ISA::seg, X86ISA::SEGMENT_REG_ES, X86ISA::SEGMENT_REG_HS, X86ISA::SEGMENT_REG_LS, X86ISA::SEGMENT_REG_MS, X86ISA::SEGMENT_REG_TSG, X86ISA::SegmentFlagMask, X86ISA::TlbEntry::size(), size, X86ISA::StoreCheck, X86ISA::SYS_SEGMENT_REG_IDTR, translateInt(), X86ISA::TlbEntry::uncacheable, Request::UNCACHEABLE, X86ISA::TlbEntry::user, MipsISA::vaddr, warn_once, X86ISA::TlbEntry::writable, BaseTLB::Write, and X86ISA::x86LocalAPICAddress().

Referenced by translateAtomic(), and translateTiming().

◆ translateAtomic()

Fault X86ISA::GpuTLB::translateAtomic	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		int &	latency
	)

Definition at line 622 of file gpu_tlb.cc.

References ArmISA::mode, and translate().

◆ translateInt()

Fault X86ISA::GpuTLB::translateInt	(	bool	read,
		const RequestPtr &	req,
		ThreadContext *	tc
	)

protected

Definition at line 301 of file gpu_tlb.cc.

References bits(), configAddress, DPRINTF, X86ISA::IntAddrPrefixCPUID, X86ISA::IntAddrPrefixIO, X86ISA::IntAddrPrefixMask, X86ISA::IntAddrPrefixMSR, X86ISA::mask, mbits(), X86ISA::MISCREG_PCI_CONFIG_ADDRESS, X86ISA::msrAddrToIndex(), NoFault, panic, X86ISA::PhysAddrPrefixIO, X86ISA::PhysAddrPrefixPciConfig, ThreadContext::readMiscRegNoEffect(), Request::STRICT_ORDER, Request::UNCACHEABLE, and MipsISA::vaddr.

Referenced by translate().

◆ translateTiming()

void X86ISA::GpuTLB::translateTiming	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		int &	latency
	)

Definition at line 632 of file gpu_tlb.cc.

References X86ISA::GpuTLB::Translation::finish(), ArmISA::mode, and translate().

◆ translationReturn()

void X86ISA::GpuTLB::translationReturn	(	Addr	virtPageAddr,
		tlbOutcome	outcome,
		PacketPtr	pkt
	)

A TLBEvent is scheduled after the TLB lookup and helps us take the appropriate actions: (e.g., update TLB on a hit, send request to lower level TLB on a miss, or start a page walk if this was the last-level TLB).

Here we take the appropriate actions based on the result of the TLB lookup.

There is a TLB below. Send the coalesced request. We actually send the very first packet of all the pending packets for this virtual page address.

we add an extra cycle in the return path of the translation requests in between the various TLB levels.

Definition at line 965 of file gpu_tlb.cc.

References accessCycles, curTick(), Clocked::cyclesToTicks(), DPRINTF, BaseTLB::Execute, ThreadContext::getProcessPtr(), handleTranslationReturn(), hasMemSidePort, localCycles, memSidePort, MISS_RETURN, missLatency2, X86ISA::p, EmulationPageTable::Entry::paddr, PAGE_WALK, pageTableCycles, panic, X86ISA::GpuTLB::TranslationState::prefetch, Packet::req, X86ISA::GpuTLB::TranslationState::reqCnt, EventManager::schedule(), Packet::senderState, X86ISA::GpuTLB::TranslationState::tc, TLB_HIT, TLB_MISS, X86ISA::GpuTLB::TranslationState::tlbEntry, X86ISA::GpuTLB::TranslationState::tlbMode, translationReturnEvent, X86ISA::GpuTLB::TLBEvent::updateOutcome(), and MipsISA::vaddr.

◆ unserialize()

void X86ISA::GpuTLB::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 658 of file gpu_tlb.cc.

◆ updatePageFootprint()

void X86ISA::GpuTLB::updatePageFootprint ( Addr virt_page_addr )

Definition at line 1390 of file gpu_tlb.cc.

References accessDistance, X86ISA::GpuTLB::AccessInfo::accessesPerPage, curTick(), X86ISA::GpuTLB::AccessInfo::lastTimeAccessed, localNumTLBAccesses, X86ISA::GpuTLB::AccessInfo::meanDistance, numUniquePages, X86ISA::GpuTLB::AccessInfo::sumDistance, TLBFootprint, X86ISA::GpuTLB::AccessInfo::totalReuseDistance, and Stats::ScalarBase< Derived, Stor >::value().

Referenced by issueTLBLookup().

◆ updatePhysAddresses()

void X86ISA::GpuTLB::updatePhysAddresses	(	Addr	virt_page_addr,
		TlbEntry *	tlb_entry,
		Addr	phys_page_addr
	)

Friends And Related Function Documentation

◆ Walker

friend class Walker

friend

Definition at line 66 of file gpu_tlb.hh.

Member Data Documentation

◆ accessCycles

Stats::Scalar X86ISA::GpuTLB::accessCycles

Definition at line 188 of file gpu_tlb.hh.

Referenced by issueTLBLookup(), regStats(), and translationReturn().

◆ accessDistance

bool X86ISA::GpuTLB::accessDistance

protected

Print out accessDistance stats.

One stat file per TLB.

Definition at line 139 of file gpu_tlb.hh.

Referenced by exitCallback(), and updatePageFootprint().

◆ allocationPolicy

bool X86ISA::GpuTLB::allocationPolicy

protected

Allocation Policy: true if we always allocate on a hit, false otherwise.

Default is true.

Definition at line 128 of file gpu_tlb.hh.

Referenced by handleFuncTranslationReturn(), and handleTranslationReturn().

◆ assoc

int X86ISA::GpuTLB::assoc

protected

Definition at line 115 of file gpu_tlb.hh.

◆ avgReuseDistance

Stats::Scalar X86ISA::GpuTLB::avgReuseDistance

Definition at line 198 of file gpu_tlb.hh.

Referenced by exitCallback(), and regStats().

◆ cleanupEvent

EventFunctionWrapper X86ISA::GpuTLB::cleanupEvent

Definition at line 395 of file gpu_tlb.hh.

Referenced by handleTranslationReturn().

◆ cleanupQueue

std::queue<Addr> X86ISA::GpuTLB::cleanupQueue

Definition at line 389 of file gpu_tlb.hh.

Referenced by cleanup(), and handleTranslationReturn().

◆ configAddress

uint32_t X86ISA::GpuTLB::configAddress

protected

Definition at line 70 of file gpu_tlb.hh.

Referenced by setConfigAddress(), and translateInt().

◆ cpuSidePort

std::vector<CpuSidePort*> X86ISA::GpuTLB::cpuSidePort

Definition at line 287 of file gpu_tlb.hh.

Referenced by cleanup(), getPort(), and handleTranslationReturn().

◆ entryList

std::vector<EntryList> X86ISA::GpuTLB::entryList

protected

An entryList per set is the equivalent of an LRU stack; it's used to guide replacement decisions.

The head of the list contains the MRU TLB entry of the given set. If the freeList for this set is empty, the last element of the list is evicted (i.e., dropped on the floor).

Definition at line 157 of file gpu_tlb.hh.

Referenced by demapPage(), insert(), invalidateAll(), invalidateNonGlobal(), lookup(), and lookupIt().

◆ exitEvent

EventFunctionWrapper X86ISA::GpuTLB::exitEvent

Definition at line 428 of file gpu_tlb.hh.

◆ FA

bool X86ISA::GpuTLB::FA

protected

true if this is a fully-associative TLB

Definition at line 121 of file gpu_tlb.hh.

Referenced by lookupIt().

◆ freeList

std::vector<EntryList> X86ISA::GpuTLB::freeList

protected

Definition at line 148 of file gpu_tlb.hh.

Referenced by demapPage(), insert(), invalidateAll(), and invalidateNonGlobal().

◆ globalNumTLBAccesses

Stats::Scalar X86ISA::GpuTLB::globalNumTLBAccesses

Definition at line 182 of file gpu_tlb.hh.

Referenced by issueTLBLookup(), and regStats().

◆ globalNumTLBHits

Stats::Scalar X86ISA::GpuTLB::globalNumTLBHits

Definition at line 183 of file gpu_tlb.hh.

Referenced by issueTLBLookup(), and regStats().

◆ globalNumTLBMisses

Stats::Scalar X86ISA::GpuTLB::globalNumTLBMisses

Definition at line 184 of file gpu_tlb.hh.

Referenced by issueTLBLookup(), and regStats().

◆ globalTLBMissRate

Stats::Formula X86ISA::GpuTLB::globalTLBMissRate

Definition at line 185 of file gpu_tlb.hh.

Referenced by regStats().

◆ hasMemSidePort

bool X86ISA::GpuTLB::hasMemSidePort

protected

if true, then this is not the last level TLB

Definition at line 133 of file gpu_tlb.hh.

Referenced by getPort(), and translationReturn().

◆ hitLatency

int X86ISA::GpuTLB::hitLatency

Definition at line 168 of file gpu_tlb.hh.

Referenced by issueTLBLookup(), and translate().

◆ localCycles

Stats::Scalar X86ISA::GpuTLB::localCycles

Definition at line 193 of file gpu_tlb.hh.

Referenced by issueTLBLookup(), regStats(), and translationReturn().

◆ localLatency

Stats::Formula X86ISA::GpuTLB::localLatency

Definition at line 195 of file gpu_tlb.hh.

Referenced by regStats().

◆ localNumTLBAccesses

Stats::Scalar X86ISA::GpuTLB::localNumTLBAccesses

Definition at line 174 of file gpu_tlb.hh.

Referenced by regStats(), tlbLookup(), translate(), and updatePageFootprint().

◆ localNumTLBHits

Stats::Scalar X86ISA::GpuTLB::localNumTLBHits

Definition at line 175 of file gpu_tlb.hh.

Referenced by regStats(), tlbLookup(), and translate().

◆ localNumTLBMisses

Stats::Scalar X86ISA::GpuTLB::localNumTLBMisses

Definition at line 176 of file gpu_tlb.hh.

Referenced by regStats(), tlbLookup(), and translate().

◆ localTLBMissRate

Stats::Formula X86ISA::GpuTLB::localTLBMissRate

Definition at line 177 of file gpu_tlb.hh.

Referenced by regStats().

◆ maxCoalescedReqs

int X86ISA::GpuTLB::maxCoalescedReqs

Definition at line 346 of file gpu_tlb.hh.

◆ memSidePort

std::vector<MemSidePort*> X86ISA::GpuTLB::memSidePort

Definition at line 289 of file gpu_tlb.hh.

Referenced by getPort(), and translationReturn().

◆ missLatency1

int X86ISA::GpuTLB::missLatency1

Definition at line 169 of file gpu_tlb.hh.

Referenced by translate().

◆ missLatency2

int X86ISA::GpuTLB::missLatency2

Definition at line 170 of file gpu_tlb.hh.

Referenced by translate(), and translationReturn().

◆ numSets

int X86ISA::GpuTLB::numSets

protected

Definition at line 116 of file gpu_tlb.hh.

Referenced by invalidateAll(), and invalidateNonGlobal().

◆ numUniquePages

Stats::Scalar X86ISA::GpuTLB::numUniquePages

Definition at line 191 of file gpu_tlb.hh.

Referenced by regStats(), and updatePageFootprint().

◆ outstandingReqs

int X86ISA::GpuTLB::outstandingReqs

Definition at line 350 of file gpu_tlb.hh.

Referenced by cleanup().

◆ pageTableCycles

Stats::Scalar X86ISA::GpuTLB::pageTableCycles

Definition at line 190 of file gpu_tlb.hh.

Referenced by regStats(), and translationReturn().

◆ setMask

Addr X86ISA::GpuTLB::setMask

protected

Definition at line 122 of file gpu_tlb.hh.

Referenced by demapPage(), insert(), lookup(), and lookupIt().

◆ size

int X86ISA::GpuTLB::size

protected

Definition at line 114 of file gpu_tlb.hh.

Referenced by translate().

◆ tlb

std::vector<TlbEntry> X86ISA::GpuTLB::tlb

protected

Definition at line 141 of file gpu_tlb.hh.

Referenced by X86ISA::GpuTLB::TLBEvent::process(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), X86ISA::GpuTLB::CpuSidePort::recvTimingReq(), and X86ISA::GpuTLB::MemSidePort::recvTimingResp().

◆ TLBFootprint

AccessPatternTable X86ISA::GpuTLB::TLBFootprint

Definition at line 423 of file gpu_tlb.hh.

Referenced by exitCallback(), and updatePageFootprint().

◆ translationReturnEvent

std::unordered_map<Addr, TLBEvent*> X86ISA::GpuTLB::translationReturnEvent

Definition at line 385 of file gpu_tlb.hh.

Referenced by cleanup(), issueTLBLookup(), translationReturn(), and ~GpuTLB().

◆ walker

Walker* X86ISA::GpuTLB::walker

protected

Definition at line 105 of file gpu_tlb.hh.

Referenced by getWalker().

The documentation for this class was generated from the following files:

gpu-compute/gpu_tlb.hh
gpu-compute/gpu_tlb.cc

Classes

Public Types

Public Member Functions

Public Attributes

Protected Types

Protected Member Functions

Protected Attributes

Friends

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ AccessPatternTable

◆ EntryList

◆ Mode

◆ Params

Member Enumeration Documentation

◆ tlbOutcome

Constructor & Destructor Documentation

◆ GpuTLB()

◆ ~GpuTLB()

Member Function Documentation

◆ cleanup()

◆ demapPage()

◆ doMmuRegRead()

◆ doMmuRegWrite()

◆ dumpAll()

◆ exitCallback()

◆ getPort()

◆ getWalker()

◆ handleFuncTranslationReturn()

◆ handleTranslationReturn()

◆ insert()

◆ invalidateAll()

◆ invalidateNonGlobal()

◆ issueTLBLookup()

◆ issueTranslation()

◆ lookup()

◆ lookupIt()

◆ pagingProtectionChecks()

◆ printAccessPattern()

◆ regStats()

◆ serialize()

◆ setConfigAddress()

◆ tlbLookup()

◆ translate()

◆ translateAtomic()

◆ translateInt()

◆ translateTiming()

◆ translationReturn()

◆ unserialize()

◆ updatePageFootprint()

◆ updatePhysAddresses()

Friends And Related Function Documentation

◆ Walker

Member Data Documentation

◆ accessCycles

◆ accessDistance

◆ allocationPolicy

◆ assoc

◆ avgReuseDistance

◆ cleanupEvent

◆ cleanupQueue

◆ configAddress

◆ cpuSidePort

◆ entryList

◆ exitEvent

◆ FA

◆ freeList

◆ globalNumTLBAccesses

◆ globalNumTLBHits

◆ globalNumTLBMisses

◆ globalTLBMissRate

◆ hasMemSidePort

◆ hitLatency

◆ localCycles

◆ localLatency

◆ localNumTLBAccesses

◆ localNumTLBHits

◆ localNumTLBMisses

◆ localTLBMissRate