|
gem5
v20.1.0.0
|
Go to the source code of this file.
Macros | |
| #define | WDCTL_4BIT 0x08 /* use four head bits (wd1003) */ |
| #define | WDCTL_RST 0x04 /* reset the controller */ |
| #define | WDCTL_IDS 0x02 /* disable controller interrupts */ |
| #define | WDCS_BSY 0x80 /* busy */ |
| #define | WDCS_DRDY 0x40 /* drive ready */ |
| #define | WDCS_DWF 0x20 /* drive write fault */ |
| #define | WDCS_DSC 0x10 /* drive seek complete */ |
| #define | WDCS_DRQ 0x08 /* data request */ |
| #define | WDCS_CORR 0x04 /* corrected data */ |
| #define | WDCS_IDX 0x02 /* index */ |
| #define | WDCS_ERR 0x01 /* error */ |
| #define | WDCS_BITS "\020\010BSY\007DRDY\006DWF\005DSC\004DRQ\003CORR\002IDX\001ERR" |
| #define | WDCE_BBK 0x80 /* bad block detected */ |
| #define | WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ |
| #define | WDCE_UNC 0x40 /* uncorrectable data error */ |
| #define | WDCE_MC 0x20 /* media changed */ |
| #define | WDCE_IDNF 0x10 /* id not found */ |
| #define | WDCE_MCR 0x08 /* media change requested */ |
| #define | WDCE_ABRT 0x04 /* aborted command */ |
| #define | WDCE_TK0NF 0x02 /* track 0 not found */ |
| #define | WDCE_AMNF 0x01 /* address mark not found */ |
| #define | WDCC_NOP 0x00 /* NOP - Always fail with "aborted command" */ |
| #define | WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ |
| #define | WDCC_READ 0x20 /* disk read code */ |
| #define | WDCC_WRITE 0x30 /* disk write code */ |
| #define | WDCC__LONG 0x02 /* modifier -- access ecc bytes */ |
| #define | WDCC__NORETRY 0x01 /* modifier -- no retrys */ |
| #define | WDCC_FORMAT 0x50 /* disk format code */ |
| #define | WDCC_DIAGNOSE 0x90 /* controller diagnostic */ |
| #define | WDCC_IDP 0x91 /* initialize drive parameters */ |
| #define | WDCC_READMULTI 0xc4 /* read multiple */ |
| #define | WDCC_WRITEMULTI 0xc5 /* write multiple */ |
| #define | WDCC_SETMULTI 0xc6 /* set multiple mode */ |
| #define | WDCC_READDMA 0xc8 /* read with DMA */ |
| #define | WDCC_WRITEDMA 0xca /* write with DMA */ |
| #define | WDCC_ACKMC 0xdb /* acknowledge media change */ |
| #define | WDCC_LOCK 0xde /* lock drawer */ |
| #define | WDCC_UNLOCK 0xdf /* unlock drawer */ |
| #define | WDCC_FLUSHCACHE 0xe7 /* Flush cache */ |
| #define | WDCC_IDENTIFY 0xec /* read parameters from controller */ |
| #define | SET_FEATURES 0xef /* set features */ |
| #define | WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ |
| #define | WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ |
| #define | WDCC_SLEEP 0xe6 /* enter sleep mode */ |
| #define | WDCC_STANDBY 0xe2 /* set standby timer & enter standby mode */ |
| #define | WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ |
| #define | WDCC_CHECK_PWR 0xe5 /* check power mode */ |
| #define | WDCC_READ_EXT 0x24 /* read 48-bit addressing */ |
| #define | WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ |
| #define | WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ |
| #define | WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ |
| #define | WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ |
| #define | WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ |
| #define | WDCC_FLUSHCACHE_EXT 0xea /* 48-bit addressing flush cache */ |
| #define | WDSF_8BIT_PIO_EN 0x01 /* Enable 8bit PIO (CFA featureset) */ |
| #define | WDSF_EN_WR_CACHE 0x02 |
| #define | WDSF_SET_MODE 0x03 |
| #define | WDSF_REASSIGN_EN 0x04 /* Obsolete in ATA-6 */ |
| #define | WDSF_APM_EN 0x05 /* Enable Adv. Power Management */ |
| #define | WDSF_PUIS_EN 0x06 /* Enable Power-Up In Standby */ |
| #define | WDSF_PUIS_SPINUP 0x07 /* Power-Up In Standby spin-up */ |
| #define | WDSF_CFA_MODE1_EN 0x0A /* Enable CFA power mode 1 */ |
| #define | WDSF_RMSN_DS 0x31 /* Disable Removable Media Status */ |
| #define | WDSF_RETRY_DS 0x33 /* Obsolete in ATA-6 */ |
| #define | WDSF_AAM_EN 0x42 /* Enable Autom. Acoustic Management */ |
| #define | WDSF_SET_CACHE_SGMT 0x54 /* Obsolete in ATA-6 */ |
| #define | WDSF_READAHEAD_DS 0x55 /* Disable read look-ahead */ |
| #define | WDSF_RLSE_EN 0x5D /* Enable release interrupt */ |
| #define | WDSF_SRV_EN 0x5E /* Enable SERVICE interrupt */ |
| #define | WDSF_POD_DS 0x66 |
| #define | WDSF_ECC_DS 0x77 |
| #define | WDSF_8BIT_PIO_DS 0x81 /* Disable 8bit PIO (CFA featureset) */ |
| #define | WDSF_WRITE_CACHE_DS 0x82 |
| #define | WDSF_REASSIGN_DS 0x84 |
| #define | WDSF_APM_DS 0x85 /* Disable Adv. Power Management */ |
| #define | WDSF_PUIS_DS 0x86 /* Disable Power-Up In Standby */ |
| #define | WDSF_ECC_EN 0x88 |
| #define | WDSF_CFA_MODE1_DS 0x8A /* Disable CFA power mode 1 */ |
| #define | WDSF_RMSN_EN 0x95 /* Enable Removable Media Status */ |
| #define | WDSF_RETRY_EN 0x99 /* Obsolete in ATA-6 */ |
| #define | WDSF_SET_CURRENT 0x9A /* Obsolete in ATA-6 */ |
| #define | WDSF_READAHEAD_EN 0xAA |
| #define | WDSF_PREFETCH_SET 0xAB /* Obsolete in ATA-6 */ |
| #define | WDSF_AAM_DS 0xC2 /* Disable Autom. Acoustic Management */ |
| #define | WDSF_POD_EN 0xCC |
| #define | WDSF_RLSE_DS 0xDD /* Disable release interrupt */ |
| #define | WDSF_SRV_DS 0xDE /* Disable SERVICE interrupt */ |
| #define | WDSF_READ_NATIVE_MAX 0xF8 |
| #define | WDSF_SEEK 0x70 |
| #define | WDSF_VERIFY 0x40 |
| #define | WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ |
| #define | WDSD_CHS 0x00 /* cylinder/head/sector addressing */ |
| #define | WDSD_LBA 0x40 /* logical block addressing */ |
| #define | ATAPI_CHECK_POWER_MODE 0xe5 |
| #define | ATAPI_EXEC_DRIVE_DIAGS 0x90 |
| #define | ATAPI_IDLE_IMMEDIATE 0xe1 |
| #define | ATAPI_NOP 0x00 |
| #define | ATAPI_PKT_CMD 0xa0 |
| #define | ATAPI_IDENTIFY_DEVICE 0xa1 |
| #define | ATAPI_SOFT_RESET 0x08 |
| #define | ATAPI_DEVICE_RESET 0x08 /* ATA/ATAPI-5 name for soft reset */ |
| #define | ATAPI_SLEEP 0xe6 |
| #define | ATAPI_STANDBY_IMMEDIATE 0xe0 |
| #define | ATAPI_SMART 0xB0 /* SMART operations */ |
| #define | ATAPI_SETMAX 0xF9 /* Set Max Address */ |
| #define | ATAPI_WRITEEXT 0x34 /* Write sectors Ext */ |
| #define | ATAPI_SETMAXEXT 0x37 /* Set Max Address Ext */ |
| #define | ATAPI_WRITEMULTIEXT 0x39 /* Write Multi Ext */ |
| #define | ATAPI_PKT_CMD_FTRE_DMA 0x01 |
| #define | ATAPI_PKT_CMD_FTRE_OVL 0x02 |
| #define | WDCI_CMD 0x01 /* command(1) or data(0) */ |
| #define | WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ |
| #define | WDCI_RELEASE 0x04 /* bus released until completion */ |
| #define | PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) |
| #define | PHASE_DATAIN (WDCS_DRQ | WDCI_IN) |
| #define | PHASE_DATAOUT WDCS_DRQ |
| #define | PHASE_COMPLETED (WDCI_IN | WDCI_CMD) |
| #define | PHASE_ABORTED 0 |
| #define ATAPI_CHECK_POWER_MODE 0xe5 |
Definition at line 166 of file ide_wdcreg.h.
| #define ATAPI_DEVICE_RESET 0x08 /* ATA/ATAPI-5 name for soft reset */ |
Definition at line 173 of file ide_wdcreg.h.
| #define ATAPI_EXEC_DRIVE_DIAGS 0x90 |
Definition at line 167 of file ide_wdcreg.h.
| #define ATAPI_IDENTIFY_DEVICE 0xa1 |
Definition at line 171 of file ide_wdcreg.h.
| #define ATAPI_IDLE_IMMEDIATE 0xe1 |
Definition at line 168 of file ide_wdcreg.h.
| #define ATAPI_NOP 0x00 |
Definition at line 169 of file ide_wdcreg.h.
| #define ATAPI_PKT_CMD 0xa0 |
Definition at line 170 of file ide_wdcreg.h.
| #define ATAPI_PKT_CMD_FTRE_DMA 0x01 |
Definition at line 183 of file ide_wdcreg.h.
| #define ATAPI_PKT_CMD_FTRE_OVL 0x02 |
Definition at line 184 of file ide_wdcreg.h.
| #define ATAPI_SETMAX 0xF9 /* Set Max Address */ |
Definition at line 177 of file ide_wdcreg.h.
| #define ATAPI_SETMAXEXT 0x37 /* Set Max Address Ext */ |
Definition at line 179 of file ide_wdcreg.h.
| #define ATAPI_SLEEP 0xe6 |
Definition at line 174 of file ide_wdcreg.h.
| #define ATAPI_SMART 0xB0 /* SMART operations */ |
Definition at line 176 of file ide_wdcreg.h.
| #define ATAPI_SOFT_RESET 0x08 |
Definition at line 172 of file ide_wdcreg.h.
| #define ATAPI_STANDBY_IMMEDIATE 0xe0 |
Definition at line 175 of file ide_wdcreg.h.
| #define ATAPI_WRITEEXT 0x34 /* Write sectors Ext */ |
Definition at line 178 of file ide_wdcreg.h.
| #define ATAPI_WRITEMULTIEXT 0x39 /* Write Multi Ext */ |
Definition at line 180 of file ide_wdcreg.h.
| #define PHASE_ABORTED 0 |
Definition at line 195 of file ide_wdcreg.h.
Definition at line 191 of file ide_wdcreg.h.
Definition at line 194 of file ide_wdcreg.h.
Definition at line 192 of file ide_wdcreg.h.
| #define PHASE_DATAOUT WDCS_DRQ |
Definition at line 193 of file ide_wdcreg.h.
| #define SET_FEATURES 0xef /* set features */ |
Definition at line 102 of file ide_wdcreg.h.
| #define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ |
Definition at line 82 of file ide_wdcreg.h.
| #define WDCC__NORETRY 0x01 /* modifier -- no retrys */ |
Definition at line 83 of file ide_wdcreg.h.
| #define WDCC_ACKMC 0xdb /* acknowledge media change */ |
Definition at line 96 of file ide_wdcreg.h.
| #define WDCC_CHECK_PWR 0xe5 /* check power mode */ |
Definition at line 109 of file ide_wdcreg.h.
| #define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ |
Definition at line 86 of file ide_wdcreg.h.
| #define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ |
Definition at line 100 of file ide_wdcreg.h.
| #define WDCC_FLUSHCACHE_EXT 0xea /* 48-bit addressing flush cache */ |
Definition at line 120 of file ide_wdcreg.h.
| #define WDCC_FORMAT 0x50 /* disk format code */ |
Definition at line 85 of file ide_wdcreg.h.
| #define WDCC_IDENTIFY 0xec /* read parameters from controller */ |
Definition at line 101 of file ide_wdcreg.h.
| #define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ |
Definition at line 104 of file ide_wdcreg.h.
| #define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ |
Definition at line 105 of file ide_wdcreg.h.
| #define WDCC_IDP 0x91 /* initialize drive parameters */ |
Definition at line 87 of file ide_wdcreg.h.
| #define WDCC_LOCK 0xde /* lock drawer */ |
Definition at line 97 of file ide_wdcreg.h.
| #define WDCC_NOP 0x00 /* NOP - Always fail with "aborted command" */ |
Definition at line 77 of file ide_wdcreg.h.
| #define WDCC_READ 0x20 /* disk read code */ |
Definition at line 80 of file ide_wdcreg.h.
| #define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ |
Definition at line 111 of file ide_wdcreg.h.
| #define WDCC_READDMA 0xc8 /* read with DMA */ |
Definition at line 93 of file ide_wdcreg.h.
| #define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ |
Definition at line 117 of file ide_wdcreg.h.
| #define WDCC_READMULTI 0xc4 /* read multiple */ |
Definition at line 89 of file ide_wdcreg.h.
| #define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ |
Definition at line 114 of file ide_wdcreg.h.
| #define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ |
Definition at line 78 of file ide_wdcreg.h.
| #define WDCC_SETMULTI 0xc6 /* set multiple mode */ |
Definition at line 91 of file ide_wdcreg.h.
| #define WDCC_SLEEP 0xe6 /* enter sleep mode */ |
Definition at line 106 of file ide_wdcreg.h.
| #define WDCC_STANDBY 0xe2 /* set standby timer & enter standby mode */ |
Definition at line 107 of file ide_wdcreg.h.
| #define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ |
Definition at line 108 of file ide_wdcreg.h.
| #define WDCC_UNLOCK 0xdf /* unlock drawer */ |
Definition at line 98 of file ide_wdcreg.h.
| #define WDCC_WRITE 0x30 /* disk write code */ |
Definition at line 81 of file ide_wdcreg.h.
| #define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ |
Definition at line 112 of file ide_wdcreg.h.
| #define WDCC_WRITEDMA 0xca /* write with DMA */ |
Definition at line 94 of file ide_wdcreg.h.
| #define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ |
Definition at line 118 of file ide_wdcreg.h.
| #define WDCC_WRITEMULTI 0xc5 /* write multiple */ |
Definition at line 90 of file ide_wdcreg.h.
| #define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ |
Definition at line 115 of file ide_wdcreg.h.
| #define WDCE_ABRT 0x04 /* aborted command */ |
Definition at line 70 of file ide_wdcreg.h.
| #define WDCE_AMNF 0x01 /* address mark not found */ |
Definition at line 72 of file ide_wdcreg.h.
| #define WDCE_BBK 0x80 /* bad block detected */ |
Definition at line 64 of file ide_wdcreg.h.
| #define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ |
Definition at line 65 of file ide_wdcreg.h.
| #define WDCE_IDNF 0x10 /* id not found */ |
Definition at line 68 of file ide_wdcreg.h.
| #define WDCE_MC 0x20 /* media changed */ |
Definition at line 67 of file ide_wdcreg.h.
| #define WDCE_MCR 0x08 /* media change requested */ |
Definition at line 69 of file ide_wdcreg.h.
| #define WDCE_TK0NF 0x02 /* track 0 not found */ |
Definition at line 71 of file ide_wdcreg.h.
| #define WDCE_UNC 0x40 /* uncorrectable data error */ |
Definition at line 66 of file ide_wdcreg.h.
| #define WDCI_CMD 0x01 /* command(1) or data(0) */ |
Definition at line 187 of file ide_wdcreg.h.
| #define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ |
Definition at line 188 of file ide_wdcreg.h.
| #define WDCI_RELEASE 0x04 /* bus released until completion */ |
Definition at line 189 of file ide_wdcreg.h.
| #define WDCS_BITS "\020\010BSY\007DRDY\006DWF\005DSC\004DRQ\003CORR\002IDX\001ERR" |
Definition at line 59 of file ide_wdcreg.h.
| #define WDCS_BSY 0x80 /* busy */ |
Definition at line 51 of file ide_wdcreg.h.
| #define WDCS_CORR 0x04 /* corrected data */ |
Definition at line 56 of file ide_wdcreg.h.
| #define WDCS_DRDY 0x40 /* drive ready */ |
Definition at line 52 of file ide_wdcreg.h.
| #define WDCS_DRQ 0x08 /* data request */ |
Definition at line 55 of file ide_wdcreg.h.
| #define WDCS_DSC 0x10 /* drive seek complete */ |
Definition at line 54 of file ide_wdcreg.h.
| #define WDCS_DWF 0x20 /* drive write fault */ |
Definition at line 53 of file ide_wdcreg.h.
| #define WDCS_ERR 0x01 /* error */ |
Definition at line 58 of file ide_wdcreg.h.
| #define WDCS_IDX 0x02 /* index */ |
Definition at line 57 of file ide_wdcreg.h.
| #define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */ |
Definition at line 44 of file ide_wdcreg.h.
| #define WDCTL_IDS 0x02 /* disable controller interrupts */ |
Definition at line 46 of file ide_wdcreg.h.
| #define WDCTL_RST 0x04 /* reset the controller */ |
Definition at line 45 of file ide_wdcreg.h.
| #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ |
Definition at line 162 of file ide_wdcreg.h.
| #define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ |
Definition at line 161 of file ide_wdcreg.h.
| #define WDSD_LBA 0x40 /* logical block addressing */ |
Definition at line 163 of file ide_wdcreg.h.
| #define WDSF_8BIT_PIO_DS 0x81 /* Disable 8bit PIO (CFA featureset) */ |
Definition at line 140 of file ide_wdcreg.h.
| #define WDSF_8BIT_PIO_EN 0x01 /* Enable 8bit PIO (CFA featureset) */ |
Definition at line 123 of file ide_wdcreg.h.
| #define WDSF_AAM_DS 0xC2 /* Disable Autom. Acoustic Management */ |
Definition at line 152 of file ide_wdcreg.h.
| #define WDSF_AAM_EN 0x42 /* Enable Autom. Acoustic Management */ |
Definition at line 133 of file ide_wdcreg.h.
| #define WDSF_APM_DS 0x85 /* Disable Adv. Power Management */ |
Definition at line 143 of file ide_wdcreg.h.
| #define WDSF_APM_EN 0x05 /* Enable Adv. Power Management */ |
Definition at line 127 of file ide_wdcreg.h.
| #define WDSF_CFA_MODE1_DS 0x8A /* Disable CFA power mode 1 */ |
Definition at line 146 of file ide_wdcreg.h.
| #define WDSF_CFA_MODE1_EN 0x0A /* Enable CFA power mode 1 */ |
Definition at line 130 of file ide_wdcreg.h.
| #define WDSF_ECC_DS 0x77 |
Definition at line 139 of file ide_wdcreg.h.
| #define WDSF_ECC_EN 0x88 |
Definition at line 145 of file ide_wdcreg.h.
| #define WDSF_EN_WR_CACHE 0x02 |
Definition at line 124 of file ide_wdcreg.h.
| #define WDSF_POD_DS 0x66 |
Definition at line 138 of file ide_wdcreg.h.
| #define WDSF_POD_EN 0xCC |
Definition at line 153 of file ide_wdcreg.h.
| #define WDSF_PREFETCH_SET 0xAB /* Obsolete in ATA-6 */ |
Definition at line 151 of file ide_wdcreg.h.
| #define WDSF_PUIS_DS 0x86 /* Disable Power-Up In Standby */ |
Definition at line 144 of file ide_wdcreg.h.
| #define WDSF_PUIS_EN 0x06 /* Enable Power-Up In Standby */ |
Definition at line 128 of file ide_wdcreg.h.
| #define WDSF_PUIS_SPINUP 0x07 /* Power-Up In Standby spin-up */ |
Definition at line 129 of file ide_wdcreg.h.
| #define WDSF_READ_NATIVE_MAX 0xF8 |
Definition at line 156 of file ide_wdcreg.h.
| #define WDSF_READAHEAD_DS 0x55 /* Disable read look-ahead */ |
Definition at line 135 of file ide_wdcreg.h.
| #define WDSF_READAHEAD_EN 0xAA |
Definition at line 150 of file ide_wdcreg.h.
| #define WDSF_REASSIGN_DS 0x84 |
Definition at line 142 of file ide_wdcreg.h.
| #define WDSF_REASSIGN_EN 0x04 /* Obsolete in ATA-6 */ |
Definition at line 126 of file ide_wdcreg.h.
| #define WDSF_RETRY_DS 0x33 /* Obsolete in ATA-6 */ |
Definition at line 132 of file ide_wdcreg.h.
| #define WDSF_RETRY_EN 0x99 /* Obsolete in ATA-6 */ |
Definition at line 148 of file ide_wdcreg.h.
| #define WDSF_RLSE_DS 0xDD /* Disable release interrupt */ |
Definition at line 154 of file ide_wdcreg.h.
| #define WDSF_RLSE_EN 0x5D /* Enable release interrupt */ |
Definition at line 136 of file ide_wdcreg.h.
| #define WDSF_RMSN_DS 0x31 /* Disable Removable Media Status */ |
Definition at line 131 of file ide_wdcreg.h.
| #define WDSF_RMSN_EN 0x95 /* Enable Removable Media Status */ |
Definition at line 147 of file ide_wdcreg.h.
| #define WDSF_SEEK 0x70 |
Definition at line 157 of file ide_wdcreg.h.
| #define WDSF_SET_CACHE_SGMT 0x54 /* Obsolete in ATA-6 */ |
Definition at line 134 of file ide_wdcreg.h.
| #define WDSF_SET_CURRENT 0x9A /* Obsolete in ATA-6 */ |
Definition at line 149 of file ide_wdcreg.h.
| #define WDSF_SET_MODE 0x03 |
Definition at line 125 of file ide_wdcreg.h.
| #define WDSF_SRV_DS 0xDE /* Disable SERVICE interrupt */ |
Definition at line 155 of file ide_wdcreg.h.
| #define WDSF_SRV_EN 0x5E /* Enable SERVICE interrupt */ |
Definition at line 137 of file ide_wdcreg.h.
| #define WDSF_VERIFY 0x40 |
Definition at line 158 of file ide_wdcreg.h.
| #define WDSF_WRITE_CACHE_DS 0x82 |
Definition at line 141 of file ide_wdcreg.h.