gem5  v20.1.0.0
iew.hh
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40 
41 #ifndef __CPU_O3_IEW_HH__
42 #define __CPU_O3_IEW_HH__
43 
44 #include <queue>
45 #include <set>
46 
47 #include "base/statistics.hh"
48 #include "cpu/o3/comm.hh"
49 #include "cpu/o3/lsq.hh"
50 #include "cpu/o3/scoreboard.hh"
51 #include "cpu/timebuf.hh"
52 #include "debug/IEW.hh"
53 #include "sim/probe/probe.hh"
54 
55 struct DerivO3CPUParams;
56 class FUPool;
57 
77 template<class Impl>
79 {
80  private:
81  //Typedefs from Impl
82  typedef typename Impl::CPUPol CPUPol;
83  typedef typename Impl::DynInstPtr DynInstPtr;
84  typedef typename Impl::O3CPU O3CPU;
85 
86  typedef typename CPUPol::IQ IQ;
87  typedef typename CPUPol::RenameMap RenameMap;
88  typedef typename CPUPol::LSQ LSQ;
89 
90  typedef typename CPUPol::TimeStruct TimeStruct;
91  typedef typename CPUPol::IEWStruct IEWStruct;
92  typedef typename CPUPol::RenameStruct RenameStruct;
93  typedef typename CPUPol::IssueStruct IssueStruct;
94 
95  public:
99  enum Status {
102  };
103 
105  enum StageStatus {
112  };
113 
114  private:
118  StageStatus dispatchStatus[Impl::MaxThreads];
123 
131 
132  public:
134  DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
135 
137  std::string name() const;
138 
140  void regStats();
141 
143  void regProbePoints();
144 
146  void startupStage();
147 
149  void clearStates(ThreadID tid);
150 
153 
156 
158  void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
159 
162 
164  void setScoreboard(Scoreboard *sb_ptr);
165 
167  void drainSanityCheck() const;
168 
170  bool isDrained() const;
171 
173  void takeOverFrom();
174 
176  void squash(ThreadID tid);
177 
179  void wakeDependents(const DynInstPtr &inst);
180 
184  void rescheduleMemInst(const DynInstPtr &inst);
185 
187  void replayMemInst(const DynInstPtr &inst);
188 
190  void blockMemInst(const DynInstPtr &inst);
191 
193  void cacheUnblocked();
194 
196  void instToCommit(const DynInstPtr &inst);
197 
199  void skidInsert(ThreadID tid);
200 
202  int skidCount();
203 
205  bool skidsEmpty();
206 
208  void updateStatus();
209 
211  void resetEntries();
212 
216  void wakeCPU();
217 
219  void activityThisCycle();
220 
222  inline void activateStage();
223 
225  inline void deactivateStage();
226 
228  bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
229 
231  bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
232 
234  void checkMisprediction(const DynInstPtr &inst);
235 
236  // hardware transactional memory
237  // For debugging purposes, it is useful to keep track of the most recent
238  // htmUid that has been committed (architecturally, not transactionally)
239  // to ensure that the core and the memory subsystem are observing
240  // correct ordering constraints.
241  void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
242  {
243  ldstQueue.setLastRetiredHtmUid(tid, htmUid);
244  }
245 
246  private:
250  void squashDueToBranch(const DynInstPtr &inst, ThreadID tid);
251 
255  void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid);
256 
258  void block(ThreadID tid);
259 
263  void unblock(ThreadID tid);
264 
266  void dispatch(ThreadID tid);
267 
269  void dispatchInsts(ThreadID tid);
270 
275  void executeInsts();
276 
282  void writebackInsts();
283 
287  unsigned validInstsFromRename();
288 
290  bool checkStall(ThreadID tid);
291 
294 
296  void emptyRenameInsts(ThreadID tid);
297 
299  void sortInsts();
300 
301  public:
305  void tick();
306 
307  private:
309  void updateExeInstStats(const DynInstPtr &inst);
310 
313 
316 
319 
322 
325 
328 
331 
334 
340 
343 
345  std::queue<DynInstPtr> insts[Impl::MaxThreads];
346 
348  std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
349 
352 
353  private:
356 
361 
363  void printAvailableInsts();
364 
365  public:
368 
371 
378 
379  private:
381  bool fetchRedirect[Impl::MaxThreads];
382 
387 
390 
393 
400 
402  unsigned dispatchWidth;
403 
405  unsigned issueWidth;
406 
408  unsigned wbNumInst;
409 
415  unsigned wbCycle;
416 
418  unsigned wbWidth;
419 
422 
425 
427  unsigned skidBufferMax;
428 
459 
465 // Stats::Scalar iewExecStoreInsts;
480 
493 };
494 
495 #endif // __CPU_O3_IEW_HH__
DefaultIEW::wakeCPU
void wakeCPU()
Tells the CPU to wakeup if it has descheduled itself due to no activity.
Definition: iew_impl.hh:879
DefaultIEW::issueToExecQueue
TimeBuffer< IssueStruct > issueToExecQueue
Issue stage queue.
Definition: iew.hh:330
DefaultIEW::wbCycle
unsigned wbCycle
Cycle number within the queue of instructions being written back.
Definition: iew.hh:415
DefaultIEW::iewExecSquashedInsts
Stats::Scalar iewExecSquashedInsts
Stat for total number of executed store instructions.
Definition: iew.hh:467
DefaultIEW::wbRate
Stats::Formula wbRate
Number of instructions per cycle written back.
Definition: iew.hh:490
DefaultIEW::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: iew_impl.hh:432
DefaultIEW::IQ
CPUPol::IQ IQ
Definition: iew.hh:86
DefaultIEW::emptyRenameInsts
void emptyRenameInsts(ThreadID tid)
Removes instructions from rename from a thread's instruction list.
Definition: iew_impl.hh:857
DefaultIEW::checkSignalsAndUpdate
void checkSignalsAndUpdate(ThreadID tid)
Processes inputs and changes state accordingly.
Definition: iew_impl.hh:779
DefaultIEW::wbWidth
unsigned wbWidth
Writeback width.
Definition: iew.hh:418
DefaultIEW::iewDispSquashedInsts
Stats::Scalar iewDispSquashedInsts
Stat for total number of squashed instructions dispatch skips.
Definition: iew.hh:440
DefaultIEW::replayMemInst
void replayMemInst(const DynInstPtr &inst)
Re-executes all rescheduled memory instructions.
Definition: iew_impl.hh:599
DefaultIEW::updateLSQNextCycle
bool updateLSQNextCycle
Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity...
Definition: iew.hh:377
DefaultIEW::TimeStruct
CPUPol::TimeStruct TimeStruct
Definition: iew.hh:90
DefaultIEW::producerInst
Stats::Vector producerInst
Number of instructions that wake consumers.
Definition: iew.hh:486
DefaultIEW::predictedTakenIncorrect
Stats::Scalar predictedTakenIncorrect
Stat for total number of incorrect predicted taken branches.
Definition: iew.hh:454
DefaultIEW::activityThisCycle
void activityThisCycle()
Reports to the CPU that there is activity this cycle.
Definition: iew_impl.hh:886
ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
DefaultIEW::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: iew_impl.hh:376
DefaultIEW::iewExecutedNop
Stats::Vector iewExecutedNop
Number of executed nops.
Definition: iew.hh:471
DefaultIEW::memOrderViolationEvents
Stats::Scalar memOrderViolationEvents
Stat for total number of memory ordering violation events.
Definition: iew.hh:452
DefaultIEW::regStats
void regStats()
Registers statistics.
Definition: iew_impl.hh:144
DefaultIEW::updateExeInstStats
void updateExeInstStats(const DynInstPtr &inst)
Updates execution stats based on the instruction.
Definition: iew_impl.hh:1645
DefaultIEW::setScoreboard
void setScoreboard(Scoreboard *sb_ptr)
Sets pointer to the scoreboard.
Definition: iew_impl.hh:386
DefaultIEW::wroteToTimeBuffer
bool wroteToTimeBuffer
Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if th...
Definition: iew.hh:360
DefaultIEW::commitToIEWDelay
Cycles commitToIEWDelay
Commit to IEW delay.
Definition: iew.hh:389
DefaultIEW::StageStatus
StageStatus
Status for Issue, Execute, and Writeback stages.
Definition: iew.hh:105
DefaultIEW::iewExecStoreInsts
Stats::Formula iewExecStoreInsts
Number of executed store instructions.
Definition: iew.hh:477
ProbePointArg< DynInstPtr >
DefaultIEW::renameQueue
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface.
Definition: iew.hh:324
DefaultIEW::isDrained
bool isDrained() const
Has the stage drained?
Definition: iew_impl.hh:393
DefaultIEW::writebackInsts
void writebackInsts()
Writebacks instructions.
Definition: iew_impl.hh:1465
DefaultIEW::name
std::string name() const
Returns the name of the DefaultIEW stage.
Definition: iew_impl.hh:117
LSQ::setLastRetiredHtmUid
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
Definition: lsq.hh:997
DefaultIEW::wakeDependents
void wakeDependents(const DynInstPtr &inst)
Wakes all dependents of a completed instruction.
Definition: iew_impl.hh:585
DefaultIEW::skidCount
int skidCount()
Returns the max of the number of entries in all of the skid buffers.
Definition: iew_impl.hh:685
DefaultIEW::toCommit
TimeBuffer< IEWStruct >::wire toCommit
Wire to write infromation heading to commit.
Definition: iew.hh:342
DefaultIEW::RenameStruct
CPUPol::RenameStruct RenameStruct
Definition: iew.hh:92
FUPool
Pool of FU's, specific to the new CPU model.
Definition: fu_pool.hh:69
DefaultIEW::squashDueToBranch
void squashDueToBranch(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a branch mispredict.
Definition: iew_impl.hh:496
Stats::Vector
A vector of scalar stats.
Definition: statistics.hh:2575
DefaultIEW::executeInsts
void executeInsts()
Executes instructions.
Definition: iew_impl.hh:1218
DefaultIEW::Inactive
@ Inactive
Definition: iew.hh:101
TimeBuffer< TimeStruct >
DefaultIEW::blockMemInst
void blockMemInst(const DynInstPtr &inst)
Moves memory instruction onto the list of cache blocked instructions.
Definition: iew_impl.hh:606
DefaultIEW::DynInstPtr
Impl::DynInstPtr DynInstPtr
Definition: iew.hh:83
DefaultIEW::sortInsts
void sortInsts()
Sorts instructions coming from rename into lists separated by thread.
Definition: iew_impl.hh:843
DefaultIEW::toRename
TimeBuffer< TimeStruct >::wire toRename
Wire to write information heading to previous stages.
Definition: iew.hh:321
DefaultIEW::checkMisprediction
void checkMisprediction(const DynInstPtr &inst)
Check misprediction
Definition: iew_impl.hh:1677
DefaultIEW::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: iew_impl.hh:325
DefaultIEW::ppMispredict
ProbePointArg< DynInstPtr > * ppMispredict
Probe points.
Definition: iew.hh:125
DefaultIEW::iewInstsToCommit
Stats::Vector iewInstsToCommit
Number of instructions sent to commit.
Definition: iew.hh:482
DefaultIEW::Active
@ Active
Definition: iew.hh:100
timebuf.hh
DefaultIEW::dispatch
void dispatch(ThreadID tid)
Determines proper actions to take given Dispatch's status.
Definition: iew_impl.hh:910
DefaultIEW::block
void block(ThreadID tid)
Sets Dispatch to blocked, and signals back to other stages to block.
Definition: iew_impl.hh:549
DefaultIEW::predictedNotTakenIncorrect
Stats::Scalar predictedNotTakenIncorrect
Stat for total number of incorrect predicted not taken branches.
Definition: iew.hh:456
Stats::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:2533
DefaultIEW::skidInsert
void skidInsert(ThreadID tid)
Inserts unused instructions of a thread into the skid buffer.
Definition: iew_impl.hh:663
DefaultIEW::fromRename
TimeBuffer< RenameStruct >::wire fromRename
Wire to get rename's output from rename queue.
Definition: iew.hh:327
DefaultIEW::branchMispredicts
Stats::Formula branchMispredicts
Stat for total number of mispredicted branches detected at execute.
Definition: iew.hh:458
DefaultIEW::setLastRetiredHtmUid
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
Definition: iew.hh:241
DefaultIEW::ldstQueue
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:370
comm.hh
DefaultIEW::IEWStruct
CPUPol::IEWStruct IEWStruct
Definition: iew.hh:91
DefaultIEW::deactivateStage
void deactivateStage()
Tells CPU that the IEW stage is inactive and idle.
Definition: iew_impl.hh:902
DefaultIEW::skidsEmpty
bool skidsEmpty()
Returns if all of the skid buffers are empty.
Definition: iew_impl.hh:704
DefaultIEW::skidBufferMax
unsigned skidBufferMax
Maximum size of the skid buffer.
Definition: iew.hh:427
DefaultIEW::RenameMap
CPUPol::RenameMap RenameMap
Definition: iew.hh:87
DefaultIEW::squashDueToMemOrder
void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a memory order violation.
Definition: iew_impl.hh:522
DefaultIEW::ppExecute
ProbePointArg< DynInstPtr > * ppExecute
To probe when instruction execution begins.
Definition: iew.hh:128
DefaultIEW::resetEntries
void resetEntries()
Resets entries of the IQ and the LSQ.
DefaultIEW::Running
@ Running
Definition: iew.hh:106
DefaultIEW::iewBlockCycles
Stats::Scalar iewBlockCycles
Stat for total number of blocking cycles.
Definition: iew.hh:434
DefaultIEW::wbFanout
Stats::Formula wbFanout
Average number of woken instructions per writeback.
Definition: iew.hh:492
LSQ
Definition: lsq.hh:62
DefaultIEW::dispatchStatus
StageStatus dispatchStatus[Impl::MaxThreads]
Dispatch status.
Definition: iew.hh:118
DefaultIEW::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: iew_impl.hh:422
DefaultIEW::issueWidth
unsigned issueWidth
Width of issue, in instructions.
Definition: iew.hh:405
DefaultIEW::fetchRedirect
bool fetchRedirect[Impl::MaxThreads]
Records if there is a fetch redirect on this cycle for each thread.
Definition: iew.hh:381
DefaultIEW::exeStatus
StageStatus exeStatus
Execute status.
Definition: iew.hh:120
DefaultIEW::iewExecLoadInsts
Stats::Vector iewExecLoadInsts
Stat for total number of executed load instructions.
Definition: iew.hh:463
DefaultIEW::consumerInst
Stats::Vector consumerInst
Number of instructions that wake up from producers.
Definition: iew.hh:488
DefaultIEW::O3CPU
Impl::O3CPU O3CPU
Definition: iew.hh:84
statistics.hh
DefaultIEW::regProbePoints
void regProbePoints()
Registers probes.
Definition: iew_impl.hh:124
DefaultIEW::iewDispStoreInsts
Stats::Scalar iewDispStoreInsts
Stat for total number of dispatched store instructions.
Definition: iew.hh:444
DefaultIEW::StartSquash
@ StartSquash
Definition: iew.hh:109
DefaultIEW::updateStatus
void updateStatus()
Updates overall IEW status based on all of the stages' statuses.
Definition: iew_impl.hh:721
DefaultIEW::setIEWQueue
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets time buffer to pass on instructions to commit.
Definition: iew_impl.hh:366
DefaultIEW::LSQ
CPUPol::LSQ LSQ
Definition: iew.hh:88
DefaultIEW::Status
Status
Overall IEW stage status.
Definition: iew.hh:99
DefaultIEW::fuPool
FUPool * fuPool
Pointer to the functional unit pool.
Definition: iew.hh:373
DefaultIEW::setRenameQueue
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets time buffer for getting instructions coming from rename.
Definition: iew_impl.hh:356
DefaultIEW::renameToIEWDelay
Cycles renameToIEWDelay
Rename to IEW delay.
Definition: iew.hh:392
DefaultIEW::iewExecutedBranches
Stats::Vector iewExecutedBranches
Number of executed branches.
Definition: iew.hh:475
DefaultIEW::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets main time buffer used for backwards communication.
Definition: iew_impl.hh:338
DefaultIEW::startupStage
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition: iew_impl.hh:303
DefaultIEW::scoreboard
Scoreboard * scoreboard
Scoreboard pointer.
Definition: iew.hh:351
DefaultIEW::iewExecutedInsts
Stats::Scalar iewExecutedInsts
Stat for total number of executed instructions.
Definition: iew.hh:461
DefaultIEW::hasStoresToWB
bool hasStoresToWB(ThreadID tid)
Returns if the LSQ has any stores to writeback.
Definition: iew.hh:231
DefaultIEW::rescheduleMemInst
void rescheduleMemInst(const DynInstPtr &inst)
Tells memory dependence unit that a memory instruction needs to be rescheduled.
Definition: iew_impl.hh:592
DefaultIEW::printAvailableInsts
void printAvailableInsts()
Debug function to print instructions that are issued this cycle.
Definition: iew_impl.hh:1195
DefaultIEW::iewIdleCycles
Stats::Scalar iewIdleCycles
Stat for total number of idle cycles.
Definition: iew.hh:430
DefaultIEW::cpu
O3CPU * cpu
CPU pointer.
Definition: iew.hh:355
DefaultIEW::updatedQueues
bool updatedQueues
Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast th...
Definition: iew.hh:386
DefaultIEW::iewUnblockCycles
Stats::Scalar iewUnblockCycles
Stat for total number of unblocking cycles.
Definition: iew.hh:436
DefaultIEW::iewExecutedRefs
Stats::Vector iewExecutedRefs
Number of executed meomory references.
Definition: iew.hh:473
DefaultIEW::iewSquashCycles
Stats::Scalar iewSquashCycles
Stat for total number of squashing cycles.
Definition: iew.hh:432
DefaultIEW::iewExecRate
Stats::Formula iewExecRate
Number of instructions executed per cycle.
Definition: iew.hh:479
DefaultIEW::iewLSQFullEvents
Stats::Scalar iewLSQFullEvents
Stat for number of times the LSQ becomes full.
Definition: iew.hh:450
DefaultIEW::unblock
void unblock(ThreadID tid)
Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock.
Definition: iew_impl.hh:568
DefaultIEW::squash
void squash(ThreadID tid)
Squashes instructions in IEW for a specific thread.
Definition: iew_impl.hh:460
DefaultIEW::insts
std::queue< DynInstPtr > insts[Impl::MaxThreads]
Queue of all instructions coming from rename this cycle.
Definition: iew.hh:345
DefaultIEW::Squashing
@ Squashing
Definition: iew.hh:110
DefaultIEW::checkStall
bool checkStall(ThreadID tid)
Checks if any of the stall conditions are currently true.
Definition: iew_impl.hh:762
DefaultIEW::iewIQFullEvents
Stats::Scalar iewIQFullEvents
Stat for number of times the IQ becomes full.
Definition: iew.hh:448
DefaultIEW::wbNumInst
unsigned wbNumInst
Index into queue of instructions being written back.
Definition: iew.hh:408
DefaultIEW::activeThreads
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: iew.hh:424
DefaultIEW::numThreads
ThreadID numThreads
Number of active threads.
Definition: iew.hh:421
DefaultIEW::dispatchWidth
unsigned dispatchWidth
Width of dispatch, in instructions.
Definition: iew.hh:402
LSQ::hasStoresToWB
bool hasStoresToWB()
Returns whether or not there are any stores to write back to memory.
Definition: lsq_impl.hh:629
DefaultIEW::toFetch
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
Definition: iew.hh:315
DefaultIEW::issueToExecuteDelay
Cycles issueToExecuteDelay
Issue to execute delay.
Definition: iew.hh:399
DefaultIEW::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
Pointer to main time buffer used for backwards communication.
Definition: iew.hh:312
DefaultIEW::DefaultIEW
DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
Constructs a DefaultIEW with the given parameters.
Definition: iew_impl.hh:66
Stats::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:3037
DefaultIEW::validInstsFromRename
unsigned validInstsFromRename()
Returns the number of valid, non-squashed instructions coming from rename to dispatch.
Definition: iew_impl.hh:649
DefaultIEW::iewQueue
TimeBuffer< IEWStruct > * iewQueue
IEW stage time buffer.
Definition: iew.hh:339
DefaultIEW::Idle
@ Idle
Definition: iew.hh:108
DefaultIEW::iewExecutedSwp
Stats::Vector iewExecutedSwp
Number of executed software prefetches.
Definition: iew.hh:469
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
DefaultIEW::ppToCommit
ProbePointArg< DynInstPtr > * ppToCommit
To probe when instruction execution is complete.
Definition: iew.hh:130
DefaultIEW::writebackCount
Stats::Vector writebackCount
Number of instructions that writeback.
Definition: iew.hh:484
DefaultIEW::CPUPol
Impl::CPUPol CPUPol
Definition: iew.hh:82
DefaultIEW::instQueue
IQ instQueue
Instruction queue.
Definition: iew.hh:367
DefaultIEW::hasStoresToWB
bool hasStoresToWB()
Returns if the LSQ has any stores to writeback.
Definition: iew.hh:228
DefaultIEW::wbStatus
StageStatus wbStatus
Writeback status.
Definition: iew.hh:122
DefaultIEW::instToCommit
void instToCommit(const DynInstPtr &inst)
Sends an instruction to commit through the time buffer.
Definition: iew_impl.hh:620
std::list< ThreadID >
DefaultIEW::activateStage
void activateStage()
Tells CPU that the IEW stage is active and running.
Definition: iew_impl.hh:894
DefaultIEW::IssueStruct
CPUPol::IssueStruct IssueStruct
Definition: iew.hh:93
probe.hh
lsq.hh
DefaultIEW::dispatchInsts
void dispatchInsts(ThreadID tid)
Dispatches instructions to IQ and LSQ.
Definition: iew_impl.hh:958
DefaultIEW::skidBuffer
std::queue< DynInstPtr > skidBuffer[Impl::MaxThreads]
Skid buffer between rename and IEW.
Definition: iew.hh:348
DefaultIEW::ppDispatch
ProbePointArg< DynInstPtr > * ppDispatch
Definition: iew.hh:126
DefaultIEW::_status
Status _status
Overall stage status.
Definition: iew.hh:116
DefaultIEW::iewDispNonSpecInsts
Stats::Scalar iewDispNonSpecInsts
Stat for total number of dispatched non speculative instructions.
Definition: iew.hh:446
scoreboard.hh
DefaultIEW::cacheUnblocked
void cacheUnblocked()
Notifies that the cache has become unblocked.
Definition: iew_impl.hh:613
DefaultIEW::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's output from backwards time buffer.
Definition: iew.hh:318
DefaultIEW::iewDispLoadInsts
Stats::Scalar iewDispLoadInsts
Stat for total number of dispatched load instructions.
Definition: iew.hh:442
DefaultIEW::fromIssue
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
Definition: iew.hh:333
DefaultIEW::Unblocking
@ Unblocking
Definition: iew.hh:111
Scoreboard
Implements a simple scoreboard to track which registers are ready.
Definition: scoreboard.hh:48
DefaultIEW::iewDispatchedInsts
Stats::Scalar iewDispatchedInsts
Stat for total number of instructions dispatched.
Definition: iew.hh:438
DefaultIEW::tick
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
Definition: iew_impl.hh:1515
DefaultIEW::Blocked
@ Blocked
Definition: iew.hh:107
DefaultIEW
DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:78

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