iew.hh

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#ifndef __CPU_O3_IEW_HH__
#define __CPU_O3_IEW_HH__
 
#include <queue>
#include <set>
 
#include "base/statistics.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/lsq.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/timebuf.hh"
#include "debug/IEW.hh"
#include "sim/probe/probe.hh"
 
struct DerivO3CPUParams;
class FUPool;
 
template<class Impl>
class DefaultIEW
{
  private:
    //Typedefs from Impl
    typedef typename Impl::CPUPol CPUPol;
    typedef typename Impl::DynInstPtr DynInstPtr;
    typedef typename Impl::O3CPU O3CPU;
 
    typedef typename CPUPol::IQ IQ;
    typedef typename CPUPol::RenameMap RenameMap;
    typedef typename CPUPol::LSQ LSQ;
 
    typedef typename CPUPol::TimeStruct TimeStruct;
    typedef typename CPUPol::IEWStruct IEWStruct;
    typedef typename CPUPol::RenameStruct RenameStruct;
    typedef typename CPUPol::IssueStruct IssueStruct;
 
  public:
    enum Status {
        Active,
        Inactive
    };
 
    enum StageStatus {
        Running,
        Blocked,
        Idle,
        StartSquash,
        Squashing,
        Unblocking
    };
 
  private:
    Status _status;
    StageStatus dispatchStatus[Impl::MaxThreads];
    StageStatus exeStatus;
    StageStatus wbStatus;
 
    ProbePointArg<DynInstPtr> *ppMispredict;
    ProbePointArg<DynInstPtr> *ppDispatch;
    ProbePointArg<DynInstPtr> *ppExecute;
    ProbePointArg<DynInstPtr> *ppToCommit;
 
  public:
    DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
 
    std::string name() const;
 
    void regStats();
 
    void regProbePoints();
 
    void startupStage();
 
    void clearStates(ThreadID tid);
 
    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 
    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
 
    void setActiveThreads(std::list<ThreadID> *at_ptr);
 
    void setScoreboard(Scoreboard *sb_ptr);
 
    void drainSanityCheck() const;
 
    bool isDrained() const;
 
    void takeOverFrom();
 
    void squash(ThreadID tid);
 
    void wakeDependents(const DynInstPtr &inst);
 
    void rescheduleMemInst(const DynInstPtr &inst);
 
    void replayMemInst(const DynInstPtr &inst);
 
    void blockMemInst(const DynInstPtr &inst);
 
    void cacheUnblocked();
 
    void instToCommit(const DynInstPtr &inst);
 
    void skidInsert(ThreadID tid);
 
    int skidCount();
 
    bool skidsEmpty();
 
    void updateStatus();
 
    void resetEntries();
 
    void wakeCPU();
 
    void activityThisCycle();
 
    inline void activateStage();
 
    inline void deactivateStage();
 
    bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
 
    bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
 
    void checkMisprediction(const DynInstPtr &inst);
 
    // hardware transactional memory
    // For debugging purposes, it is useful to keep track of the most recent
    // htmUid that has been committed (architecturally, not transactionally)
    // to ensure that the core and the memory subsystem are observing
    // correct ordering constraints.
    void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
    {
        ldstQueue.setLastRetiredHtmUid(tid, htmUid);
    }
 
  private:
    void squashDueToBranch(const DynInstPtr &inst, ThreadID tid);
 
    void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid);
 
    void block(ThreadID tid);
 
    void unblock(ThreadID tid);
 
    void dispatch(ThreadID tid);
 
    void dispatchInsts(ThreadID tid);
 
    void executeInsts();
 
    void writebackInsts();
 
    unsigned validInstsFromRename();
 
    bool checkStall(ThreadID tid);
 
    void checkSignalsAndUpdate(ThreadID tid);
 
    void emptyRenameInsts(ThreadID tid);
 
    void sortInsts();
 
  public:
    void tick();
 
  private:
    void updateExeInstStats(const DynInstPtr &inst);
 
    TimeBuffer<TimeStruct> *timeBuffer;
 
    typename TimeBuffer<TimeStruct>::wire toFetch;
 
    typename TimeBuffer<TimeStruct>::wire fromCommit;
 
    typename TimeBuffer<TimeStruct>::wire toRename;
 
    TimeBuffer<RenameStruct> *renameQueue;
 
    typename TimeBuffer<RenameStruct>::wire fromRename;
 
    TimeBuffer<IssueStruct> issueToExecQueue;
 
    typename TimeBuffer<IssueStruct>::wire fromIssue;
 
    TimeBuffer<IEWStruct> *iewQueue;
 
    typename TimeBuffer<IEWStruct>::wire toCommit;
 
    std::queue<DynInstPtr> insts[Impl::MaxThreads];
 
    std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
 
    Scoreboard* scoreboard;
 
  private:
    O3CPU *cpu;
 
    bool wroteToTimeBuffer;
 
    void printAvailableInsts();
 
  public:
    IQ instQueue;
 
    LSQ ldstQueue;
 
    FUPool *fuPool;
    bool updateLSQNextCycle;
 
  private:
    bool fetchRedirect[Impl::MaxThreads];
 
    bool updatedQueues;
 
    Cycles commitToIEWDelay;
 
    Cycles renameToIEWDelay;
 
    Cycles issueToExecuteDelay;
 
    unsigned dispatchWidth;
 
    unsigned issueWidth;
 
    unsigned wbNumInst;
 
    unsigned wbCycle;
 
    unsigned wbWidth;
 
    ThreadID numThreads;
 
    std::list<ThreadID> *activeThreads;
 
    unsigned skidBufferMax;
 
    Stats::Scalar iewIdleCycles;
    Stats::Scalar iewSquashCycles;
    Stats::Scalar iewBlockCycles;
    Stats::Scalar iewUnblockCycles;
    Stats::Scalar iewDispatchedInsts;
    Stats::Scalar iewDispSquashedInsts;
    Stats::Scalar iewDispLoadInsts;
    Stats::Scalar iewDispStoreInsts;
    Stats::Scalar iewDispNonSpecInsts;
    Stats::Scalar iewIQFullEvents;
    Stats::Scalar iewLSQFullEvents;
    Stats::Scalar memOrderViolationEvents;
    Stats::Scalar predictedTakenIncorrect;
    Stats::Scalar predictedNotTakenIncorrect;
    Stats::Formula branchMispredicts;
 
    Stats::Scalar iewExecutedInsts;
    Stats::Vector iewExecLoadInsts;
//    Stats::Scalar iewExecStoreInsts;
    Stats::Scalar iewExecSquashedInsts;
    Stats::Vector iewExecutedSwp;
    Stats::Vector iewExecutedNop;
    Stats::Vector iewExecutedRefs;
    Stats::Vector iewExecutedBranches;
    Stats::Formula iewExecStoreInsts;
    Stats::Formula iewExecRate;
 
    Stats::Vector iewInstsToCommit;
    Stats::Vector writebackCount;
    Stats::Vector producerInst;
    Stats::Vector consumerInst;
    Stats::Formula wbRate;
    Stats::Formula wbFanout;
};
 
#endif // __CPU_O3_IEW_HH__