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42 #ifndef __CPU_O3_LSQ_HH__
43 #define __CPU_O3_LSQ_HH__
52 #include "enums/SMTQueuePolicy.hh"
56 struct DerivO3CPUParams;
66 typedef typename Impl::O3CPU
O3CPU;
68 typedef typename Impl::CPUPol::IEW
IEW;
69 typedef typename Impl::CPUPol::LSQUnit
LSQUnit;
311 _inst->isStoreConditional() ||
_inst->isAtomic());
316 const Addr&
addr,
const uint32_t& size,
331 _inst->isStoreConditional() ||
_inst->isAtomic());
362 return _inst->isSquashed();
388 assert(reason == Flag::LSQEntryFreed || reason == Flag::Discarded);
409 if (byte_enable.empty() ||
411 auto request = std::make_shared<Request>(
415 if (!byte_enable.empty()) {
416 request->setByteEnable(byte_enable);
429 _inst->savedReq =
nullptr;
445 request()->setContext(context_id);
506 pkt->senderState =
st;
593 return flags.
isSet(Flag::TranslationStarted) &&
660 assert(!
flags.
isSet(Flag::WritebackScheduled));
661 flags.
set(Flag::WritebackScheduled);
678 flags.
set(Flag::TranslationSquashed);
691 virtual std::string
name()
const {
return "LSQRequest"; }
727 const Addr&
addr,
const uint32_t& size,
730 uint64_t* res =
nullptr,
733 std::move(amo_op)) {}
744 virtual std::string
name()
const {
return "SingleDataRequest"; }
772 virtual std::string
name()
const {
return "HtmCmdRequest"; }
814 const Addr&
addr,
const uint32_t& size,
817 uint64_t* res =
nullptr) :
849 virtual std::string
name()
const {
return "SplitDataRequest"; }
853 LSQ(
O3CPU *cpu_ptr,
IEW *iew_ptr, DerivO3CPUParams *params);
857 std::string
name()
const;
890 {
thread.at(tid).commitLoads(youngest_inst); }
896 {
thread.at(tid).commitStores(youngest_inst); }
912 thread.at(tid).squash(squashed_num);
927 return thread.at(tid).getMemDepViolator();
937 return thread.at(tid).getLoadHeadSeqNum();
947 return thread.at(tid).getStoreHeadSeqNum();
973 return thread[tid].numHtmStarts();
980 return thread[tid].numHtmStops();
986 thread[tid].resetHtmStartsStops();
994 return thread[tid].getLatestHtmUid();
1000 thread[tid].setLastRetiredHtmUid(htmUid);
1080 Fault read(LSQRequest* req,
int load_idx);
1150 if (pol == SMTQueuePolicy::Dynamic) {
1152 }
else if (pol == SMTQueuePolicy::Partitioned) {
1155 }
else if (pol == SMTQueuePolicy::Threshold) {
1159 return SMTThreshold;
1188 template <
class Impl>
1194 return thread.at(tid).read(req, load_idx);
1197 template <
class Impl>
1203 return thread.at(tid).write(req,
data, store_idx);
1206 #endif // __CPU_O3_LSQ_HH__
void insertStore(const DynInstPtr &store_inst)
Inserts a store into the LSQ.
const ThreadID InvalidThreadID
std::vector< LSQUnit > thread
The LSQ units for individual threads.
uint32_t numReceivedPackets
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
virtual ~SplitDataRequest()
virtual Cycles handleLocalAccess(ThreadContext *thread, PacketPtr pkt)
Memory mapped IPR accesses.
bool willWB()
Returns if the LSQ will write back to memory this cycle.
virtual void buildPackets()=0
FullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time ...
Fault executeStore(const DynInstPtr &inst)
Executes a store.
LSQ< Impl > * lsq
Pointer to LSQ.
unsigned maxSQEntries
Max SQ Size - Used to Enforce Sharing Policies.
@ IsAtomic
True if this is an atomic request.
void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
Commits stores up until the given sequence number for a specific thread.
virtual ~SingleDataRequest()
bool violation(ThreadID tid)
Returns whether or not there was a memory ordering violation for a specific thread.
bool deleted
Has the request been deleted? LSQ entries can be squashed before the response comes back.
int numHtmStops(ThreadID tid) const
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Impl::CPUPol::LSQUnit LSQUnit
void discard()
The request is discarded (e.g.
virtual PacketPtr mainPacket()
bool willWB(ThreadID tid)
Returns if the LSQ of a specific thread will write back to memory this cycle.
virtual RequestPtr mainRequest()
void insertLoad(const DynInstPtr &load_inst)
Inserts a load into the LSQ.
bool sqEmpty() const
Returns if all of the SQs are empty.
virtual bool squashed() const override
This function is used by the page table walker to determine if it should translate the a pending requ...
LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
Constructs an LSQ with the given parameters.
int16_t ThreadID
Thread index/ID type.
uint32_t numInTranslationFragments
bool isMemAccessRequired()
@ TranslationStarted
True if any translation has been sent to TLB.
void resetHtmStartsStops(ThreadID tid)
LSQSenderState(LSQRequest *request, bool isLoad_)
Default constructor.
PacketPtr pendingPacket
A second packet from a split store that needs sending.
uint8_t outstanding
Number of outstanding packets to complete.
int ContextID
Globally unique thread context ID.
virtual void initiateTranslation()
DynInstPtr inst
Instruction which initiated the access to memory.
AtomicOpFunctorPtr _amo_op
@ Discarded
Request discarded.
const RequestPtr request(int idx=0) const
virtual bool recvTimingResp(PacketPtr pkt)
Timing version of receive.
int numLoads(ThreadID tid)
Returns the total number of loads for a single thread.
::Flags< FlagsStorage > FlagsType
bool recvTimingResp(PacketPtr pkt)
Handles writing back and completing the load or store that has returned from memory.
LSQSenderState * _senderState
std::shared_ptr< Request > RequestPtr
virtual void buildPackets()
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
void recvReqRetry()
Retry the previous send that failed.
DcachePort(LSQ< Impl > *_lsq, FullO3CPU< Impl > *_cpu)
Default constructor.
bool isComplete()
Completes a packet and returns whether the access is finished.
virtual bool recvTimingResp(PacketPtr pkt)
SingleDataRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr, AtomicOpFunctorPtr amo_op=nullptr)
void sendFragmentToTranslation(int i)
int numStores()
Returns the total number of stores in the store queue.
std::list< ThreadID > * activeThreads
List of Active Threads in System.
bool violation()
Returns whether or not there was a memory ordering violation.
@ TranslationFinished
True if there are un-replied outbound translations.
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)=0
Test if the request accesses a particular cache line.
bool isEmpty() const
Returns if the LSQ is empty (both LQ and SQ are empty).
uint32_t _numOutstandingPackets
int numLoads()
Returns the total number of loads in the load queue.
bool isSplit
Whether or not this access is split in two.
void tick()
Ticks the LSQ.
void packetNotSent()
Update the status to reflect that a packet was not sent.
virtual Cycles handleLocalAccess(ThreadContext *thread, PacketPtr pkt)=0
Memory mapped IPR accesses.
int getCount(ThreadID tid)
Returns the number of instructions in the queues of one thread.
void packetSent()
Update the status to reflect that a packet was sent.
bool lqFull()
Returns if any of the LQs are full.
bool isFull()
Returns if the LSQ is full (either LQ or SQ is full).
bool isAnyActiveElement(const std::vector< bool >::const_iterator &it_start, const std::vector< bool >::const_iterator &it_end)
Test if there is any active element in an enablement range.
void completeDataAccess(PacketPtr pkt)
bool isDrained() const
Has the LSQ drained?
IEW * iewStage
The IEW stage pointer.
std::vector< RequestPtr > _requests
virtual void sendPacketToCache()
void markDelayed() override
Signal that the translation has been delayed due to a hw page table walk.
void takeOverFrom()
Takes over execution from another CPU's thread.
DcachePort dcachePort
Data port.
Class that implements the actual LQ and SQ for each specific thread.
std::vector< bool > _byteEnable
bool isReleased()
Test if the LSQRequest has been released, i.e.
int numStores(ThreadID tid)
Returns the total number of stores for a single thread.
int usedLoadPorts
The number of used cache ports in this cycle by loads.
void drainSanityCheck() const
Perform sanity checks after a drain.
virtual std::string name() const
void addRequest(Addr addr, unsigned size, const std::vector< bool > &byte_enable)
Helper function used to add a (sub)request, given its address addr, size size and byte-enable mask by...
virtual ~LSQRequest()
Destructor.
LoadQueue loadQueue
The load queue.
bool isStalled()
Returns if the LSQ is stalled due to a memory operation that must be replayed.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
A virtual base opaque structure used to hold state associated with the packet (e.g....
@ WbStore
True if this is a store/atomic that writes registers (SC).
Fault read(LSQRequest *req, int load_idx)
Executes a read operation, using the load specified at the load index.
bool cachePortAvailable(bool is_load) const
Is any store port available to use?
InstSeqNum getStoreHeadSeqNum(ThreadID tid)
Returns the sequence number of the head of the store queue.
const Request::Flags _flags
LSQRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr, AtomicOpFunctorPtr amo_op=nullptr)
virtual void sendPacketToCache()
std::shared_ptr< FaultBase > Fault
void dumpInsts(ThreadID tid) const
Debugging function to print out instructions from a specific thread.
Derived class to hold any sender state the LSQ needs.
uint32_t _entryIdx
LQ/SQ entry idx.
void cachePortBusy(bool is_load)
Another store port is in use.
unsigned numFreeStoreEntries()
Returns the number of free store entries.
virtual void buildPackets()
InstSeqNum getLoadHeadSeqNum(ThreadID tid)
Returns the sequence number of the head of the load queue.
Fault executeLoad(const DynInstPtr &inst)
Executes a load.
static uint32_t maxLSQAllocation(SMTQueuePolicy pol, uint32_t entries, uint32_t numThreads, uint32_t SMTThreshold)
Auxiliary function to calculate per-thread max LSQ allocation limit.
bool isTranslationComplete()
void install()
Install the request in the LQ/SQ.
RequestPort & getDataPort()
bool lqEmpty() const
Returns if all of the LQs are empty.
Impl::DynInstPtr DynInstPtr
void senderState(LSQSenderState *st)
std::vector< PacketPtr > _packets
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable)
SplitDataRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr)
virtual std::string name() const
int usedStorePorts
The number of used cache ports in this cycle by stores.
uint64_t getLatestHtmUid(ThreadID tid) const
unsigned LQEntries
Total Size of LQ Entries.
@ WritebackScheduled
Store written back.
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
const DynInstPtr & instruction()
int getCount()
Returns the number of instructions in all of the queues.
virtual void initiateTranslation()=0
void writebackStores()
Attempts to write back stores until all cache ports are used or the interface becomes blocked.
bool needWB
Whether or not the instruction will need to writeback.
void setContext(const ContextID &context_id)
Convenience getters/setters.
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
bool isAnyOutstandingRequest()
Test if there is any in-flight translation or mem access request.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
LSQRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad)
const std::string name() const
Return port name (for DPRINTF).
int getStoreHead(ThreadID tid)
Returns the head index of the store queue.
void writebackScheduled()
int getLoadHead(ThreadID tid)
Returns the head index of the load queue for a specific thread.
unsigned numFreeLoadEntries()
Returns the number of free load entries.
void release(Flag reason)
Release the LSQRequest.
Fault write(LSQRequest *req, uint8_t *data, int store_idx)
Executes a store operation, using the store specified at the store index.
void freeLSQEntry()
The LSQ entry is cleared.
unsigned maxLQEntries
Max LQ Size - Used to Enforce Sharing Policies.
Addr getVaddr(int idx=0) const
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets the pointer to the list of active threads.
void setState(const State &newState)
virtual void recvTimingSnoopReq(PacketPtr pkt)
Receive a timing snoop request from the peer.
std::vector< Fault > _fault
unsigned SQEntries
Total Size of SQ Entries.
bool hasStoresToWB()
Returns whether or not there are any stores to write back to memory.
@ TranslationSquashed
Ownership tracking flags.
Memory operation metadata.
PacketPtr packet(int idx=0)
virtual Cycles handleLocalAccess(ThreadContext *thread, PacketPtr pkt)
Memory mapped IPR accesses.
virtual void initiateTranslation()
Overload hash function for BasicBlockRange type.
PacketPtr mainPkt
The main packet from a split load, used during writeback.
bool isLoad
Whether or not it is a load.
unsigned numFreeEntries(ThreadID tid)
Returns the number of free entries for a specific thread.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
int cacheLoadPorts
The number of cache ports available each cycle (loads only).
CircularQueue< SQEntry > storeQueue
The store queue.
uint32_t numTranslatedFragments
bool hasStoresToWB(ThreadID tid)
Returns whether or not a specific thread has any stores to write back to memory.
virtual void sendPacketToCache()=0
void recvTimingSnoopReq(PacketPtr pkt)
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squash instructions from a thread until the specified sequence number.
Cycles is a wrapper class for representing cycle counts, i.e.
bool sqFull()
Returns if any of the SQs are full.
virtual bool isSnooping() const
As this CPU requires snooping to maintain the load store queue change the behaviour from the base CPU...
void taskId(const uint32_t &v)
bool cacheBlocked() const
Is D-cache blocked?
bool isTranslationBlocked()
virtual bool recvTimingResp(PacketPtr pkt)
DcachePort class for the load/store queue.
int numStoresToWB(ThreadID tid)
Returns the number of stores a specific thread has to write back.
int entryAmount(ThreadID num_threads)
Number of entries needed for the given amount of threads.
DynInstPtr getMemDepViolator(ThreadID tid)
Gets the instruction that caused the memory ordering violation.
SMTQueuePolicy lsqPolicy
The LSQ policy for SMT mode.
const LSQSenderState * senderState() const
std::string name() const
Returns the name of the LSQ.
void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
Commits loads up until the given sequence number for a specific thread.
int cacheStorePorts
The number of cache ports available each cycle (stores only).
bool _cacheBlocked
D-cache is blocked.
virtual void initiateTranslation()
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)
Caches may probe into the load-store queue to enforce memory ordering guarantees.
virtual RequestPtr mainRequest()
void discardSenderState()
Mark senderState as discarded.
LSQRequest * _request
The senderState needs to know the LSQRequest who owns it.
virtual std::string name() const
int numHtmStarts(ThreadID tid) const
HtmCmdRequest(LSQUnit *port, const DynInstPtr &inst, const Request::Flags &flags_)
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)
Test if the request accesses a particular cache line.
virtual void recvReqRetry()
Handles doing a retry of the previous send.
virtual std::string name() const
void dumpInsts() const
Debugging function to print out all instructions.
virtual bool recvTimingResp(PacketPtr pkt)=0
virtual void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the peer.
@ LSQEntryFreed
LSQ resources freed.
virtual void complete()=0
O3CPU * cpu
The CPU pointer.
void setVirt(Addr vaddr, unsigned size, Request::Flags flags_, RequestorID requestor_id, Addr pc)
Set up virtual request.
bool pktToSend
Whether or not there is a packet that needs sending.
ThreadID numThreads
Number of Threads.
virtual PacketPtr mainPacket()
RequestPtr request(int idx=0)
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