gem5  v20.1.0.0
lsq.hh
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41 
42 #ifndef __CPU_O3_LSQ_HH__
43 #define __CPU_O3_LSQ_HH__
44 
45 #include <map>
46 #include <queue>
47 
48 #include "arch/generic/tlb.hh"
49 #include "cpu/inst_seq.hh"
50 #include "cpu/o3/lsq_unit.hh"
51 #include "cpu/utils.hh"
52 #include "enums/SMTQueuePolicy.hh"
53 #include "mem/port.hh"
54 #include "sim/sim_object.hh"
55 
56 struct DerivO3CPUParams;
57 
58 template <class Impl>
59 class FullO3CPU;
60 
61 template <class Impl>
62 class LSQ
63 
64 {
65  public:
66  typedef typename Impl::O3CPU O3CPU;
67  typedef typename Impl::DynInstPtr DynInstPtr;
68  typedef typename Impl::CPUPol::IEW IEW;
69  typedef typename Impl::CPUPol::LSQUnit LSQUnit;
70 
71  class LSQRequest;
74  {
75  protected:
78 
81  : _request(request), mainPkt(nullptr), pendingPacket(nullptr),
82  outstanding(0), isLoad(isLoad_), needWB(isLoad_), isSplit(false),
83  pktToSend(false), deleted(false)
84  { }
85  public:
86 
94  uint8_t outstanding;
96  bool isLoad;
98  bool needWB;
100  bool isSplit;
102  bool pktToSend;
107  bool deleted;
108  ContextID contextId() { return inst->contextId(); }
109 
111  inline bool isComplete() { return outstanding == 0; }
112  inline void deleteRequest() { deleted = true; }
113  inline bool alive() { return !deleted; }
114  LSQRequest* request() { return _request; }
115  virtual void complete() = 0;
117  };
118 
122  class DcachePort : public RequestPort
123  {
124  protected:
125 
129 
130  public:
133  : RequestPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
134  cpu(_cpu)
135  { }
136 
137  protected:
138 
142  virtual bool recvTimingResp(PacketPtr pkt);
143  virtual void recvTimingSnoopReq(PacketPtr pkt);
144 
145  virtual void recvFunctionalSnoop(PacketPtr pkt)
146  {
147  // @todo: Is there a need for potential invalidation here?
148  }
149 
151  virtual void recvReqRetry();
152 
159  virtual bool isSnooping() const { return true; }
160  };
161 
231  {
232  protected:
233  typedef uint32_t FlagsStorage;
234  typedef ::Flags<FlagsStorage> FlagsType;
235 
237  {
238  IsLoad = 0x00000001,
240  WbStore = 0x00000002,
241  Delayed = 0x00000004,
242  IsSplit = 0x00000008,
244  TranslationStarted = 0x00000010,
246  TranslationFinished = 0x00000020,
247  Sent = 0x00000040,
248  Retry = 0x00000080,
249  Complete = 0x00000100,
252  TranslationSquashed = 0x00000200,
254  Discarded = 0x00000400,
256  LSQEntryFreed = 0x00000800,
258  WritebackScheduled = 0x00001000,
259  WritebackDone = 0x00002000,
261  IsAtomic = 0x00004000
262  };
264 
265  enum class State
266  {
267  NotIssued,
268  Translation,
269  Request,
270  Fault,
271  PartialFault,
272  };
275  void setState(const State& newState) { _state = newState; }
276 
279 
281  uint32_t _entryIdx;
282 
283  void markDelayed() override { flags.set(Flag::Delayed); }
284  bool isDelayed() { return flags.isSet(Flag::Delayed); }
285 
286  public:
289  uint32_t _taskId;
294  uint64_t* _res;
295  const Addr _addr;
296  const uint32_t _size;
301  protected:
302  LSQUnit* lsqUnit() { return &_port; }
303  LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad) :
304  _state(State::NotIssued), _senderState(nullptr),
305  _port(*port), _inst(inst), _data(nullptr),
306  _res(nullptr), _addr(0), _size(0), _flags(0),
307  _numOutstandingPackets(0), _amo_op(nullptr)
308  {
309  flags.set(Flag::IsLoad, isLoad);
310  flags.set(Flag::WbStore,
311  _inst->isStoreConditional() || _inst->isAtomic());
312  flags.set(Flag::IsAtomic, _inst->isAtomic());
313  install();
314  }
315  LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
316  const Addr& addr, const uint32_t& size,
317  const Request::Flags& flags_,
318  PacketDataPtr data = nullptr, uint64_t* res = nullptr,
319  AtomicOpFunctorPtr amo_op = nullptr)
320  : _state(State::NotIssued), _senderState(nullptr),
323  _port(*port), _inst(inst), _data(data),
324  _res(res), _addr(addr), _size(size),
325  _flags(flags_),
327  _amo_op(std::move(amo_op))
328  {
329  flags.set(Flag::IsLoad, isLoad);
330  flags.set(Flag::WbStore,
331  _inst->isStoreConditional() || _inst->isAtomic());
332  flags.set(Flag::IsAtomic, _inst->isAtomic());
333  install();
334  }
335 
336  bool
337  isLoad() const
338  {
339  return flags.isSet(Flag::IsLoad);
340  }
341 
342  bool
343  isAtomic() const
344  {
345  return flags.isSet(Flag::IsAtomic);
346  }
347 
349  void install()
350  {
351  if (isLoad()) {
352  _port.loadQueue[_inst->lqIdx].setRequest(this);
353  } else {
354  // Store, StoreConditional, and Atomic requests are pushed
355  // to this storeQueue
356  _port.storeQueue[_inst->sqIdx].setRequest(this);
357  }
358  }
359  virtual bool
360  squashed() const override
361  {
362  return _inst->isSquashed();
363  }
364 
370  bool
372  {
373  return flags.isSet(Flag::LSQEntryFreed) ||
374  flags.isSet(Flag::Discarded);
375  }
376 
386  void release(Flag reason)
387  {
388  assert(reason == Flag::LSQEntryFreed || reason == Flag::Discarded);
389  if (!isAnyOutstandingRequest()) {
390  delete this;
391  } else {
392  if (_senderState) {
394  }
395  flags.set(reason);
396  }
397  }
398 
405  void
406  addRequest(Addr addr, unsigned size,
407  const std::vector<bool>& byte_enable)
408  {
409  if (byte_enable.empty() ||
410  isAnyActiveElement(byte_enable.begin(), byte_enable.end())) {
411  auto request = std::make_shared<Request>(
412  addr, size, _flags, _inst->requestorId(),
413  _inst->instAddr(), _inst->contextId(),
414  std::move(_amo_op));
415  if (!byte_enable.empty()) {
416  request->setByteEnable(byte_enable);
417  }
418  _requests.push_back(request);
419  }
420  }
421 
426  virtual ~LSQRequest()
427  {
428  assert(!isAnyOutstandingRequest());
429  _inst->savedReq = nullptr;
430  if (_senderState)
431  delete _senderState;
432 
433  for (auto r: _packets)
434  delete r;
435  };
436 
437 
438  public:
442  void
443  setContext(const ContextID& context_id)
444  {
445  request()->setContext(context_id);
446  }
447 
448  const DynInstPtr&
450  {
451  return _inst;
452  }
453 
457  void
458  setVirt(Addr vaddr, unsigned size, Request::Flags flags_,
459  RequestorID requestor_id, Addr pc)
460  {
461  request()->setVirt(vaddr, size, flags_, requestor_id, pc);
462  }
463 
464  void
465  taskId(const uint32_t& v)
466  {
467  _taskId = v;
468  for (auto& r: _requests)
469  r->taskId(v);
470  }
471 
472  uint32_t taskId() const { return _taskId; }
473  RequestPtr request(int idx = 0) { return _requests.at(idx); }
474 
475  const RequestPtr
476  request(int idx = 0) const
477  {
478  return _requests.at(idx);
479  }
480 
481  Addr getVaddr(int idx = 0) const { return request(idx)->getVaddr(); }
482  virtual void initiateTranslation() = 0;
483 
484  PacketPtr packet(int idx = 0) { return _packets.at(idx); }
485 
486  virtual PacketPtr
488  {
489  assert (_packets.size() == 1);
490  return packet();
491  }
492 
493  virtual RequestPtr
495  {
496  assert (_requests.size() == 1);
497  return request();
498  }
499 
500  void
502  {
503  _senderState = st;
504  for (auto& pkt: _packets) {
505  if (pkt)
506  pkt->senderState = st;
507  }
508  }
509 
510  const LSQSenderState*
511  senderState() const
512  {
513  return _senderState;
514  }
515 
520  void
522  {
523  assert(_senderState);
525  }
526 
530  bool
532  {
533  return numInTranslationFragments > 0 ||
535  (flags.isSet(Flag::WritebackScheduled) &&
536  !flags.isSet(Flag::WritebackDone));
537  }
538 
539  bool
540  isSplit() const
541  {
542  return flags.isSet(Flag::IsSplit);
543  }
545  virtual bool recvTimingResp(PacketPtr pkt) = 0;
546  virtual void sendPacketToCache() = 0;
547  virtual void buildPackets() = 0;
548 
552  virtual Cycles handleLocalAccess(
553  ThreadContext *thread, PacketPtr pkt) = 0;
554 
558  virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask) = 0;
559 
561  void
563  {
564  flags.set(Flag::Sent);
565  }
570  void
572  {
573  flags.set(Flag::Retry);
574  flags.clear(Flag::Sent);
575  }
576 
577  void sendFragmentToTranslation(int i);
578  bool
580  {
581  return flags.isSet(Flag::Complete);
582  }
583 
584  bool
586  {
587  return _state == State::Translation;
588  }
589 
590  bool
592  {
593  return flags.isSet(Flag::TranslationStarted) &&
594  !isInTranslation();
595  }
596 
597  bool
599  {
600  return _state == State::Translation &&
601  flags.isSet(Flag::TranslationStarted) &&
602  !flags.isSet(Flag::TranslationFinished);
603  }
604 
605  bool
607  {
608  return flags.isSet(Flag::Sent);
609  }
610 
611  bool
613  {
614  return _state == State::PartialFault;
615  }
616 
617  bool
619  {
620  return (_state == State::Request ||
621  (isPartialFault() && isLoad()));
622  }
623 
624  void
626  {
628  }
629 
633  void
635  {
636  release(Flag::LSQEntryFreed);
637  }
638 
642  void
644  {
645  release(Flag::Discarded);
646  }
647 
648  void
650  {
651  assert(_numOutstandingPackets > 0);
653  if (_numOutstandingPackets == 0 && isReleased())
654  delete this;
655  }
656 
657  void
659  {
660  assert(!flags.isSet(Flag::WritebackScheduled));
661  flags.set(Flag::WritebackScheduled);
662  }
663 
664  void
666  {
667  flags.set(Flag::WritebackDone);
668  /* If the lsq resources are already free */
669  if (isReleased()) {
670  delete this;
671  }
672  }
673 
674  void
676  {
677  assert(numInTranslationFragments == 0);
678  flags.set(Flag::TranslationSquashed);
679  /* If we are on our own, self-destruct. */
680  if (isReleased()) {
681  delete this;
682  }
683  }
684 
685  void
687  {
689  }
690 
691  virtual std::string name() const { return "LSQRequest"; }
692  };
693 
695  {
696  protected:
697  /* Given that we are inside templates, children need explicit
698  * declaration of the names in the parent class. */
699  using Flag = typename LSQRequest::Flag;
700  using State = typename LSQRequest::State;
701  using LSQRequest::_addr;
702  using LSQRequest::_fault;
703  using LSQRequest::_flags;
704  using LSQRequest::_size;
706  using LSQRequest::_requests;
707  using LSQRequest::_inst;
708  using LSQRequest::_packets;
709  using LSQRequest::_port;
710  using LSQRequest::_res;
711  using LSQRequest::_taskId;
713  using LSQRequest::_state;
714  using LSQRequest::flags;
715  using LSQRequest::isLoad;
717  using LSQRequest::lsqUnit;
718  using LSQRequest::request;
720  using LSQRequest::setState;
724  using LSQRequest::_amo_op;
725  public:
726  SingleDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
727  const Addr& addr, const uint32_t& size,
728  const Request::Flags& flags_,
729  PacketDataPtr data = nullptr,
730  uint64_t* res = nullptr,
731  AtomicOpFunctorPtr amo_op = nullptr) :
732  LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
733  std::move(amo_op)) {}
734 
735  inline virtual ~SingleDataRequest() {}
736  virtual void initiateTranslation();
737  virtual void finish(const Fault &fault, const RequestPtr &req,
739  virtual bool recvTimingResp(PacketPtr pkt);
740  virtual void sendPacketToCache();
741  virtual void buildPackets();
743  virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
744  virtual std::string name() const { return "SingleDataRequest"; }
745  };
746 
747  // hardware transactional memory
748  // This class extends SingleDataRequest for the sole purpose
749  // of encapsulating hardware transactional memory command requests
751  {
752  protected:
753  /* Given that we are inside templates, children need explicit
754  * declaration of the names in the parent class. */
755  using Flag = typename LSQRequest::Flag;
756  using State = typename LSQRequest::State;
757  using LSQRequest::_addr;
758  using LSQRequest::_size;
760  using LSQRequest::_requests;
761  using LSQRequest::_inst;
762  using LSQRequest::_taskId;
763  using LSQRequest::flags;
764  using LSQRequest::setState;
765  public:
766  HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
767  const Request::Flags& flags_);
768  inline virtual ~HtmCmdRequest() {}
769  virtual void initiateTranslation();
770  virtual void finish(const Fault &fault, const RequestPtr &req,
772  virtual std::string name() const { return "HtmCmdRequest"; }
773  };
774 
776  {
777  protected:
778  /* Given that we are inside templates, children need explicit
779  * declaration of the names in the parent class. */
780  using Flag = typename LSQRequest::Flag;
781  using State = typename LSQRequest::State;
782  using LSQRequest::_addr;
783  using LSQRequest::_data;
784  using LSQRequest::_fault;
785  using LSQRequest::_flags;
786  using LSQRequest::_inst;
787  using LSQRequest::_packets;
788  using LSQRequest::_port;
789  using LSQRequest::_requests;
790  using LSQRequest::_res;
793  using LSQRequest::_size;
794  using LSQRequest::_state;
795  using LSQRequest::_taskId;
796  using LSQRequest::flags;
797  using LSQRequest::isLoad;
799  using LSQRequest::lsqUnit;
802  using LSQRequest::request;
804  using LSQRequest::setState;
806 
807  uint32_t numFragments;
811 
812  public:
813  SplitDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
814  const Addr& addr, const uint32_t& size,
815  const Request::Flags & flags_,
816  PacketDataPtr data = nullptr,
817  uint64_t* res = nullptr) :
818  LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
819  nullptr),
820  numFragments(0),
822  mainReq(nullptr),
823  _mainPacket(nullptr)
824  {
825  flags.set(Flag::IsSplit);
826  }
828  {
829  if (mainReq) {
830  mainReq = nullptr;
831  }
832  if (_mainPacket) {
833  delete _mainPacket;
834  _mainPacket = nullptr;
835  }
836  }
837  virtual void finish(const Fault &fault, const RequestPtr &req,
839  virtual bool recvTimingResp(PacketPtr pkt);
840  virtual void initiateTranslation();
841  virtual void sendPacketToCache();
842  virtual void buildPackets();
843 
845  virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
846 
847  virtual RequestPtr mainRequest();
848  virtual PacketPtr mainPacket();
849  virtual std::string name() const { return "SplitDataRequest"; }
850  };
851 
853  LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
854  ~LSQ() { }
855 
857  std::string name() const;
858 
861 
863  void drainSanityCheck() const;
865  bool isDrained() const;
867  void takeOverFrom();
868 
870  int entryAmount(ThreadID num_threads);
871 
873  void tick();
874 
876  void insertLoad(const DynInstPtr &load_inst);
878  void insertStore(const DynInstPtr &store_inst);
879 
881  Fault executeLoad(const DynInstPtr &inst);
882 
884  Fault executeStore(const DynInstPtr &inst);
885 
889  void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
890  { thread.at(tid).commitLoads(youngest_inst); }
891 
895  void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
896  { thread.at(tid).commitStores(youngest_inst); }
897 
902  void writebackStores();
904  void writebackStores(ThreadID tid);
905 
909  void
910  squash(const InstSeqNum &squashed_num, ThreadID tid)
911  {
912  thread.at(tid).squash(squashed_num);
913  }
914 
916  bool violation();
921  bool violation(ThreadID tid) { return thread.at(tid).violation(); }
922 
924  DynInstPtr
926  {
927  return thread.at(tid).getMemDepViolator();
928  }
929 
931  int getLoadHead(ThreadID tid) { return thread.at(tid).getLoadHead(); }
932 
934  InstSeqNum
936  {
937  return thread.at(tid).getLoadHeadSeqNum();
938  }
939 
941  int getStoreHead(ThreadID tid) { return thread.at(tid).getStoreHead(); }
942 
944  InstSeqNum
946  {
947  return thread.at(tid).getStoreHeadSeqNum();
948  }
949 
951  int getCount();
953  int getCount(ThreadID tid) { return thread.at(tid).getCount(); }
954 
956  int numLoads();
958  int numLoads(ThreadID tid) { return thread.at(tid).numLoads(); }
959 
961  int numStores();
963  int numStores(ThreadID tid) { return thread.at(tid).numStores(); }
964 
965 
966  // hardware transactional memory
967 
968  int numHtmStarts(ThreadID tid) const
969  {
970  if (tid == InvalidThreadID)
971  return 0;
972  else
973  return thread[tid].numHtmStarts();
974  }
975  int numHtmStops(ThreadID tid) const
976  {
977  if (tid == InvalidThreadID)
978  return 0;
979  else
980  return thread[tid].numHtmStops();
981  }
982 
984  {
985  if (tid != InvalidThreadID)
986  thread[tid].resetHtmStartsStops();
987  }
988 
989  uint64_t getLatestHtmUid(ThreadID tid) const
990  {
991  if (tid == InvalidThreadID)
992  return 0;
993  else
994  return thread[tid].getLatestHtmUid();
995  }
996 
997  void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
998  {
999  if (tid != InvalidThreadID)
1000  thread[tid].setLastRetiredHtmUid(htmUid);
1001  }
1002 
1004  unsigned numFreeLoadEntries();
1005 
1007  unsigned numFreeStoreEntries();
1008 
1010  unsigned numFreeEntries(ThreadID tid);
1011 
1013  unsigned numFreeLoadEntries(ThreadID tid);
1014 
1016  unsigned numFreeStoreEntries(ThreadID tid);
1017 
1019  bool isFull();
1024  bool isFull(ThreadID tid);
1025 
1027  bool isEmpty() const;
1029  bool lqEmpty() const;
1031  bool sqEmpty() const;
1032 
1034  bool lqFull();
1036  bool lqFull(ThreadID tid);
1037 
1039  bool sqFull();
1041  bool sqFull(ThreadID tid);
1042 
1047  bool isStalled();
1052  bool isStalled(ThreadID tid);
1053 
1055  bool hasStoresToWB();
1056 
1060  bool hasStoresToWB(ThreadID tid) { return thread.at(tid).hasStoresToWB(); }
1061 
1063  int numStoresToWB(ThreadID tid) { return thread.at(tid).numStoresToWB(); }
1064 
1066  bool willWB();
1070  bool willWB(ThreadID tid) { return thread.at(tid).willWB(); }
1071 
1073  void dumpInsts() const;
1075  void dumpInsts(ThreadID tid) const { thread.at(tid).dumpInsts(); }
1076 
1080  Fault read(LSQRequest* req, int load_idx);
1081 
1085  Fault write(LSQRequest* req, uint8_t *data, int store_idx);
1086 
1090  void recvReqRetry();
1091 
1092  void completeDataAccess(PacketPtr pkt);
1099  bool recvTimingResp(PacketPtr pkt);
1100 
1101  void recvTimingSnoopReq(PacketPtr pkt);
1102 
1103  Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
1104  unsigned int size, Addr addr, Request::Flags flags,
1105  uint64_t *res, AtomicOpFunctorPtr amo_op,
1106  const std::vector<bool>& byte_enable);
1107 
1110 
1113 
1115  bool cacheBlocked() const;
1117  void cacheBlocked(bool v);
1119  bool cachePortAvailable(bool is_load) const;
1121  void cachePortBusy(bool is_load);
1122 
1124 
1125  protected:
1136 
1137 
1139  SMTQueuePolicy lsqPolicy;
1140 
1146  static uint32_t
1147  maxLSQAllocation(SMTQueuePolicy pol, uint32_t entries,
1148  uint32_t numThreads, uint32_t SMTThreshold)
1149  {
1150  if (pol == SMTQueuePolicy::Dynamic) {
1151  return entries;
1152  } else if (pol == SMTQueuePolicy::Partitioned) {
1153  //@todo:make work if part_amt doesnt divide evenly.
1154  return entries / numThreads;
1155  } else if (pol == SMTQueuePolicy::Threshold) {
1156  //Divide up by threshold amount
1157  //@todo: Should threads check the max and the total
1158  //amount of the LSQ
1159  return SMTThreshold;
1160  }
1161  return 0;
1162  }
1163 
1166 
1168  unsigned LQEntries;
1170  unsigned SQEntries;
1171 
1173  unsigned maxLQEntries;
1174 
1176  unsigned maxSQEntries;
1177 
1180 
1183 
1186 };
1187 
1188 template <class Impl>
1189 Fault
1190 LSQ<Impl>::read(LSQRequest* req, int load_idx)
1191 {
1192  ThreadID tid = cpu->contextToThread(req->request()->contextId());
1193 
1194  return thread.at(tid).read(req, load_idx);
1195 }
1196 
1197 template <class Impl>
1198 Fault
1199 LSQ<Impl>::write(LSQRequest* req, uint8_t *data, int store_idx)
1200 {
1201  ThreadID tid = cpu->contextToThread(req->request()->contextId());
1202 
1203  return thread.at(tid).write(req, data, store_idx);
1204 }
1205 
1206 #endif // __CPU_O3_LSQ_HH__
LSQ::insertStore
void insertStore(const DynInstPtr &store_inst)
Inserts a store into the LSQ.
Definition: lsq_impl.hh:230
InvalidThreadID
const ThreadID InvalidThreadID
Definition: types.hh:228
LSQ::thread
std::vector< LSQUnit > thread
The LSQ units for individual threads.
Definition: lsq.hh:1182
LSQ::SplitDataRequest::numReceivedPackets
uint32_t numReceivedPackets
Definition: lsq.hh:808
AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:239
LSQ::SplitDataRequest::~SplitDataRequest
virtual ~SplitDataRequest()
Definition: lsq.hh:827
LSQ::SingleDataRequest::handleLocalAccess
virtual Cycles handleLocalAccess(ThreadContext *thread, PacketPtr pkt)
Memory mapped IPR accesses.
Definition: lsq_impl.hh:1143
LSQ::willWB
bool willWB()
Returns if the LSQ will write back to memory this cycle.
Definition: lsq_impl.hh:646
LSQ::LSQRequest::buildPackets
virtual void buildPackets()=0
FullO3CPU
FullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time ...
Definition: cpu.hh:93
LSQ::executeStore
Fault executeStore(const DynInstPtr &inst)
Executes a store.
Definition: lsq_impl.hh:248
utils.hh
LSQ::LSQRequest::packetReplied
void packetReplied()
Definition: lsq.hh:649
LSQ::DcachePort::lsq
LSQ< Impl > * lsq
Pointer to LSQ.
Definition: lsq.hh:127
LSQ::maxSQEntries
unsigned maxSQEntries
Max SQ Size - Used to Enforce Sharing Policies.
Definition: lsq.hh:1176
LSQ::LSQRequest::IsAtomic
@ IsAtomic
True if this is an atomic request.
Definition: lsq.hh:261
LSQ::commitStores
void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
Commits stores up until the given sequence number for a specific thread.
Definition: lsq.hh:895
LSQ::SingleDataRequest::~SingleDataRequest
virtual ~SingleDataRequest()
Definition: lsq.hh:735
LSQ::violation
bool violation(ThreadID tid)
Returns whether or not there was a memory ordering violation for a specific thread.
Definition: lsq.hh:921
data
const char data[]
Definition: circlebuf.test.cc:42
LSQ::LSQSenderState::deleted
bool deleted
Has the request been deleted? LSQ entries can be squashed before the response comes back.
Definition: lsq.hh:107
LSQ::numHtmStops
int numHtmStops(ThreadID tid) const
Definition: lsq.hh:975
LSQ::HtmCmdRequest::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Definition: lsq_impl.hh:1290
LSQ::LSQUnit
Impl::CPUPol::LSQUnit LSQUnit
Definition: lsq.hh:69
LSQ::LSQRequest::discard
void discard()
The request is discarded (e.g.
Definition: lsq.hh:643
LSQ::SplitDataRequest::mainPacket
virtual PacketPtr mainPacket()
Definition: lsq_impl.hh:872
LSQ::willWB
bool willWB(ThreadID tid)
Returns if the LSQ of a specific thread will write back to memory this cycle.
Definition: lsq.hh:1070
LSQ::SplitDataRequest::mainRequest
virtual RequestPtr mainRequest()
Definition: lsq_impl.hh:879
LSQ::LSQRequest::Complete
@ Complete
Definition: lsq.hh:249
LSQ::insertLoad
void insertLoad(const DynInstPtr &load_inst)
Inserts a load into the LSQ.
Definition: lsq_impl.hh:221
LSQ::sqEmpty
bool sqEmpty() const
Returns if all of the SQs are empty.
Definition: lsq_impl.hh:527
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
LSQ::LSQRequest::squashed
virtual bool squashed() const override
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition: lsq.hh:360
LSQ::LSQ
LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
Constructs an LSQ with the given parameters.
Definition: lsq_impl.hh:62
ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
LSQ::LSQRequest::numInTranslationFragments
uint32_t numInTranslationFragments
Definition: lsq.hh:278
LSQ::LSQRequest::isAtomic
bool isAtomic() const
Definition: lsq.hh:343
LSQ::LSQRequest::isMemAccessRequired
bool isMemAccessRequired()
Definition: lsq.hh:618
LSQ::LSQRequest::TranslationStarted
@ TranslationStarted
True if any translation has been sent to TLB.
Definition: lsq.hh:244
LSQ::resetHtmStartsStops
void resetHtmStartsStops(ThreadID tid)
Definition: lsq.hh:983
LSQ::LSQSenderState::LSQSenderState
LSQSenderState(LSQRequest *request, bool isLoad_)
Default constructor.
Definition: lsq.hh:80
Flags< FlagsStorage >
LSQ::LSQSenderState::writebackDone
void writebackDone()
Definition: lsq.hh:116
LSQ::LSQSenderState::pendingPacket
PacketPtr pendingPacket
A second packet from a split store that needs sending.
Definition: lsq.hh:92
LSQ::LSQSenderState::outstanding
uint8_t outstanding
Number of outstanding packets to complete.
Definition: lsq.hh:94
LSQ::LSQSenderState::request
LSQRequest * request()
Definition: lsq.hh:114
ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:231
LSQ::LSQRequest::isDelayed
bool isDelayed()
Definition: lsq.hh:284
LSQ::SplitDataRequest::initiateTranslation
virtual void initiateTranslation()
Definition: lsq_impl.hh:886
LSQ::LSQSenderState::inst
DynInstPtr inst
Instruction which initiated the access to memory.
Definition: lsq.hh:88
LSQ::LSQRequest::_amo_op
AtomicOpFunctorPtr _amo_op
Definition: lsq.hh:300
tlb.hh
LSQ::LSQRequest::flags
FlagsType flags
Definition: lsq.hh:263
LSQ::LSQRequest::Discarded
@ Discarded
Request discarded.
Definition: lsq.hh:254
BaseTLB::Mode
Mode
Definition: tlb.hh:57
LSQ::LSQRequest::request
const RequestPtr request(int idx=0) const
Definition: lsq.hh:476
PacketDataPtr
uint8_t * PacketDataPtr
Definition: packet.hh:67
LSQ::DcachePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Timing version of receive.
Definition: lsq_impl.hh:1217
LSQ::numLoads
int numLoads(ThreadID tid)
Returns the total number of loads for a single thread.
Definition: lsq.hh:958
LSQ::LSQRequest::FlagsType
::Flags< FlagsStorage > FlagsType
Definition: lsq.hh:234
LSQ::LSQRequest::_data
PacketDataPtr _data
Definition: lsq.hh:290
LSQ::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Handles writing back and completing the load or store that has returned from memory.
Definition: lsq_impl.hh:315
LSQ::LSQRequest::_senderState
LSQSenderState * _senderState
Definition: lsq.hh:274
LSQ::LSQRequest::Retry
@ Retry
Definition: lsq.hh:248
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:82
LSQ::SingleDataRequest::buildPackets
virtual void buildPackets()
Definition: lsq_impl.hh:1022
LSQ::setLastRetiredHtmUid
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
Definition: lsq.hh:997
LSQ::recvReqRetry
void recvReqRetry()
Retry the previous send that failed.
Definition: lsq_impl.hh:294
LSQ::DcachePort::DcachePort
DcachePort(LSQ< Impl > *_lsq, FullO3CPU< Impl > *_cpu)
Default constructor.
Definition: lsq.hh:132
std::vector
STL vector class.
Definition: stl.hh:37
LSQ::LSQSenderState::isComplete
bool isComplete()
Completes a packet and returns whether the access is finished.
Definition: lsq.hh:111
LSQ::SingleDataRequest::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Definition: lsq_impl.hh:981
LSQ::SingleDataRequest::SingleDataRequest
SingleDataRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr, AtomicOpFunctorPtr amo_op=nullptr)
Definition: lsq.hh:726
LSQ::LSQRequest::_port
LSQUnit & _port
Definition: lsq.hh:287
LSQ::LSQRequest::sendFragmentToTranslation
void sendFragmentToTranslation(int i)
Definition: lsq_impl.hh:970
LSQ::numStores
int numStores()
Returns the total number of stores in the store queue.
Definition: lsq_impl.hh:406
LSQ::activeThreads
std::list< ThreadID > * activeThreads
List of Active Threads in System.
Definition: lsq.hh:1165
LSQ::violation
bool violation()
Returns whether or not there was a memory ordering violation.
Definition: lsq_impl.hh:276
LSQ::LSQRequest::TranslationFinished
@ TranslationFinished
True if there are un-replied outbound translations.
Definition: lsq.hh:246
LSQ::SplitDataRequest::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Definition: lsq_impl.hh:801
LSQ::LSQRequest::isCacheBlockHit
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)=0
Test if the request accesses a particular cache line.
LSQ::isEmpty
bool isEmpty() const
Returns if the LSQ is empty (both LQ and SQ are empty).
Definition: lsq_impl.hh:503
LSQ::LSQRequest::_numOutstandingPackets
uint32_t _numOutstandingPackets
Definition: lsq.hh:299
LSQ::numLoads
int numLoads()
Returns the total number of loads in the load queue.
Definition: lsq_impl.hh:388
LSQ::LSQSenderState::isSplit
bool isSplit
Whether or not this access is split in two.
Definition: lsq.hh:100
LSQ::LSQRequest::isInTranslation
bool isInTranslation()
Definition: lsq.hh:585
LSQ::tick
void tick()
Ticks the LSQ.
Definition: lsq_impl.hh:170
LSQ::LSQRequest::packetNotSent
void packetNotSent()
Update the status to reflect that a packet was not sent.
Definition: lsq.hh:571
LSQ::LSQRequest::handleLocalAccess
virtual Cycles handleLocalAccess(ThreadContext *thread, PacketPtr pkt)=0
Memory mapped IPR accesses.
LSQ::getCount
int getCount(ThreadID tid)
Returns the number of instructions in the queues of one thread.
Definition: lsq.hh:953
LSQ::LSQRequest::isLoad
bool isLoad() const
Definition: lsq.hh:337
LSQ::LSQRequest::packetSent
void packetSent()
Update the status to reflect that a packet was sent.
Definition: lsq.hh:562
LSQ::lqFull
bool lqFull()
Returns if any of the LQs are full.
Definition: lsq_impl.hh:544
LSQ::isFull
bool isFull()
Returns if the LSQ is full (either LQ or SQ is full).
Definition: lsq_impl.hh:474
isAnyActiveElement
bool isAnyActiveElement(const std::vector< bool >::const_iterator &it_start, const std::vector< bool >::const_iterator &it_end)
Test if there is any active element in an enablement range.
Definition: utils.hh:86
LSQ::completeDataAccess
void completeDataAccess(PacketPtr pkt)
Definition: lsq_impl.hh:306
LSQ::isDrained
bool isDrained() const
Has the LSQ drained?
Definition: lsq_impl.hh:139
LSQ::LSQSenderState::deleteRequest
void deleteRequest()
Definition: lsq.hh:112
LSQ::iewStage
IEW * iewStage
The IEW stage pointer.
Definition: lsq.hh:1112
LSQ::LSQRequest::_requests
std::vector< RequestPtr > _requests
Definition: lsq.hh:292
LSQ::SplitDataRequest::sendPacketToCache
virtual void sendPacketToCache()
Definition: lsq_impl.hh:1131
LSQ::LSQRequest::markDelayed
void markDelayed() override
Signal that the translation has been delayed due to a hw page table walk.
Definition: lsq.hh:283
LSQ::LSQRequest::State::Request
@ Request
LSQ::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: lsq_impl.hh:158
RequestorID
uint16_t RequestorID
Definition: request.hh:85
LSQ::dcachePort
DcachePort dcachePort
Data port.
Definition: lsq.hh:1179
LSQ::O3CPU
Impl::O3CPU O3CPU
Definition: lsq.hh:66
LSQUnit
Class that implements the actual LQ and SQ for each specific thread.
Definition: lsq_unit.hh:78
LSQ::LSQRequest::_byteEnable
std::vector< bool > _byteEnable
Definition: lsq.hh:298
LSQ::LSQRequest::_taskId
uint32_t _taskId
Definition: lsq.hh:289
LSQ::LSQRequest::isComplete
bool isComplete()
Definition: lsq.hh:579
LSQ::LSQRequest::isReleased
bool isReleased()
Test if the LSQRequest has been released, i.e.
Definition: lsq.hh:371
LSQ::numStores
int numStores(ThreadID tid)
Returns the total number of stores for a single thread.
Definition: lsq.hh:963
LSQ::usedLoadPorts
int usedLoadPorts
The number of used cache ports in this cycle by loads.
Definition: lsq.hh:1135
LSQ::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: lsq_impl.hh:129
LSQ::SplitDataRequest::name
virtual std::string name() const
Definition: lsq.hh:849
LSQ::LSQRequest::addRequest
void addRequest(Addr addr, unsigned size, const std::vector< bool > &byte_enable)
Helper function used to add a (sub)request, given its address addr, size size and byte-enable mask by...
Definition: lsq.hh:406
LSQ::LSQRequest::~LSQRequest
virtual ~LSQRequest()
Destructor.
Definition: lsq.hh:426
LSQ::LSQSenderState::alive
bool alive()
Definition: lsq.hh:113
LSQUnit::loadQueue
LoadQueue loadQueue
The load queue.
Definition: lsq_unit.hh:498
LSQ::isStalled
bool isStalled()
Returns if the LSQ is stalled due to a memory operation that must be replayed.
Definition: lsq_impl.hh:602
inst_seq.hh
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:431
LSQ::LSQRequest::WbStore
@ WbStore
True if this is a store/atomic that writes registers (SC).
Definition: lsq.hh:240
LSQ::read
Fault read(LSQRequest *req, int load_idx)
Executes a read operation, using the load specified at the load index.
Definition: lsq.hh:1190
LSQ
Definition: lsq.hh:62
Flags::clear
void clear()
Definition: flags.hh:85
LSQ::cachePortAvailable
bool cachePortAvailable(bool is_load) const
Is any store port available to use?
Definition: lsq_impl.hh:196
LSQ::getStoreHeadSeqNum
InstSeqNum getStoreHeadSeqNum(ThreadID tid)
Returns the sequence number of the head of the store queue.
Definition: lsq.hh:945
sim_object.hh
LSQ::LSQRequest::_flags
const Request::Flags _flags
Definition: lsq.hh:297
LSQ::DcachePort::cpu
FullO3CPU< Impl > * cpu
Definition: lsq.hh:128
LSQ::LSQRequest::LSQRequest
LSQRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr, AtomicOpFunctorPtr amo_op=nullptr)
Definition: lsq.hh:315
LSQ::SingleDataRequest::sendPacketToCache
virtual void sendPacketToCache()
Definition: lsq_impl.hh:1122
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
MipsISA::vaddr
vaddr
Definition: pra_constants.hh:275
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
LSQ::LSQRequest::isPartialFault
bool isPartialFault()
Definition: lsq.hh:612
LSQ::LSQRequest::_res
uint64_t * _res
Definition: lsq.hh:294
LSQ::dumpInsts
void dumpInsts(ThreadID tid) const
Debugging function to print out instructions from a specific thread.
Definition: lsq.hh:1075
ArmISA::st
Bitfield< 31, 28 > st
Definition: miscregs_types.hh:152
LSQ::LSQRequest::Delayed
@ Delayed
Definition: lsq.hh:241
MipsISA::r
r
Definition: pra_constants.hh:95
LSQ::LSQSenderState
Derived class to hold any sender state the LSQ needs.
Definition: lsq.hh:73
LSQ::LSQRequest::_entryIdx
uint32_t _entryIdx
LQ/SQ entry idx.
Definition: lsq.hh:281
LSQ::cachePortBusy
void cachePortBusy(bool is_load)
Another store port is in use.
Definition: lsq_impl.hh:209
LSQ::numFreeStoreEntries
unsigned numFreeStoreEntries()
Returns the number of free store entries.
Definition: lsq_impl.hh:442
LSQ::SplitDataRequest::buildPackets
virtual void buildPackets()
Definition: lsq_impl.hh:1056
LSQ::getLoadHeadSeqNum
InstSeqNum getLoadHeadSeqNum(ThreadID tid)
Returns the sequence number of the head of the load queue.
Definition: lsq.hh:935
LSQ::executeLoad
Fault executeLoad(const DynInstPtr &inst)
Executes a load.
Definition: lsq_impl.hh:239
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
LSQ::maxLSQAllocation
static uint32_t maxLSQAllocation(SMTQueuePolicy pol, uint32_t entries, uint32_t numThreads, uint32_t SMTThreshold)
Auxiliary function to calculate per-thread max LSQ allocation limit.
Definition: lsq.hh:1147
LSQ::LSQRequest::isTranslationComplete
bool isTranslationComplete()
Definition: lsq.hh:591
LSQ::LSQRequest::taskId
uint32_t taskId() const
Definition: lsq.hh:472
port.hh
LSQ::LSQRequest::install
void install()
Install the request in the LQ/SQ.
Definition: lsq.hh:349
LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:1123
LSQ::IEW
Impl::CPUPol::IEW IEW
Definition: lsq.hh:68
LSQ::HtmCmdRequest
Definition: lsq.hh:750
BaseTLB::Translation
Definition: tlb.hh:59
LSQ::lqEmpty
bool lqEmpty() const
Returns if all of the LQs are empty.
Definition: lsq_impl.hh:510
Flags::set
void set(Type flags)
Definition: flags.hh:87
LSQ::DynInstPtr
Impl::DynInstPtr DynInstPtr
Definition: lsq.hh:67
LSQ::LSQRequest::senderState
void senderState(LSQSenderState *st)
Definition: lsq.hh:501
LSQ::LSQRequest::_packets
std::vector< PacketPtr > _packets
Definition: lsq.hh:291
LSQ::pushRequest
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable)
Definition: lsq_impl.hh:677
LSQ::HtmCmdRequest::~HtmCmdRequest
virtual ~HtmCmdRequest()
Definition: lsq.hh:768
LSQ::SplitDataRequest::SplitDataRequest
SplitDataRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr)
Definition: lsq.hh:813
LSQ::HtmCmdRequest::name
virtual std::string name() const
Definition: lsq.hh:772
LSQ::LSQRequest::setStateToFault
void setStateToFault()
Definition: lsq.hh:625
LSQ::usedStorePorts
int usedStorePorts
The number of used cache ports in this cycle by stores.
Definition: lsq.hh:1131
LSQ::getLatestHtmUid
uint64_t getLatestHtmUid(ThreadID tid) const
Definition: lsq.hh:989
LSQ::LQEntries
unsigned LQEntries
Total Size of LQ Entries.
Definition: lsq.hh:1168
LSQ::LSQRequest::WritebackScheduled
@ WritebackScheduled
Store written back.
Definition: lsq.hh:258
RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:74
LSQ::LSQRequest::instruction
const DynInstPtr & instruction()
Definition: lsq.hh:449
LSQ::getCount
int getCount()
Returns the number of instructions in all of the queues.
Definition: lsq_impl.hh:370
LSQ::LSQRequest::IsSplit
@ IsSplit
Definition: lsq.hh:242
LSQ::LSQRequest::initiateTranslation
virtual void initiateTranslation()=0
InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:37
LSQ::SplitDataRequest::numFragments
uint32_t numFragments
Definition: lsq.hh:807
LSQ::writebackStores
void writebackStores()
Attempts to write back stores until all cache ports are used or the interface becomes blocked.
Definition: lsq_impl.hh:257
LSQ::LSQSenderState::needWB
bool needWB
Whether or not the instruction will need to writeback.
Definition: lsq.hh:98
LSQ::LSQRequest::setContext
void setContext(const ContextID &context_id)
Convenience getters/setters.
Definition: lsq.hh:443
LSQ::SingleDataRequest::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Definition: lsq_impl.hh:768
LSQ::SplitDataRequest::mainReq
RequestPtr mainReq
Definition: lsq.hh:809
LSQ::LSQRequest::isAnyOutstandingRequest
bool isAnyOutstandingRequest()
Test if there is any in-flight translation or mem access request.
Definition: lsq.hh:531
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
LSQ::LSQRequest::LSQRequest
LSQRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad)
Definition: lsq.hh:303
Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:106
LSQ::LSQRequest::State::Fault
@ Fault
LSQ::getStoreHead
int getStoreHead(ThreadID tid)
Returns the head index of the store queue.
Definition: lsq.hh:941
LSQ::LSQRequest::writebackScheduled
void writebackScheduled()
Definition: lsq.hh:658
LSQ::LSQRequest::Sent
@ Sent
Definition: lsq.hh:247
LSQ::getLoadHead
int getLoadHead(ThreadID tid)
Returns the head index of the load queue for a specific thread.
Definition: lsq.hh:931
LSQ::numFreeLoadEntries
unsigned numFreeLoadEntries()
Returns the number of free load entries.
Definition: lsq_impl.hh:424
LSQ::LSQRequest::release
void release(Flag reason)
Release the LSQRequest.
Definition: lsq.hh:386
LSQ::LSQRequest::isSplit
bool isSplit() const
Definition: lsq.hh:540
LSQ::write
Fault write(LSQRequest *req, uint8_t *data, int store_idx)
Executes a store operation, using the store specified at the store index.
Definition: lsq.hh:1199
LSQ::LSQRequest::freeLSQEntry
void freeLSQEntry()
The LSQ entry is cleared.
Definition: lsq.hh:634
LSQ::maxLQEntries
unsigned maxLQEntries
Max LQ Size - Used to Enforce Sharing Policies.
Definition: lsq.hh:1173
LSQ::LSQRequest::getVaddr
Addr getVaddr(int idx=0) const
Definition: lsq.hh:481
LSQ::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets the pointer to the list of active threads.
Definition: lsq_impl.hh:121
LSQ::LSQRequest::setState
void setState(const State &newState)
Definition: lsq.hh:275
LSQ::DcachePort::recvTimingSnoopReq
virtual void recvTimingSnoopReq(PacketPtr pkt)
Receive a timing snoop request from the peer.
Definition: lsq_impl.hh:1224
LSQ::LSQRequest::_fault
std::vector< Fault > _fault
Definition: lsq.hh:293
LSQ::SQEntries
unsigned SQEntries
Total Size of SQ Entries.
Definition: lsq.hh:1170
LSQ::hasStoresToWB
bool hasStoresToWB()
Returns whether or not there are any stores to write back to memory.
Definition: lsq_impl.hh:629
LSQ::LSQRequest::State
State
Definition: lsq.hh:265
LSQ::LSQRequest::Flag
Flag
Definition: lsq.hh:236
LSQ::LSQRequest::FlagsStorage
uint32_t FlagsStorage
Definition: lsq.hh:233
LSQ::LSQRequest::_addr
const Addr _addr
Definition: lsq.hh:295
LSQ::LSQRequest::TranslationSquashed
@ TranslationSquashed
Ownership tracking flags.
Definition: lsq.hh:252
LSQ::LSQRequest
Memory operation metadata.
Definition: lsq.hh:230
LSQ::LSQRequest::packet
PacketPtr packet(int idx=0)
Definition: lsq.hh:484
LSQ::LSQRequest::squashTranslation
void squashTranslation()
Definition: lsq.hh:675
LSQ::SplitDataRequest::handleLocalAccess
virtual Cycles handleLocalAccess(ThreadContext *thread, PacketPtr pkt)
Memory mapped IPR accesses.
Definition: lsq_impl.hh:1151
LSQ::LSQRequest::complete
void complete()
Definition: lsq.hh:686
LSQ::HtmCmdRequest::initiateTranslation
virtual void initiateTranslation()
Definition: lsq_impl.hh:1272
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
LSQ::LSQSenderState::mainPkt
PacketPtr mainPkt
The main packet from a split load, used during writeback.
Definition: lsq.hh:90
LSQ::LSQRequest::State::PartialFault
@ PartialFault
LSQ::LSQRequest::writebackDone
void writebackDone()
Definition: lsq.hh:665
LSQ::LSQSenderState::isLoad
bool isLoad
Whether or not it is a load.
Definition: lsq.hh:96
LSQ::numFreeEntries
unsigned numFreeEntries(ThreadID tid)
Returns the number of free entries for a specific thread.
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
LSQ::LSQRequest::isSent
bool isSent()
Definition: lsq.hh:606
LSQ::cacheLoadPorts
int cacheLoadPorts
The number of cache ports available each cycle (loads only).
Definition: lsq.hh:1133
addr
ip6_addr_t addr
Definition: inet.hh:423
LSQUnit::storeQueue
CircularQueue< SQEntry > storeQueue
The store queue.
Definition: lsq_unit.hh:495
LSQ::LSQRequest::numTranslatedFragments
uint32_t numTranslatedFragments
Definition: lsq.hh:277
lsq_unit.hh
LSQ::hasStoresToWB
bool hasStoresToWB(ThreadID tid)
Returns whether or not a specific thread has any stores to write back to memory.
Definition: lsq.hh:1060
LSQ::LSQRequest::sendPacketToCache
virtual void sendPacketToCache()=0
LSQ::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt)
Definition: lsq_impl.hh:353
LSQ::LSQRequest::State::NotIssued
@ NotIssued
LSQ::squash
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squash instructions from a thread until the specified sequence number.
Definition: lsq.hh:910
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
LSQ::SingleDataRequest
Definition: lsq.hh:694
LSQ::sqFull
bool sqFull()
Returns if any of the SQs are full.
Definition: lsq_impl.hh:573
LSQ::DcachePort::isSnooping
virtual bool isSnooping() const
As this CPU requires snooping to maintain the load store queue change the behaviour from the base CPU...
Definition: lsq.hh:159
LSQ::LSQRequest::taskId
void taskId(const uint32_t &v)
Definition: lsq.hh:465
LSQ::cacheBlocked
bool cacheBlocked() const
Is D-cache blocked?
Definition: lsq_impl.hh:182
LSQ::LSQRequest::isTranslationBlocked
bool isTranslationBlocked()
Definition: lsq.hh:598
LSQ::LSQRequest::_inst
const DynInstPtr _inst
Definition: lsq.hh:288
LSQ::SplitDataRequest::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Definition: lsq_impl.hh:994
LSQ::DcachePort
DcachePort class for the load/store queue.
Definition: lsq.hh:122
LSQ::numStoresToWB
int numStoresToWB(ThreadID tid)
Returns the number of stores a specific thread has to write back.
Definition: lsq.hh:1063
LSQ::LSQRequest::lsqUnit
LSQUnit * lsqUnit()
Definition: lsq.hh:302
Complete
@ Complete
Definition: misc.hh:55
LSQ::entryAmount
int entryAmount(ThreadID num_threads)
Number of entries needed for the given amount of threads.
LSQ::getMemDepViolator
DynInstPtr getMemDepViolator(ThreadID tid)
Gets the instruction that caused the memory ordering violation.
Definition: lsq.hh:925
LSQ::SplitDataRequest
Definition: lsq.hh:775
LSQ::lsqPolicy
SMTQueuePolicy lsqPolicy
The LSQ policy for SMT mode.
Definition: lsq.hh:1139
Flags::isSet
bool isSet() const
Definition: flags.hh:79
LSQ::LSQSenderState::contextId
ContextID contextId()
Definition: lsq.hh:108
LSQ::LSQRequest::senderState
const LSQSenderState * senderState() const
Definition: lsq.hh:511
LSQ::name
std::string name() const
Returns the name of the LSQ.
Definition: lsq_impl.hh:114
std::list< ThreadID >
LSQ::commitLoads
void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
Commits loads up until the given sequence number for a specific thread.
Definition: lsq.hh:889
LSQ::~LSQ
~LSQ()
Definition: lsq.hh:854
LSQ::cacheStorePorts
int cacheStorePorts
The number of cache ports available each cycle (stores only).
Definition: lsq.hh:1129
LSQ::LSQRequest::_state
State _state
Definition: lsq.hh:273
LSQ::LSQRequest::WritebackDone
@ WritebackDone
Definition: lsq.hh:259
LSQ::_cacheBlocked
bool _cacheBlocked
D-cache is blocked.
Definition: lsq.hh:1127
LSQ::SingleDataRequest::initiateTranslation
virtual void initiateTranslation()
Definition: lsq_impl.hh:850
LSQ::SplitDataRequest::isCacheBlockHit
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)
Caches may probe into the load-store queue to enforce memory ordering guarantees.
Definition: lsq_impl.hh:1194
LSQ::LSQRequest::_size
const uint32_t _size
Definition: lsq.hh:296
LSQ::LSQRequest::mainRequest
virtual RequestPtr mainRequest()
Definition: lsq.hh:494
LSQ::LSQRequest::discardSenderState
void discardSenderState()
Mark senderState as discarded.
Definition: lsq.hh:521
LSQ::LSQSenderState::_request
LSQRequest * _request
The senderState needs to know the LSQRequest who owns it.
Definition: lsq.hh:77
LSQ::LSQRequest::name
virtual std::string name() const
Definition: lsq.hh:691
LSQ::numHtmStarts
int numHtmStarts(ThreadID tid) const
Definition: lsq.hh:968
LSQ::HtmCmdRequest::HtmCmdRequest
HtmCmdRequest(LSQUnit *port, const DynInstPtr &inst, const Request::Flags &flags_)
Definition: lsq_impl.hh:1242
LSQ::SingleDataRequest::isCacheBlockHit
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)
Test if the request accesses a particular cache line.
Definition: lsq_impl.hh:1172
LSQ::DcachePort::recvReqRetry
virtual void recvReqRetry()
Handles doing a retry of the previous send.
Definition: lsq_impl.hh:1236
LSQ::SingleDataRequest::name
virtual std::string name() const
Definition: lsq.hh:744
ArmISA::v
Bitfield< 28 > v
Definition: miscregs_types.hh:51
LSQ::SplitDataRequest::_mainPacket
PacketPtr _mainPacket
Definition: lsq.hh:810
LSQ::dumpInsts
void dumpInsts() const
Debugging function to print out all instructions.
Definition: lsq_impl.hh:663
LSQ::LSQRequest::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)=0
LSQ::LSQRequest::IsLoad
@ IsLoad
Definition: lsq.hh:238
LSQ::DcachePort::recvFunctionalSnoop
virtual void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the peer.
Definition: lsq.hh:145
LSQ::LSQRequest::LSQEntryFreed
@ LSQEntryFreed
LSQ resources freed.
Definition: lsq.hh:256
LSQ::LSQSenderState::complete
virtual void complete()=0
LSQ::cpu
O3CPU * cpu
The CPU pointer.
Definition: lsq.hh:1109
LSQ::LSQRequest::setVirt
void setVirt(Addr vaddr, unsigned size, Request::Flags flags_, RequestorID requestor_id, Addr pc)
Set up virtual request.
Definition: lsq.hh:458
LSQ::LSQSenderState::pktToSend
bool pktToSend
Whether or not there is a packet that needs sending.
Definition: lsq.hh:102
LSQ::numThreads
ThreadID numThreads
Number of Threads.
Definition: lsq.hh:1185
LSQ::LSQRequest::mainPacket
virtual PacketPtr mainPacket()
Definition: lsq.hh:487
LSQ::LSQRequest::request
RequestPtr request(int idx=0)
Definition: lsq.hh:473
LSQ::LSQRequest::State::Translation
@ Translation

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