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42 #ifndef __CPU_O3_INST_QUEUE_HH__
43 #define __CPU_O3_INST_QUEUE_HH__
56 #include "enums/SMTQueuePolicy.hh"
59 struct DerivO3CPUParams;
85 typedef typename Impl::O3CPU
O3CPU;
88 typedef typename Impl::CPUPol::IEW
IEW;
130 std::string
name()
const;
339 return lhs->seqNum > rhs->seqNum;
343 typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
360 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator
NonSpecMapIt;
545 #endif //__CPU_O3_INST_QUEUE_HH__
static const OpClass Num_OpClasses
std::map< InstSeqNum, DynInstPtr > nonSpecInsts
List of non-speculative instructions that will be scheduled once the IQ gets a signal from commit.
void addIfReady(const DynInstPtr &inst)
Moves an instruction to the ready queue if it is ready.
void takeOverFrom()
Takes over execution from another CPU's thread.
Stats::Formula fuBusyRate
Number of times the FU was busy per instruction issued.
Stats::Scalar vecAluAccesses
IEW * iewStage
Pointer to IEW stage.
int wakeDependents(const DynInstPtr &completed_inst)
Wakes all dependents of a completed instruction.
void commit(const InstSeqNum &inst, ThreadID tid=0)
Commits all instructions up to and including the given sequence number, for a specific thread.
ReadyInstQueue readyInsts[Num_OpClasses]
List of ready instructions, per op class.
std::string name() const
Returns the name of the IQ.
Stats::Scalar iqBranchInstsIssued
Stat for number of branch instructions issued.
TimeBuffer< TimeStruct >::wire fromCommit
Wire to read information from timebuffer.
DynInstPtr getDeferredMemInstToExecute()
Gets a memory instruction that was referred due to a delayed DTB translation if it is now ready to ex...
void squash(ThreadID tid)
Squashes instructions for a thread.
DynInstPtr getBlockedMemInstToExecute()
Gets a memory instruction that was blocked on the cache.
unsigned count[Impl::MaxThreads]
Per Thread IQ count.
int16_t ThreadID
Thread index/ID type.
Stats::Scalar iqSquashedInstsIssued
Stat for number of squashed instructions that were ready to issue.
TimeBuffer< TimeStruct > * timeBuffer
The backwards time buffer.
Cycles commitToIEWDelay
Delay between commit stage and the IQ.
SMTQueuePolicy iqPolicy
IQ sharing policy for SMT.
std::list< ListOrderEntry >::iterator ListOrderIt
void resetEntries()
Resets max entries for all threads.
Stats::Scalar vecInstQueueWrites
std::list< DynInstPtr > retryMemInsts
List of instructions that were cache blocked, but a retry has been seen since, so they can now be ret...
void resetState()
Resets all instruction queue state.
int entryAmount(ThreadID num_threads)
Number of entries needed for given amount of threads.
void deferMemInst(const DynInstPtr &deferred_inst)
Defers a memory instruction when its DTB translation incurs a hw page table walk.
std::map< InstSeqNum, DynInstPtr >::iterator NonSpecMapIt
void drainSanityCheck() const
Perform sanity checks after a drain.
~InstructionQueue()
Destructs the IQ.
Stats::Scalar iqIntInstsIssued
Stat for number of integer instructions issued.
Stats::Vector2d statIssuedInstType
Stat for total number issued for each instruction type.
int countInsts()
Debugging function to count how many entries are in the IQ.
Stats::Vector fuBusy
Number of times the FU was busy.
DependencyGraph< DynInstPtr > dependGraph
std::list< DynInstPtr >::iterator ListIt
Stats::Scalar iqSquashedOperandsExamined
Stat for number of squashed instruction operands examined when squashing.
unsigned maxEntries[Impl::MaxThreads]
Max IQ Entries Per Thread.
int fuIdx
Index of the FU used for executing.
void blockMemInst(const DynInstPtr &blocked_inst)
Defers a memory instruction when it is cache blocked.
Stats::Scalar vecInstQueueWakeupAccesses
void moveToYoungerInst(ListOrderIt age_order_it)
Called when the oldest instruction has been removed from a ready queue; this places that ready queue ...
Stats::Scalar fpInstQueueReads
void cacheUnblocked()
Notify instruction queue that a previous blockage has resolved.
Pool of FU's, specific to the new CPU model.
A vector of scalar stats.
void setIssueToExecuteQueue(TimeBuffer< IssueStruct > *i2eQueue)
Sets the timer buffer between issue and execute.
std::priority_queue< DynInstPtr, std::vector< DynInstPtr >, pqCompare > ReadyInstQueue
void printInsts()
Debug function to print all instructions.
unsigned numPhysRegs
The number of physical registers in the CPU.
ListOrderIt readyIt[Num_OpClasses]
Iterators of each ready queue.
Array of linked list that maintains the dependencies between producing instructions and consuming ins...
Stats::Scalar iqSquashedInstsExamined
Stat for number of squashed instructions examined when squashing.
Stats::Scalar intInstQueueReads
void processFUCompletion(const DynInstPtr &inst, int fu_idx)
Process FU completion event.
O3CPU * cpu
Pointer to the CPU.
This is a simple scalar statistic, like a counter.
FUPool * fuPool
Function unit pool.
std::list< DynInstPtr > deferredMemInsts
List of instructions waiting for their DTB translation to complete (hw page table walk in progress).
Stats::Scalar iqNonSpecInstsAdded
Stat for number of non-speculative instructions added.
Stats::Distribution numIssuedDist
Distribution of number of instructions in the queue.
unsigned totalWidth
The total number of instructions that can be issued in one cycle.
Stats::Formula issueRate
Number of instructions issued per cycle.
Stats::Vector statFuBusy
Distribution of the cycles it takes to issue an instruction.
Impl::CPUPol::MemDepUnit MemDepUnit
Impl::CPUPol::TimeStruct TimeStruct
Entry for the list age ordering by op class.
MemDepUnit memDepUnit[Impl::MaxThreads]
The memory dependence unit, which tracks/predicts memory dependences between instructions.
void insert(const DynInstPtr &new_inst)
Inserts a new instruction into the IQ.
void regStats()
Registers statistics.
void addToProducers(const DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a producer.
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
bool isDrained() const
Determine if we are drained.
Stats::Scalar iqFloatInstsIssued
Stat for number of floating point instructions issued.
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
void dumpLists()
Debugging function to dump all the list sizes, as well as print out the list of nonspeculative instru...
unsigned freeEntries
Number of free IQ entries left.
ThreadID numThreads
Number of Total Threads.
Stats::Scalar vecInstQueueReads
Stats::Scalar iqMiscInstsIssued
Stat for number of miscellaneous instructions issued.
Struct for comparing entries to be added to the priority queue.
int wbOutstanding
Number of instructions currently in flight to FUs.
void recordProducer(const DynInstPtr &inst)
Records the instruction as the producer of a register without adding it to the rest of the IQ.
InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
Constructs an IQ.
Stats::Scalar iqInstsAdded
Stat for number of instructions added.
Stats::Scalar fpInstQueueWakeupAccesses
void replayMemInst(const DynInstPtr &replay_inst)
Replays a memory instruction.
void dumpInsts()
Debugging function to dump out all instructions that are in the IQ.
void insertNonSpec(const DynInstPtr &new_inst)
Inserts a new, non-speculative instruction into the IQ.
void doSquash(ThreadID tid)
Does the actual squashing.
std::list< DynInstPtr > instsToExecute
List of instructions that are ready to be executed.
Stats::Scalar fpAluAccesses
void scheduleReadyInsts()
Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute.
Stats::Scalar intAluAccesses
A simple distribution stat.
Impl::DynInstPtr DynInstPtr
InstSeqNum squashedSeqNum[Impl::MaxThreads]
The sequence number of the squashed instruction.
void scheduleNonSpec(const InstSeqNum &inst)
Schedules a single specific non-speculative instruction.
void violation(const DynInstPtr &store, const DynInstPtr &faulting_load)
Indicates an ordering violation between a store and a load.
FUCompletion(const DynInstPtr &_inst, int fu_idx, InstructionQueue< Impl > *iq_ptr)
Construct a FU completion event.
Stats::Scalar iqInstsIssued
bool queueOnList[Num_OpClasses]
Tracks if each ready queue is on the age order list.
InstructionQueue< Impl > * iqPtr
Pointer back to the instruction queue.
bool freeFU
Should the FU be added to the list to be freed upon completing this event.
virtual const char * description() const
Return a C string describing the event.
A 2-Dimensional vecto of scalar stats.
unsigned numEntries
The number of entries in the instruction queue.
bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const
DynInstPtr getInstToExecute()
Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to exe...
MemInterface * dcacheInterface
Cache interface.
Stats::Scalar iqMemInstsIssued
Stat for number of memory instructions issued.
DynInstPtr inst
Executing instruction.
A standard instruction queue class.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets active threads list.
void addToOrderList(OpClass op_class)
Add an op class to the age order list.
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly.
Cycles is a wrapper class for representing cycle counts, i.e.
Stats::Scalar fpInstQueueWrites
std::list< DynInstPtr > instList[Impl::MaxThreads]
List of all the instructions in the IQ (some of which may be issued).
std::vector< bool > regScoreboard
A cache of the recently woken registers.
std::list< DynInstPtr > blockedMemInsts
List of instructions that have been cache blocked.
bool addToDependents(const DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a consumer.
unsigned numFreeEntries()
Returns total number of free entries.
Memory dependency unit class.
FU completion event class.
void rescheduleMemInst(const DynInstPtr &resched_inst)
Reschedules a memory instruction.
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the global time buffer.
Impl::CPUPol::IssueStruct IssueStruct
bool isFull()
Returns whether or not the IQ is full.
Stats::Scalar intInstQueueWakeupAccesses
TimeBuffer< IssueStruct > * issueToExecuteQueue
The queue to the execute stage.
bool hasReadyInsts()
Returns if there are any ready instructions in the IQ.
Stats::Scalar intInstQueueWrites
Stats::Scalar iqSquashedNonSpecRemoved
Stat for number of non-speculative instructions removed due to a squash.
void addReadyMemInst(const DynInstPtr &ready_inst)
Adds a ready memory instruction to the ready list.
std::list< ListOrderEntry > listOrder
List that contains the age order of the oldest instruction of each ready queue.
General interface to memory device Includes functions and parameters shared across media types.
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