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41 #ifndef __CPU_O3_MEM_DEP_UNIT_HH__
42 #define __CPU_O3_MEM_DEP_UNIT_HH__
47 #include <unordered_map>
48 #include <unordered_set>
52 #include "debug/MemDepUnit.hh"
56 unsigned a = (unsigned)seq_num;
57 unsigned hash = (((
a >> 14) ^ ((
a >> 2) & 0xffff))) & 0x7FFFFFFF;
63 struct DerivO3CPUParams;
79 template <
class MemDepPred,
class Impl>
189 "memdep_count=%i %s\n", memdep_count,
inst->pcState());
203 "memdep_count=%i %s\n", memdep_count,
inst->pcState());
208 std::string
name()
const {
return "memdepentry"; }
230 static int memdep_count;
231 static int memdep_insert;
232 static int memdep_erase;
242 typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash>
MemDepHash;
293 #endif // __CPU_O3_MEM_DEP_UNIT_HH__
bool regsReady
If the registers are ready or not.
MemDepHash::iterator MemDepHashIt
void replay()
Replays all instructions that have been rescheduled by moving them to the ready list.
Impl::DynInstConstPtr DynInstConstPtr
std::string name() const
Returns the name of the memory dependence entry.
void takeOverFrom()
Takes over from another CPU's thread.
int id
The thread id of this memory dependence unit.
std::list< DynInstPtr >::iterator ListIt
void nonSpecInstReady(const DynInstPtr &inst)
Indicate that a non-speculative instruction is ready.
int16_t ThreadID
Thread index/ID type.
std::unordered_map< InstSeqNum, MemDepEntryPtr, SNHash > MemDepHash
void wakeDependents(const DynInstPtr &inst)
Wakes any dependents of a memory instruction.
bool isDrained() const
Determine if we are drained.
bool hasLoadBarrier() const
Is there an outstanding load barrier that loads must wait on.
void issue(const DynInstPtr &inst)
Issues the given instruction.
~MemDepEntry()
Frees any pointers.
MemDepUnit()
Empty constructor.
MemDepHash memDepHash
A hash map of all memory dependence entries.
void completeInst(const DynInstPtr &inst)
Notifies completion of an instruction.
void violation(const DynInstPtr &store_inst, const DynInstPtr &violating_load)
Indicates an ordering violation between a store and a younger load.
InstructionQueue< Impl > * iqPtr
Pointer to the IQ.
Stats::Scalar conflictingLoads
Stat for number of conflicting loads that had to wait for a store.
This is a simple scalar statistic, like a counter.
MemDepEntryPtr & findInHash(const DynInstConstPtr &inst)
Finds the memory dependence entry in the hash map.
MemDepEntry(const DynInstPtr &new_inst)
Constructs a memory dependence entry.
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squashes all instructions up until a given sequence number for a specific thread.
std::list< DynInstPtr > instsToReplay
A list of all instructions that are going to be replayed.
void dumpLists()
Debugging function to dump the lists of instructions.
void insertNonSpec(const DynInstPtr &inst)
Inserts a non-speculative memory instruction.
~MemDepUnit()
Frees up any memory allocated.
Stats::Scalar insertedLoads
Stat for number of inserted loads.
void reschedule(const DynInstPtr &inst)
Reschedules an instruction to be re-executed.
ListIt listIt
The iterator to the instruction's location inside the list.
void moveToReady(MemDepEntryPtr &ready_inst_entry)
Moves an entry to the ready list.
DynInstPtr inst
The instruction being tracked.
void setIQ(InstructionQueue< Impl > *iq_ptr)
Sets the pointer to the IQ.
int memDeps
Number of memory dependencies that need to be satisfied.
std::list< DynInstPtr > instList[Impl::MaxThreads]
A list of all instructions in the memory dependence unit.
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a barrier instruction.
void regsReady(const DynInstPtr &inst)
Indicate that an instruction has its registers ready.
std::unordered_set< InstSeqNum > storeBarrierSNs
Sequence numbers of outstanding store barriers.
void insert(const DynInstPtr &inst)
Inserts a memory instruction.
Stats::Scalar insertedStores
Stat for number of inserted stores.
size_t operator()(const InstSeqNum &seq_num) const
Stats::Scalar conflictingStores
Stat for number of conflicting stores that had to wait for a store.
bool completed
If the instruction is completed.
void insertBarrierSN(const DynInstPtr &barr_inst)
Inserts the SN of a barrier inst.
MemDepPred depPred
The memory dependence predictor.
A standard instruction queue class.
std::string name() const
Returns the name of the memory dependence unit.
Impl::DynInstPtr DynInstPtr
bool squashed
If the instruction is squashed.
std::shared_ptr< MemDepEntry > MemDepEntryPtr
void init(DerivO3CPUParams *params, ThreadID tid)
Initializes the unit with parameters and a thread id.
void drainSanityCheck() const
Perform sanity checks after a drain.
Memory dependency unit class.
void regStats()
Registers statistics.
bool hasStoreBarrier() const
Is there an outstanding store barrier that loads must wait on.
void completed(const DynInstPtr &inst)
Completes a memory instruction.
std::vector< MemDepEntryPtr > dependInsts
A vector of any dependent instructions.
Memory dependence entries that track memory operations, marking when the instruction is ready to exec...
std::unordered_set< InstSeqNum > loadBarrierSNs
Sequence numbers of outstanding load barriers.
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