mem_interface.hh

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/*
 * Copyright (c) 2012-2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2013 Amin Farmahini-Farahani
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __MEM_INTERFACE_HH__
#define __MEM_INTERFACE_HH__
 
#include <deque>
#include <string>
#include <unordered_set>
#include <utility>
#include <vector>
 
#include "base/statistics.hh"
#include "enums/AddrMap.hh"
#include "enums/PageManage.hh"
#include "mem/abstract_mem.hh"
#include "mem/drampower.hh"
#include "mem/mem_ctrl.hh"
#include "params/DRAMInterface.hh"
#include "params/MemInterface.hh"
#include "params/NVMInterface.hh"
#include "sim/eventq.hh"
 
class MemInterface : public AbstractMemory
{
  protected:
    class Bank
    {
 
      public:
        static const uint32_t NO_ROW = -1;
 
        uint32_t openRow;
        uint8_t bank;
        uint8_t bankgr;
 
        Tick rdAllowedAt;
        Tick wrAllowedAt;
        Tick preAllowedAt;
        Tick actAllowedAt;
 
        uint32_t rowAccesses;
        uint32_t bytesAccessed;
 
        Bank() :
            openRow(NO_ROW), bank(0), bankgr(0),
            rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
            rowAccesses(0), bytesAccessed(0)
        { }
    };
 
    MemCtrl* ctrl;
 
    unsigned int maxCommandsPerWindow;
 
    Enums::AddrMap addrMapping;
 
    const uint32_t burstSize;
    const uint32_t deviceSize;
    const uint32_t deviceRowBufferSize;
    const uint32_t devicesPerRank;
    const uint32_t rowBufferSize;
    const uint32_t burstsPerRowBuffer;
    const uint32_t burstsPerStripe;
    const uint32_t ranksPerChannel;
    const uint32_t banksPerRank;
    uint32_t rowsPerBank;
 
    const Tick M5_CLASS_VAR_USED tCK;
    const Tick tCS;
    const Tick tBURST;
    const Tick tRTW;
    const Tick tWTR;
 
    /*
     * @return delay between write and read commands
     */
    virtual Tick writeToReadDelay() const { return tBURST + tWTR; }
 
    /*
     * @return delay between write and read commands
     */
    Tick readToWriteDelay() const { return tBURST + tRTW; }
 
    /*
     * @return delay between accesses to different ranks
     */
    Tick rankToRankDelay() const { return tBURST + tCS; }
 
 
  public:
 
    const uint32_t readBufferSize;
    const uint32_t writeBufferSize;
 
    void setCtrl(MemCtrl* _ctrl, unsigned int command_window);
 
    Addr getCtrlAddr(Addr addr) { return range.getOffset(addr); }
 
    virtual void setupRank(const uint8_t rank, const bool is_read) = 0;
 
    virtual bool allRanksDrained() const = 0;
 
    virtual std::pair<MemPacketQueue::iterator, Tick>
    chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const = 0;
 
    /*
     * Function to calulate unloaded latency
     */
    virtual Tick accessLatency() const = 0;
 
    uint32_t bytesPerBurst() const { return burstSize; }
 
    /*
     * @return time to offset next command
     */
    virtual Tick commandOffset() const = 0;
 
    virtual bool burstReady(MemPacket* pkt) const = 0;
 
    Tick rankDelay() const { return tCS; }
 
    Tick minReadToWriteDataGap() const { return std::min(tRTW, tCS); }
 
    Tick minWriteToReadDataGap() const { return std::min(tWTR, tCS); }
 
    MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
                           unsigned int size, bool is_read, bool is_dram);
 
    virtual void addRankToRankDelay(Tick cmd_at) = 0;
 
    typedef MemInterfaceParams Params;
    MemInterface(const Params* _p);
};
 
class DRAMInterface : public MemInterface
{
  private:
    struct Command
    {
       Data::MemCommand::cmds type;
       uint8_t bank;
       Tick timeStamp;
 
       constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
                         Tick time_stamp)
            : type(_type), bank(_bank), timeStamp(time_stamp)
        { }
    };
 
    enum PowerState
    {
        PWR_IDLE = 0,
        PWR_REF,
        PWR_SREF,
        PWR_PRE_PDN,
        PWR_ACT,
        PWR_ACT_PDN
    };
 
    enum RefreshState
    {
        REF_IDLE = 0,
        REF_DRAIN,
        REF_PD_EXIT,
        REF_SREF_EXIT,
        REF_PRE,
        REF_START,
        REF_RUN
    };
 
    class Rank;
    struct RankStats : public Stats::Group
    {
        RankStats(DRAMInterface &dram, Rank &rank);
 
        void regStats() override;
        void resetStats() override;
        void preDumpStats() override;
 
        Rank &rank;
 
        /*
         * Command energies
         */
        Stats::Scalar actEnergy;
        Stats::Scalar preEnergy;
        Stats::Scalar readEnergy;
        Stats::Scalar writeEnergy;
        Stats::Scalar refreshEnergy;
 
        /*
         * Active Background Energy
         */
        Stats::Scalar actBackEnergy;
 
        /*
         * Precharge Background Energy
         */
        Stats::Scalar preBackEnergy;
 
        /*
         * Active Power-Down Energy
         */
        Stats::Scalar actPowerDownEnergy;
 
        /*
         * Precharge Power-Down Energy
         */
        Stats::Scalar prePowerDownEnergy;
 
        /*
         * self Refresh Energy
         */
        Stats::Scalar selfRefreshEnergy;
 
        Stats::Scalar totalEnergy;
        Stats::Scalar averagePower;
 
        Stats::Scalar totalIdleTime;
 
        Stats::Vector pwrStateTime;
    };
 
    class Rank : public EventManager
    {
      private:
 
        DRAMInterface& dram;
 
        PowerState pwrStateTrans;
 
        PowerState pwrStatePostRefresh;
 
        Tick pwrStateTick;
 
        Tick refreshDueAt;
 
        void updatePowerStats();
 
        void schedulePowerEvent(PowerState pwr_state, Tick tick);
 
      public:
 
        PowerState pwrState;
 
        RefreshState refreshState;
 
        bool inLowPowerState;
 
        uint8_t rank;
 
        uint32_t readEntries;
 
        uint32_t writeEntries;
 
        uint8_t outstandingEvents;
 
        Tick wakeUpAllowedAt;
 
        DRAMPower power;
 
        std::vector<Command> cmdList;
 
        std::vector<Bank> banks;
 
        unsigned int numBanksActive;
 
        std::deque<Tick> actTicks;
 
        Tick lastBurstTick;
 
        Rank(const DRAMInterfaceParams* _p, int _rank,
             DRAMInterface& _dram);
 
        const std::string name() const { return csprintf("%d", rank); }
 
        void startup(Tick ref_tick);
 
        void suspend();
 
        bool inRefIdleState() const { return refreshState == REF_IDLE; }
 
        bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
 
        bool forceSelfRefreshExit() const;
 
        bool isQueueEmpty() const;
 
        void checkDrainDone();
 
        void flushCmdList();
 
        void computeStats();
 
        void resetStats();
 
        void powerDownSleep(PowerState pwr_state, Tick tick);
 
        void scheduleWakeUpEvent(Tick exit_delay);
 
        void processWriteDoneEvent();
        EventFunctionWrapper writeDoneEvent;
 
        void processActivateEvent();
        EventFunctionWrapper activateEvent;
 
        void processPrechargeEvent();
        EventFunctionWrapper prechargeEvent;
 
        void processRefreshEvent();
        EventFunctionWrapper refreshEvent;
 
        void processPowerEvent();
        EventFunctionWrapper powerEvent;
 
        void processWakeUpEvent();
        EventFunctionWrapper wakeUpEvent;
 
      protected:
        RankStats stats;
    };
 
    static bool
    sortTime(const Command& cmd, const Command& cmd_next)
    {
        return cmd.timeStamp < cmd_next.timeStamp;
    }
 
    const uint32_t bankGroupsPerRank;
    const bool bankGroupArch;
 
    const Tick tCL;
    const Tick tBURST_MIN;
    const Tick tBURST_MAX;
    const Tick tCCD_L_WR;
    const Tick tCCD_L;
    const Tick tRCD;
    const Tick tRP;
    const Tick tRAS;
    const Tick tWR;
    const Tick tRTP;
    const Tick tRFC;
    const Tick tREFI;
    const Tick tRRD;
    const Tick tRRD_L;
    const Tick tPPD;
    const Tick tAAD;
    const Tick tXAW;
    const Tick tXP;
    const Tick tXS;
    const Tick clkResyncDelay;
    const bool dataClockSync;
    const bool burstInterleave;
    const uint8_t twoCycleActivate;
    const uint32_t activationLimit;
    const Tick wrToRdDlySameBG;
    const Tick rdToWrDlySameBG;
 
 
    Enums::PageManage pageMgmt;
    const uint32_t maxAccessesPerRow;
 
    // timestamp offset
    uint64_t timeStampOffset;
 
    // Holds the value of the DRAM rank of burst issued
    uint8_t activeRank;
 
    bool enableDRAMPowerdown;
 
    Tick lastStatsResetTick;
 
    void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
                      uint32_t row);
 
    void prechargeBank(Rank& rank_ref, Bank& bank_ref,
                       Tick pre_tick, bool auto_or_preall = false,
                       bool trace = true);
 
    struct DRAMStats : public Stats::Group
    {
        DRAMStats(DRAMInterface &dram);
 
        void regStats() override;
        void resetStats() override;
 
        DRAMInterface &dram;
 
        Stats::Scalar readBursts;
        Stats::Scalar writeBursts;
 
        Stats::Vector perBankRdBursts;
        Stats::Vector perBankWrBursts;
 
        // Latencies summed over all requests
        Stats::Scalar totQLat;
        Stats::Scalar totBusLat;
        Stats::Scalar totMemAccLat;
 
        // Average latencies per request
        Stats::Formula avgQLat;
        Stats::Formula avgBusLat;
        Stats::Formula avgMemAccLat;
 
        // Row hit count and rate
        Stats::Scalar readRowHits;
        Stats::Scalar writeRowHits;
        Stats::Formula readRowHitRate;
        Stats::Formula writeRowHitRate;
        Stats::Histogram bytesPerActivate;
        // Number of bytes transferred to/from DRAM
        Stats::Scalar bytesRead;
        Stats::Scalar bytesWritten;
 
        // Average bandwidth
        Stats::Formula avgRdBW;
        Stats::Formula avgWrBW;
        Stats::Formula peakBW;
        // bus utilization
        Stats::Formula busUtil;
        Stats::Formula busUtilRead;
        Stats::Formula busUtilWrite;
        Stats::Formula pageHitRate;
    };
 
    DRAMStats stats;
 
    std::vector<Rank*> ranks;
 
    /*
     * @return delay between write and read commands
     */
    Tick writeToReadDelay() const override { return tBURST + tWTR + tCL; }
 
    std::pair<std::vector<uint32_t>, bool>
    minBankPrep(const MemPacketQueue& queue, Tick min_col_at) const;
 
    /*
     * @return time to send a burst of data without gaps
     */
    Tick
    burstDelay() const
    {
        return (burstInterleave ? tBURST_MAX / 2 : tBURST);
    }
 
  public:
    void init() override;
 
    void startup() override;
 
    void setupRank(const uint8_t rank, const bool is_read) override;
 
    void drainRanks();
 
    bool allRanksDrained() const override;
 
    void suspend();
 
    /*
     * @return time to offset next command
     */
    Tick commandOffset() const override { return (tRP + tRCD); }
 
    /*
     * Function to calulate unloaded, closed bank access latency
     */
    Tick accessLatency() const override { return (tRP + tRCD + tCL); }
 
    std::pair<MemPacketQueue::iterator, Tick>
    chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
 
    std::pair<Tick, Tick>
    doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
                  const std::vector<MemPacketQueue>& queue);
 
    bool
    burstReady(MemPacket* pkt) const override
    {
        return ranks[pkt->rank]->inRefIdleState();
    }
 
    bool isBusy();
 
    void addRankToRankDelay(Tick cmd_at) override;
 
    void respondEvent(uint8_t rank);
 
    void checkRefreshState(uint8_t rank);
 
    DRAMInterface(const DRAMInterfaceParams* _p);
};
 
class NVMInterface : public MemInterface
{
  private:
    class Rank : public EventManager
    {
      public:
 
        uint8_t rank;
 
        std::vector<Bank> banks;
 
        Rank(const NVMInterfaceParams* _p, int _rank,
             NVMInterface& _nvm);
    };
 
    const uint32_t maxPendingWrites;
    const uint32_t maxPendingReads;
    const bool twoCycleRdWr;
 
    const Tick tREAD;
    const Tick tWRITE;
    const Tick tSEND;
 
    struct NVMStats : public Stats::Group
    {
        NVMStats(NVMInterface &nvm);
 
        void regStats() override;
 
        NVMInterface &nvm;
 
        Stats::Scalar readBursts;
        Stats::Scalar writeBursts;
 
        Stats::Vector perBankRdBursts;
        Stats::Vector perBankWrBursts;
 
        // Latencies summed over all requests
        Stats::Scalar totQLat;
        Stats::Scalar totBusLat;
        Stats::Scalar totMemAccLat;
 
        // Average latencies per request
        Stats::Formula avgQLat;
        Stats::Formula avgBusLat;
        Stats::Formula avgMemAccLat;
 
        Stats::Scalar bytesRead;
        Stats::Scalar bytesWritten;
 
        // Average bandwidth
        Stats::Formula avgRdBW;
        Stats::Formula avgWrBW;
        Stats::Formula peakBW;
        Stats::Formula busUtil;
        Stats::Formula busUtilRead;
        Stats::Formula busUtilWrite;
 
        Stats::Histogram pendingReads;
        Stats::Histogram pendingWrites;
        Stats::Histogram bytesPerBank;
    };
    NVMStats stats;
 
    void processWriteRespondEvent();
    EventFunctionWrapper writeRespondEvent;
 
    void processReadReadyEvent();
    EventFunctionWrapper readReadyEvent;
 
    std::vector<Rank*> ranks;
 
    std::list<Tick> writeRespQueue;
 
    std::deque<Tick> readReadyQueue;
 
    bool writeRespQueueEmpty() const { return writeRespQueue.empty(); }
 
    Tick nextReadAt;
 
    // keep track of reads that have issued for which data is either
    // not yet ready or has not yet been transferred to the ctrl
    uint16_t numPendingReads;
    uint16_t numReadDataReady;
 
  public:
    // keep track of the number of reads that have yet to be issued
    uint16_t numReadsToIssue;
 
    // number of writes in the writeQueue for the NVM interface
    uint32_t numWritesQueued;
 
    void init() override;
 
    void setupRank(const uint8_t rank, const bool is_read) override;
 
    bool allRanksDrained() const override { return writeRespQueueEmpty(); }
 
    /*
     * @return time to offset next command
     */
    Tick commandOffset() const override { return tBURST; }
 
    bool burstReady(MemPacket* pkt) const override;
 
    bool isBusy(bool read_queue_empty, bool all_writes_nvm);
    std::pair<MemPacketQueue::iterator, Tick>
    chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
 
    void addRankToRankDelay(Tick cmd_at) override;
 
 
    void chooseRead(MemPacketQueue& queue);
 
    /*
     * Function to calulate unloaded access latency
     */
    Tick accessLatency() const override { return (tREAD + tSEND); }
 
    bool
    writeRespQueueFull() const
    {
        return writeRespQueue.size() == maxPendingWrites;
    }
 
    bool
    readsWaitingToIssue() const
    {
        return ((numReadsToIssue != 0) &&
                (numPendingReads < maxPendingReads));
    }
 
    std::pair<Tick, Tick>
    doBurstAccess(MemPacket* pkt, Tick next_burst_at);
 
    NVMInterface(const NVMInterfaceParams* _p);
};
 
#endif //__MEM_INTERFACE_HH__