Go to the documentation of this file.
35 #ifndef __DEV_MALTA_HH__
36 #define __DEV_MALTA_HH__
39 #include "params/Malta.hh"
110 panic(
"Need implementation\n");
117 panic(
"Need implementation\n");
124 panic(
"Need implementation\n");
132 #endif // __DEV_MALTA_HH__
MaltaCChip * cchip
Pointer to the Malta CChip.
void serialize(CheckpointOut &cp) const override
Serialize an object.
Addr calcPciConfigAddr(int bus, int dev, int func)
Device model for an Intel PIIX4 IDE controller.
int intr_sum_type[Malta::Max_CPUs]
virtual Addr pciToDma(Addr pciAddr) const
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void clearPciInt(int line) override
Clear a posted PCI->CPU interrupt.
int ipi_pending[Malta::Max_CPUs]
static const int Max_CPUs
Max number of CPUs in a Malta.
Addr calcPciMemAddr(Addr addr)
System * system
Pointer to the system.
void postConsoleInt() override
Cause the cpu to post a serial interrupt to the CPU.
Malta CChip CSR Emulation.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Top level class for Malta Chipset emulation.
void postPciInt(int line) override
Cause the chipset to post a cpi interrupt to the CPU.
Malta I/O device is a catch all for all the south bridge stuff we care to implement.
std::ostream CheckpointOut
MaltaIO * io
Pointer to the MaltaIO device which has the RTC.
void clearConsoleInt() override
Clear a posted CPU interrupt (id=55)
Addr calcPciIOAddr(Addr addr)
#define panic(...)
This implements a cprintf based panic() function.
MaltaParams Params
Constructor for the Malta Class.
Generated on Wed Sep 30 2020 14:02:11 for gem5 by doxygen 1.8.17