gem5  v20.1.0.0
malta.hh
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28 
35 #ifndef __DEV_MALTA_HH__
36 #define __DEV_MALTA_HH__
37 
38 #include "dev/platform.hh"
39 #include "params/Malta.hh"
40 
41 class IdeController;
42 class MaltaCChip;
43 class MaltaIO;
44 class System;
45 
53 class Malta : public Platform
54 {
55  public:
57  static const int Max_CPUs = 64;
58 
61 
64 
70 
73 
74  public:
81  typedef MaltaParams Params;
82  Malta(const Params *p);
83 
87  void postConsoleInt() override;
88 
92  void clearConsoleInt() override;
93 
97  void postPciInt(int line) override;
98 
102  void clearPciInt(int line) override;
103 
104 
105  virtual Addr pciToDma(Addr pciAddr) const;
106 
107  Addr
108  calcPciConfigAddr(int bus, int dev, int func)
109  {
110  panic("Need implementation\n");
111  M5_DUMMY_RETURN
112  }
113 
114  Addr
116  {
117  panic("Need implementation\n");
118  M5_DUMMY_RETURN
119  }
120 
121  Addr
123  {
124  panic("Need implementation\n");
125  M5_DUMMY_RETURN
126  }
127 
128  void serialize(CheckpointOut &cp) const override;
129  void unserialize(CheckpointIn &cp) override;
130 };
131 
132 #endif // __DEV_MALTA_HH__
Malta::cchip
MaltaCChip * cchip
Pointer to the Malta CChip.
Definition: malta.hh:69
Malta::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: malta.cc:88
Malta::calcPciConfigAddr
Addr calcPciConfigAddr(int bus, int dev, int func)
Definition: malta.hh:108
IdeController
Device model for an Intel PIIX4 IDE controller.
Definition: ide_ctrl.hh:48
Malta::intr_sum_type
int intr_sum_type[Malta::Max_CPUs]
Definition: malta.hh:71
Malta::pciToDma
virtual Addr pciToDma(Addr pciAddr) const
Definition: malta.cc:82
Malta::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: malta.cc:94
Malta::clearPciInt
void clearPciInt(int line) override
Clear a posted PCI->CPU interrupt.
Definition: malta.cc:76
Malta::ipi_pending
int ipi_pending[Malta::Max_CPUs]
Definition: malta.hh:72
Malta::Max_CPUs
static const int Max_CPUs
Max number of CPUs in a Malta.
Definition: malta.hh:57
cp
Definition: cprintf.cc:40
Malta::calcPciMemAddr
Addr calcPciMemAddr(Addr addr)
Definition: malta.hh:122
System
Definition: system.hh:73
Malta::system
System * system
Pointer to the system.
Definition: malta.hh:60
Platform
Definition: platform.hh:49
Malta::postConsoleInt
void postConsoleInt() override
Cause the cpu to post a serial interrupt to the CPU.
Definition: malta.cc:56
platform.hh
MaltaCChip
Malta CChip CSR Emulation.
Definition: malta_cchip.hh:44
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
Malta
Top level class for Malta Chipset emulation.
Definition: malta.hh:53
addr
ip6_addr_t addr
Definition: inet.hh:423
Malta::postPciInt
void postPciInt(int line) override
Cause the chipset to post a cpi interrupt to the CPU.
Definition: malta.cc:70
MaltaIO
Malta I/O device is a catch all for all the south bridge stuff we care to implement.
Definition: malta_io.hh:48
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
Malta::io
MaltaIO * io
Pointer to the MaltaIO device which has the RTC.
Definition: malta.hh:63
Malta::clearConsoleInt
void clearConsoleInt() override
Clear a posted CPU interrupt (id=55)
Definition: malta.cc:63
CheckpointIn
Definition: serialize.hh:67
Malta::Malta
Malta(const Params *p)
Definition: malta.cc:48
Malta::calcPciIOAddr
Addr calcPciIOAddr(Addr addr)
Definition: malta.hh:115
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
Malta::Params
MaltaParams Params
Constructor for the Malta Class.
Definition: malta.hh:81

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