gem5  v20.1.0.0
malta.cc
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28 
33 #include "dev/mips/malta.hh"
34 
35 #include <deque>
36 #include <string>
37 #include <vector>
38 
39 #include "cpu/intr_control.hh"
40 #include "debug/Malta.hh"
41 #include "dev/mips/malta_cchip.hh"
42 #include "dev/mips/malta_io.hh"
43 #include "params/Malta.hh"
44 #include "sim/system.hh"
45 
46 using namespace std;
47 
49  : Platform(p), system(p->system)
50 {
51  for (int i = 0; i < Malta::Max_CPUs; i++)
52  intr_sum_type[i] = 0;
53 }
54 
55 void
57 {
58  //see {Linux-src}/arch/mips/mips-boards/sim/sim_setup.c
59  io->postIntr(0x10/*HW4*/);
60 }
61 
62 void
64 {
65  //FIXME: implement clearConsoleInt()
66  io->clearIntr(0x10/*HW4*/);
67 }
68 
69 void
71 {
72  panic("Malta::postPciInt() has not been implemented.");
73 }
74 
75 void
77 {
78  panic("Malta::clearPciInt() has not been implemented.");
79 }
80 
81 Addr
82 Malta::pciToDma(Addr pciAddr) const
83 {
84  panic("Malta::pciToDma() has not been implemented.");
85 }
86 
87 void
89 {
91 }
92 
93 void
95 {
97 }
98 
99 Malta *
100 MaltaParams::create()
101 {
102  return new Malta(this);
103 }
Malta::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: malta.cc:88
MaltaIO::clearIntr
void clearIntr(uint8_t interrupt)
Clear an Interrupt to the CPU.
Definition: malta_io.cc:102
malta.hh
system.hh
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
malta_io.hh
Malta::intr_sum_type
int intr_sum_type[Malta::Max_CPUs]
Definition: malta.hh:71
Malta::pciToDma
virtual Addr pciToDma(Addr pciAddr) const
Definition: malta.cc:82
Malta::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: malta.cc:94
malta_cchip.hh
Malta::clearPciInt
void clearPciInt(int line) override
Clear a posted PCI->CPU interrupt.
Definition: malta.cc:76
Malta::Max_CPUs
static const int Max_CPUs
Max number of CPUs in a Malta.
Definition: malta.hh:57
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
cp
Definition: cprintf.cc:40
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:832
Platform
Definition: platform.hh:49
Malta::postConsoleInt
void postConsoleInt() override
Cause the cpu to post a serial interrupt to the CPU.
Definition: malta.cc:56
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
MaltaIO::postIntr
void postIntr(uint8_t interrupt)
Post an Interrupt to the CPU.
Definition: malta_io.cc:95
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:840
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
Malta
Top level class for Malta Chipset emulation.
Definition: malta.hh:53
intr_control.hh
Malta::postPciInt
void postPciInt(int line) override
Cause the chipset to post a cpi interrupt to the CPU.
Definition: malta.cc:70
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
Malta::io
MaltaIO * io
Pointer to the MaltaIO device which has the RTC.
Definition: malta.hh:63
Malta::clearConsoleInt
void clearConsoleInt() override
Clear a posted CPU interrupt (id=55)
Definition: malta.cc:63
CheckpointIn
Definition: serialize.hh:67
Malta::Malta
Malta(const Params *p)
Definition: malta.cc:48
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
Malta::Params
MaltaParams Params
Constructor for the Malta Class.
Definition: malta.hh:81

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