gem5  v20.1.0.0
decode.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2013-2014 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
45 #ifndef __CPU_MINOR_DECODE_HH__
46 #define __CPU_MINOR_DECODE_HH__
47 
48 #include "cpu/minor/buffers.hh"
49 #include "cpu/minor/cpu.hh"
50 #include "cpu/minor/dyn_inst.hh"
51 #include "cpu/minor/pipe_data.hh"
52 
53 namespace Minor
54 {
55 
56 /* Decode takes instructions from Fetch2 and decomposes them into micro-ops
57  * to feed to Execute. It generates a new sequence number for each
58  * instruction: execSeqNum.
59  */
60 class Decode : public Named
61 {
62  protected:
65 
70 
73 
75  unsigned int outputWidth;
76 
80 
81  public:
82  /* Public for Pipeline to be able to pass it to Fetch2 */
84 
85  protected:
89 
92  inputIndex(0),
93  inMacroop(false),
94  execSeqNum(InstId::firstExecSeqNum),
95  blocked(false)
96  { }
97 
99  inputIndex(other.inputIndex),
100  inMacroop(other.inMacroop),
101  execSeqNum(other.execSeqNum),
102  blocked(other.blocked)
103  { }
104 
105 
108  unsigned int inputIndex;
109 
115  bool inMacroop;
117 
120 
122  bool blocked;
123  };
124 
127 
128  protected:
130  const ForwardInstData *getInput(ThreadID tid);
131 
133  void popInput(ThreadID tid);
134 
138  public:
139  Decode(const std::string &name,
140  MinorCPU &cpu_,
141  MinorCPUParams &params,
144  std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
145 
146  public:
148  void evaluate();
149 
150  void minorTrace() const;
151 
156  bool isDrained();
157 };
158 
159 }
160 
161 #endif /* __CPU_MINOR_DECODE_HH__ */
Minor::Decode::DecodeThreadInfo::inMacroop
bool inMacroop
True when we're in the process of decomposing a micro-op and microopPC will be valid.
Definition: decode.hh:115
pipe_data.hh
dyn_inst.hh
Minor::ForwardInstData
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Definition: pipe_data.hh:253
Minor::Decode::inp
Latch< ForwardInstData >::Output inp
Input port carrying macro instructions from Fetch2.
Definition: decode.hh:67
Minor::Decode::DecodeThreadInfo::inputIndex
unsigned int inputIndex
Index into the inputBuffer's head marking the start of unhandled instructions.
Definition: decode.hh:108
ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
Minor::Latch::Input
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:245
Minor::Decode::DecodeThreadInfo::execSeqNum
InstSeqNum execSeqNum
Source of execSeqNums to number instructions.
Definition: decode.hh:119
Minor::Decode::evaluate
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: decode.cc:122
cpu.hh
std::vector
STL vector class.
Definition: stl.hh:37
Minor::Decode::outputWidth
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
Definition: decode.hh:75
Minor
Definition: activity.cc:44
Minor::Decode::DecodeThreadInfo
Data members after this line are cycle-to-cycle state.
Definition: decode.hh:88
Minor::Decode::DecodeThreadInfo::blocked
bool blocked
Blocked indication for report.
Definition: decode.hh:122
Minor::Decode::out
Latch< ForwardInstData >::Input out
Output port carrying micro-op decomposed instructions to Execute.
Definition: decode.hh:69
Minor::Decode
Definition: decode.hh:60
Minor::Decode::popInput
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Definition: decode.cc:93
Minor::Decode::minorTrace
void minorTrace() const
Definition: decode.cc:336
Minor::Decode::Decode
Decode(const std::string &name, MinorCPU &cpu_, MinorCPUParams &params, Latch< ForwardInstData >::Output inp_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
Definition: decode.cc:46
MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:77
Minor::Latch::Output
Definition: buffers.hh:256
Minor::Decode::DecodeThreadInfo::DecodeThreadInfo
DecodeThreadInfo()
Default Constructor.
Definition: decode.hh:91
Minor::Decode::processMoreThanOneInput
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
Definition: decode.hh:79
Minor::Decode::isDrained
bool isDrained()
Is this stage drained? For Decoed, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
Definition: decode.cc:325
Minor::Decode::DecodeThreadInfo::microopPC
TheISA::PCState microopPC
Definition: decode.hh:116
Minor::InputBuffer
Like a Queue but with a restricted interface and a setTail function which, when the queue is empty,...
Definition: buffers.hh:565
Minor::Decode::nextStageReserve
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
Definition: decode.hh:72
Minor::Decode::cpu
MinorCPU & cpu
Pointer back to the containing CPU.
Definition: decode.hh:64
InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:37
Minor::Decode::threadPriority
ThreadID threadPriority
Definition: decode.hh:126
Named
Definition: trace.hh:147
Minor::Decode::getInput
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on, or 0 if there is no data.
Definition: decode.cc:80
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
Minor::Decode::getScheduledThread
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to decode from.
Definition: decode.cc:295
Minor::Decode::inputBuffer
std::vector< InputBuffer< ForwardInstData > > inputBuffer
Definition: decode.hh:83
buffers.hh
Minor::Decode::DecodeThreadInfo::DecodeThreadInfo
DecodeThreadInfo(const DecodeThreadInfo &other)
Definition: decode.hh:98
Named::name
const std::string & name() const
Definition: trace.hh:156
Minor::InstId
Id for lines and instructions.
Definition: dyn_inst.hh:68
Minor::Decode::decodeInfo
std::vector< DecodeThreadInfo > decodeInfo
Definition: decode.hh:125

Generated on Wed Sep 30 2020 14:02:08 for gem5 by doxygen 1.8.17