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44 #ifndef __CPU_MINOR_CPU_HH__
45 #define __CPU_MINOR_CPU_HH__
51 #include "enums/ThreadPolicy.hh"
52 #include "params/MinorCPU.hh"
127 void init()
override;
178 prio_list.push_back(
i);
180 std::random_shuffle(prio_list.begin(), prio_list.end());
void wakeup(ThreadID tid) override
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
MinorCPU & cpu
The enclosing cpu.
Port & getInstPort() override
Return a reference to the instruction port.
void init() override
Starting, waking and initialisation.
int16_t ThreadID
Thread index/ID type.
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Minor::MinorStats stats
Processor-specific statistics.
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
MinorCPU(MinorCPUParams *params)
std::vector< Minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
DrainState
Object drain/handover states.
ActivityRecorder with a Ticked interface.
int64_t Counter
Statistics counter type.
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
MinorCPU is an in-order CPU model with four fixed pipeline stages:
void switchOut() override
Switching interface from BaseCPU.
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
void memWriteback() override
Ports are used to interface objects to each other.
The constructed pipeline.
void drainResume() override
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState.
const Params * params() const
Counter totalOps() const override
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
Currently unused stats class.
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
std::ostream CheckpointOut
Port & getDataPort() override
Return a reference to the data port.
std::vector< ThreadID > randomPriority()
void unserialize(CheckpointIn &cp) override
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
DrainState drain() override
Drain interface.
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