gem5  v20.1.0.0
locked_mem.hh
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40 
41 #ifndef __ARCH_MIPS_LOCKED_MEM_HH__
42 #define __ARCH_MIPS_LOCKED_MEM_HH__
43 
50 #include "arch/registers.hh"
51 #include "base/logging.hh"
52 #include "base/trace.hh"
53 #include "debug/LLSC.hh"
54 #include "mem/packet.hh"
55 #include "mem/request.hh"
56 
57 namespace MipsISA
58 {
59 template <class XC>
60 inline void
61 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
62 {
63  if (!xc->readMiscReg(MISCREG_LLFLAG))
64  return;
65 
66  Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
67  Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
68 
69  if (locked_addr == snoop_addr)
70  xc->setMiscReg(MISCREG_LLFLAG, false);
71 }
72 
73 
74 template <class XC>
75 inline void
76 handleLockedRead(XC *xc, const RequestPtr &req)
77 {
78  xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
79  xc->setMiscReg(MISCREG_LLFLAG, true);
80  DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link"
81  " Address set to %x.\n",
82  req->contextId(), req->getPaddr() & ~0xf);
83 }
84 
85 template <class XC>
86 inline void
88 {
89 }
90 
91 template <class XC>
92 inline bool
93 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
94 {
95  if (req->isUncacheable()) {
96  // Funky Turbolaser mailbox access...don't update
97  // result register (see stq_c in decoder.isa)
98  req->setExtraData(2);
99  } else {
100  // standard store conditional
101  bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
102  Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
103 
104  if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
105  // Lock flag not set or addr mismatch in CPU;
106  // don't even bother sending to memory system
107  req->setExtraData(0);
108  xc->setMiscReg(MISCREG_LLFLAG, false);
109 
110  // the rest of this code is not architectural;
111  // it's just a debugging aid to help detect
112  // livelock by warning on long sequences of failed
113  // store conditionals
114  int stCondFailures = xc->readStCondFailures();
115  stCondFailures++;
116  xc->setStCondFailures(stCondFailures);
117  if (stCondFailures % 100000 == 0) {
118  warn("%i: context %d: %d consecutive "
119  "store conditional failures\n",
120  curTick(), xc->contextId(), stCondFailures);
121  }
122 
123  if (!lock_flag){
124  DPRINTF(LLSC, "[cid:%i]: Lock Flag Set, "
125  "Store Conditional Failed.\n",
126  req->contextId());
127  } else if ((req->getPaddr() & ~0xf) != lock_addr) {
128  DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, "
129  "Store Conditional Failed.\n",
130  req->contextId());
131  }
132  // store conditional failed already, so don't issue it to mem
133  return false;
134  }
135  }
136 
137  return true;
138 }
139 
140 template <class XC>
141 inline void
143 {
144  xc->getCpuPtr()->wakeup(xc->threadId());
145 }
146 
147 } // namespace MipsISA
148 
149 #endif
warn
#define warn(...)
Definition: logging.hh:239
MipsISA::handleLockedWrite
bool handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
Definition: locked_mem.hh:93
MipsISA::globalClearExclusive
void globalClearExclusive(XC *xc)
Definition: locked_mem.hh:142
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:754
MipsISA::handleLockedSnoop
void handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
Definition: locked_mem.hh:61
MipsISA::handleLockedSnoopHit
void handleLockedSnoopHit(XC *xc)
Definition: locked_mem.hh:87
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:82
request.hh
MipsISA
Definition: decoder.cc:31
packet.hh
MipsISA::MISCREG_LLFLAG
@ MISCREG_LLFLAG
Definition: registers.hh:274
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
MipsISA::MISCREG_LLADDR
@ MISCREG_LLADDR
Definition: registers.hh:201
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
logging.hh
trace.hh
MipsISA::handleLockedRead
void handleLockedRead(XC *xc, const RequestPtr &req)
Definition: locked_mem.hh:76
curTick
Tick curTick()
The current simulated tick.
Definition: core.hh:45

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