gem5  v20.1.0.0
registers.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2013 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __ARCH_NULL_REGISTERS_HH__
39 #define __ARCH_NULL_REGISTERS_HH__
40 
42 #include "arch/generic/vec_reg.hh"
43 #include "arch/types.hh"
44 #include "base/types.hh"
45 
46 namespace NullISA {
47 
48 const RegIndex ZeroReg = 0;
49 
50 // Not applicable to null
57 
58 // Not applicable to null
64 
65 }
66 
67 #endif // __ARCH_NULL_REGISTERS_HH__
DummyVecRegSizeBytes
constexpr size_t DummyVecRegSizeBytes
Definition: vec_reg.hh:669
DummyVecPredRegSizeBits
constexpr size_t DummyVecPredRegSizeBits
Definition: vec_pred_reg.hh:398
VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:47
NullISA::VecPredRegHasPackedRepr
constexpr bool VecPredRegHasPackedRepr
Definition: registers.hh:63
DummyVecPredRegHasPackedRepr
constexpr bool DummyVecPredRegHasPackedRepr
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:391
NullISA::VecPredRegSizeBits
constexpr size_t VecPredRegSizeBits
Definition: registers.hh:62
DummyVecPredReg
VecPredRegT< DummyVecElem, DummyNumVecElemPerVecReg, DummyVecPredRegHasPackedRepr, false > DummyVecPredReg
Definition: vec_pred_reg.hh:393
NullISA
Definition: isa_traits.hh:43
NullISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: registers.hh:55
DummyVecRegContainer
DummyVecReg::Container DummyVecRegContainer
Definition: vec_reg.hh:668
VecPredRegT
Predicate register view.
Definition: vec_pred_reg.hh:66
DummyConstVecReg
VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, true > DummyConstVecReg
Definition: vec_reg.hh:667
DummyVecElem
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:664
vec_pred_reg.hh
NullISA::VecElem
::DummyVecElem VecElem
Definition: registers.hh:51
DummyVecReg
VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, false > DummyVecReg
Definition: vec_reg.hh:666
DummyVecPredRegContainer
DummyVecPredReg::Container DummyVecPredRegContainer
Definition: vec_pred_reg.hh:397
NullISA::VecRegSizeBytes
constexpr size_t VecRegSizeBytes
Definition: registers.hh:56
vec_reg.hh
DummyConstVecPredReg
VecPredRegT< DummyVecElem, DummyNumVecElemPerVecReg, DummyVecPredRegHasPackedRepr, true > DummyConstVecPredReg
Definition: vec_pred_reg.hh:396
types.hh
RegIndex
uint16_t RegIndex
Definition: types.hh:52
DummyNumVecElemPerVecReg
constexpr unsigned DummyNumVecElemPerVecReg
Definition: vec_reg.hh:665
NullISA::ZeroReg
const RegIndex ZeroReg
Definition: registers.hh:48
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:156
VecRegT
Vector Register Abstraction This generic class is a view in a particularization of MVC,...
Definition: vec_reg.hh:170

Generated on Wed Sep 30 2020 14:02:01 for gem5 by doxygen 1.8.17