gem5  v20.1.0.0
vec_pred_reg.hh
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35 
36 #ifndef __ARCH_GENERIC_VEC_PRED_REG_HH__
37 #define __ARCH_GENERIC_VEC_PRED_REG_HH__
38 
39 #include <array>
40 #include <cassert>
41 #include <vector>
42 
43 #include "arch/generic/vec_reg.hh"
44 #include "base/cprintf.hh"
45 
46 template <size_t NumBits, bool Packed>
48 
65 template <typename VecElem, size_t NumElems, bool Packed, bool Const>
67 {
68  protected:
70  static constexpr size_t NUM_BITS = Packed ? NumElems :
71  sizeof(VecElem) * NumElems;
72 
73  public:
75  using Container = typename std::conditional<
76  Const,
79 
80  protected:
81  // Alias for this type
85 
86  public:
88 
90  template<bool Condition = !Const>
92  reset() { container.reset(); }
93 
95  template<bool Condition = !Const>
97  set() { container.set(); }
98 
99  template<bool Condition = !Const>
101  operator=(const MyClass& that)
102  {
103  container = that.container;
104  return *this;
105  }
106 
107  const bool&
108  operator[](size_t idx) const
109  {
110  return container[idx * (Packed ? 1 : sizeof(VecElem))];
111  }
112 
113  template<bool Condition = !Const>
115  operator[](size_t idx)
116  {
117  return container[idx * (Packed ? 1 : sizeof(VecElem))];
118  }
119 
122  uint8_t
123  get_raw(size_t idx) const
124  {
125  return container.get_bits(idx * (Packed ? 1 : sizeof(VecElem)),
126  (Packed ? 1 : sizeof(VecElem)));
127  }
128 
130  template<bool Condition = !Const>
132  set_raw(size_t idx, uint8_t val)
133  {
134  container.set_bits(idx * (Packed ? 1 : sizeof(VecElem)),
135  (Packed ? 1 : sizeof(VecElem)), val);
136  }
137 
139  template<typename VE2, size_t NE2, bool P2, bool C2>
140  bool
142  {
143  return container == that.container;
144  }
145 
147  template<typename VE2, size_t NE2, bool P2, bool C2>
148  bool
150  {
151  return !operator==(that);
152  }
153 
154  friend std::ostream&
155  operator<<(std::ostream& os, const MyClass& p)
156  {
157  // 0-sized is not allowed
158  os << '[' << p.container[0];
159  for (int i = 0; i < p.NUM_BITS; ++i) {
160  os << " " << (p.container[i] ? 1 : 0);
161  }
162  os << ']';
163  return os;
164  }
165 
167  const std::string print() const { return csprintf("%s", *this); }
168 
173  template <bool MC>
174  bool
176  size_t actual_num_elems) const
177  {
178  assert(actual_num_elems <= NumElems);
179  for (int i = 0; i < actual_num_elems; ++i) {
180  if (mask[i]) {
181  return (*this)[i];
182  }
183  }
184  return false;
185  }
186 
191  template <bool MC>
192  bool
194  size_t actual_num_elems) const
195  {
196  assert(actual_num_elems <= NumElems);
197  for (int i = 0; i < actual_num_elems; ++i) {
198  if (mask[i] && operator[](i)) {
199  return false;
200  }
201  }
202  return true;
203  }
204 
209  template <bool MC>
210  bool
212  size_t actual_num_elems) const
213  {
214  assert(actual_num_elems <= NumElems);
215  for (int i = actual_num_elems - 1; i >= 0; --i) {
216  if (mask[i]) {
217  return operator[](i);
218  }
219  }
220  return false;
221  }
222 };
223 
230 template <size_t NumBits, bool Packed>
232 {
233  static_assert(NumBits > 0,
234  "Size of a predicate register must be > 0");
235 
236  public:
237  static constexpr size_t NUM_BITS = NumBits;
238  using Container = std::array<bool, NumBits>;
239 
240  private:
242  // Alias for this type
244 
245  public:
247  VecPredRegContainer(const VecPredRegContainer &) = default;
248 
249  MyClass&
250  operator=(const MyClass& that)
251  {
252  if (&that == this)
253  return *this;
254  container = that.container;
255  return *this;
256  }
257 
259  MyClass&
261  {
262  assert(that.size() == NUM_BITS);
263  std::copy(that.begin(), that.end(), container.begin());
264  return *this;
265  }
266 
268  void
270  {
271  container.fill(false);
272  }
273 
275  void
276  set()
277  {
278  container.fill(true);
279  }
280 
282  template<size_t N2, bool P2>
283  inline bool
285  {
286  return NumBits == N2 && Packed == P2 && container == that.container;
287  }
288 
290  template<size_t N2, bool P2>
291  bool
293  {
294  return !operator==(that);
295  }
296 
298  bool& operator[](size_t idx) { return container[idx]; }
299 
302  const bool& operator[](size_t idx) const { return container[idx]; }
303 
306  uint8_t
307  get_bits(size_t idx, uint8_t nbits) const
308  {
309  assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
310  uint8_t v = 0;
311  idx = idx + nbits - 1;
312  for (int i = 0; i < nbits; ++i, --idx) {
313  v <<= 1;
314  v |= container[idx];
315  }
316  return v;
317  }
318 
321  void
322  set_bits(size_t idx, uint8_t nbits, uint8_t bval)
323  {
324  assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
325  for (int i = 0; i < nbits; ++i, ++idx) {
326  container[idx] = bval & 1;
327  bval >>= 1;
328  }
329  }
330 
332  const std::string print() const { return csprintf("%s", *this); }
333 
334  friend std::ostream&
335  operator<<(std::ostream& os, const MyClass& v)
336  {
337  for (auto b: v.container) {
338  os << csprintf("%d", b);
339  }
340  return os;
341  }
342 
350  template <typename VecElem,
351  size_t NumElems = (Packed ? NumBits : NumBits / sizeof(VecElem))>
353  {
354  static_assert((Packed && NumElems <= NumBits) ||
355  (!Packed &&
356  NumBits % sizeof(VecElem) == 0 &&
357  sizeof(VecElem) * NumElems <= NumBits),
358  "Container size incompatible with view size");
360  }
361 
362  template <typename VecElem,
363  size_t NumElems = (Packed ? NumBits : NumBits / sizeof(VecElem))>
365  {
366  static_assert((Packed && NumElems <= NumBits) ||
367  (!Packed &&
368  NumBits % sizeof(VecElem) == 0 &&
369  sizeof(VecElem) * NumElems <= NumBits),
370  "Container size incompatible with view size");
372  }
374 };
375 
377 template <size_t NumBits, bool Packed>
378 inline bool
380 {
381  int i = 0;
382  for (const auto& c: value) {
383  p[i] = (c == '1');
384  }
385  return true;
386 }
387 
391 constexpr bool DummyVecPredRegHasPackedRepr = false;
398 constexpr size_t DummyVecPredRegSizeBits = 8;
400 
401 #endif // __ARCH_GENERIC_VEC_PRED_REG_HH__
VecPredRegT::operator[]
const bool & operator[](size_t idx) const
Definition: vec_pred_reg.hh:108
X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
VecPredRegT::NUM_BITS
static constexpr size_t NUM_BITS
Size of the register in bits.
Definition: vec_pred_reg.hh:70
VecPredRegContainer::set_bits
void set_bits(size_t idx, uint8_t nbits, uint8_t bval)
Set a subset of bits starting from a specific element in the container.
Definition: vec_pred_reg.hh:322
DummyVecPredRegSizeBits
constexpr size_t DummyVecPredRegSizeBits
Definition: vec_pred_reg.hh:398
VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:47
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
VecPredRegContainer::operator[]
const bool & operator[](size_t idx) const
Returns a const reference to a specific element of the internal container.
Definition: vec_pred_reg.hh:302
DummyVecPredRegHasPackedRepr
constexpr bool DummyVecPredRegHasPackedRepr
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:391
VecPredRegT::noneActive
bool noneActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if there are no active elements in the register.
Definition: vec_pred_reg.hh:193
VecPredRegContainer::operator[]
bool & operator[](size_t idx)
Returns a reference to a specific element of the internal container.
Definition: vec_pred_reg.hh:298
type
uint8_t type
Definition: inet.hh:421
VecPredRegContainer::print
const std::string print() const
Returns a string representation of the register content.
Definition: vec_pred_reg.hh:332
VecPredRegT::lastActive
bool lastActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if the last active element of the register is true.
Definition: vec_pred_reg.hh:211
std::vector< uint8_t >
VecPredRegContainer::NUM_BITS
static constexpr size_t NUM_BITS
Definition: vec_pred_reg.hh:237
VecPredRegT::operator<<
friend std::ostream & operator<<(std::ostream &os, const MyClass &p)
Definition: vec_pred_reg.hh:155
VecPredRegContainer::container
Container container
Definition: vec_pred_reg.hh:241
VecPredRegContainer::operator==
bool operator==(const VecPredRegContainer< N2, P2 > &that) const
Equality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:284
VecPredRegContainer< TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr >::Container
std::array< bool, NumBits > Container
Definition: vec_pred_reg.hh:238
VecPredRegT::container
Container & container
Container corresponding to this view.
Definition: vec_pred_reg.hh:84
to_number
bool to_number(const std::string &value, VecPredRegContainer< NumBits, Packed > &p)
Helper functions used for serialization/de-serialization.
Definition: vec_pred_reg.hh:379
VecPredRegT::print
const std::string print() const
Returns a string representation of the register content.
Definition: vec_pred_reg.hh:167
ArmISA::VecElem
uint32_t VecElem
Definition: registers.hh:68
VecPredRegT::operator==
bool operator==(const VecPredRegT< VE2, NE2, P2, C2 > &that) const
Equality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:141
VecPredRegT::VecPredRegT
VecPredRegT(Container &c)
Definition: vec_pred_reg.hh:87
VecPredRegT::operator!=
bool operator!=(const VecPredRegT< VE2, NE2, P2, C2 > &that) const
Inequality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:149
VecPredRegContainer::operator=
MyClass & operator=(const MyClass &that)
Definition: vec_pred_reg.hh:250
VecPredRegT::set
std::enable_if< Condition, void >::type set()
Reset the register to an all-true value.
Definition: vec_pred_reg.hh:97
VecPredRegT
Predicate register view.
Definition: vec_pred_reg.hh:66
VecPredRegT::operator=
std::enable_if< Condition, MyClass & >::type operator=(const MyClass &that)
Definition: vec_pred_reg.hh:101
VecPredRegT::Container
typename std::conditional< Const, const VecPredRegContainer< NUM_BITS, Packed >, VecPredRegContainer< NUM_BITS, Packed > >::type Container
Container type alias.
Definition: vec_pred_reg.hh:78
VecPredRegContainer::as
VecPredRegT< VecElem, NumElems, Packed, true > as() const
Create a view of this container.
Definition: vec_pred_reg.hh:352
VecPredRegContainer::reset
void reset()
Resets the predicate register to an all-false register.
Definition: vec_pred_reg.hh:269
VecPredRegT::operator[]
std::enable_if< Condition, bool & >::type operator[](size_t idx)
Definition: vec_pred_reg.hh:115
cprintf.hh
VecPredRegT::get_raw
uint8_t get_raw(size_t idx) const
Return an element of the predicate register as it appears in the raw (untyped) internal representatio...
Definition: vec_pred_reg.hh:123
VecPredRegContainer::VecPredRegContainer
VecPredRegContainer()
Definition: vec_pred_reg.hh:246
VecPredRegT::firstActive
bool firstActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if the first active element of the register is true.
Definition: vec_pred_reg.hh:175
VecPredRegContainer::as
VecPredRegT< VecElem, NumElems, Packed, false > as()
Definition: vec_pred_reg.hh:364
DummyVecElem
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:664
VecPredRegT::reset
std::enable_if< Condition, void >::type reset()
Reset the register to an all-false value.
Definition: vec_pred_reg.hh:92
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
DummyVecPredRegContainer
DummyVecPredReg::Container DummyVecPredRegContainer
Definition: vec_pred_reg.hh:397
VecPredRegContainer::set
void set()
Sets the predicate register to an all-true value.
Definition: vec_pred_reg.hh:276
vec_reg.hh
VecPredRegT::set_raw
std::enable_if< Condition, void >::type set_raw(size_t idx, uint8_t val)
Write a raw value in an element of the predicate register.
Definition: vec_pred_reg.hh:132
ArmISA::b
Bitfield< 7 > b
Definition: miscregs_types.hh:376
VecPredRegContainer::MyClass
VecPredRegContainer< NumBits, Packed > MyClass
Definition: vec_pred_reg.hh:243
DummyNumVecElemPerVecReg
constexpr unsigned DummyNumVecElemPerVecReg
Definition: vec_reg.hh:665
VecPredRegContainer::get_bits
uint8_t get_bits(size_t idx, uint8_t nbits) const
Returns a subset of bits starting from a specific element in the container.
Definition: vec_pred_reg.hh:307
ArmISA::c
Bitfield< 29 > c
Definition: miscregs_types.hh:50
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
VecPredRegContainer::operator<<
friend std::ostream & operator<<(std::ostream &os, const MyClass &v)
Definition: vec_pred_reg.hh:335
VecPredRegContainer::operator!=
bool operator!=(const VecPredRegContainer< N2, P2 > &that) const
Inequality operator, required to compare thread contexts.
Definition: vec_pred_reg.hh:292
csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:158
ArmISA::v
Bitfield< 28 > v
Definition: miscregs_types.hh:51
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
VecPredRegContainer::operator=
MyClass & operator=(const std::vector< uint8_t > &that)
Required for de-serialization.
Definition: vec_pred_reg.hh:260

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