gem5
v20.1.0.0
arch
riscv
pagetable.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2020 Barkhausen Institut
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_RISCV_PAGETABLE_H__
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#define __ARCH_RISCV_PAGETABLE_H__
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#include "
base/logging.hh
"
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#include "
base/trie.hh
"
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#include "
base/types.hh
"
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#include "
sim/serialize.hh
"
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namespace
RiscvISA
{
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BitUnion64
(SATP)
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Bitfield<63, 60>
mode
;
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Bitfield<59, 44>
asid
;
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Bitfield<43, 0>
ppn
;
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EndBitUnion
(SATP)
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enum AddrXlateMode
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{
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BARE = 0,
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SV39 = 8,
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SV48 = 9,
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};
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// Sv39 paging
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const
Addr
VADDR_BITS
= 39;
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const
Addr
LEVEL_BITS
= 9;
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const
Addr
LEVEL_MASK
= (1 <<
LEVEL_BITS
) - 1;
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BitUnion64
(PTESv39)
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Bitfield<53, 10>
ppn
;
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Bitfield<53, 28>
ppn2
;
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Bitfield<27, 19>
ppn1
;
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Bitfield<18, 10>
ppn0
;
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Bitfield<7>
d
;
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Bitfield<6>
a
;
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Bitfield<5>
g
;
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Bitfield<4>
u
;
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Bitfield<3, 1>
perm
;
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Bitfield<3>
x
;
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Bitfield<2>
w
;
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Bitfield<1>
r
;
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Bitfield<0>
v
;
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EndBitUnion
(PTESv39)
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struct
TlbEntry
;
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typedef
Trie<Addr, TlbEntry>
TlbEntryTrie
;
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struct
TlbEntry
:
public
Serializable
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{
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// The base of the physical page.
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Addr
paddr
;
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// The beginning of the virtual page this entry maps.
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Addr
vaddr
;
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// The size of the page this represents, in address bits.
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unsigned
logBytes
;
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uint16_t
asid
;
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PTESv39
pte
;
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TlbEntryTrie::Handle
trieHandle
;
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// A sequence number to keep track of LRU.
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uint64_t
lruSeq
;
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TlbEntry
()
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:
paddr
(0),
vaddr
(0),
logBytes
(0),
pte
(),
lruSeq
(0)
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{}
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// Return the page size in bytes
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Addr
size
()
const
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{
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return
(
static_cast<
Addr
>
(1) <<
logBytes
);
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}
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void
serialize
(
CheckpointOut
&
cp
)
const override
;
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void
unserialize
(
CheckpointIn
&
cp
)
override
;
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};
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};
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#endif // __ARCH_RISCV_PAGETABLE_H__
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RiscvISA::TlbEntry
Definition:
pagetable.hh:78
RiscvISA::mode
mode
Definition:
pagetable.hh:42
serialize.hh
RiscvISA::TlbEntry::size
Addr size() const
Definition:
pagetable.hh:102
Trie< Addr, TlbEntry >::Handle
Node * Handle
Definition:
trie.hh:122
RiscvISA::ppn
Bitfield< 43, 0 > ppn
Definition:
pagetable.hh:44
RiscvISA::w
Bitfield< 2 > w
Definition:
pagetable.hh:70
Serializable
Basic support for object serialization.
Definition:
serialize.hh:172
RiscvISA::ppn0
Bitfield< 18, 10 > ppn0
Definition:
pagetable.hh:63
RiscvISA::TlbEntry::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition:
pagetable.cc:51
RiscvISA::g
Bitfield< 5 > g
Definition:
pagetable.hh:66
RiscvISA::TlbEntry::logBytes
unsigned logBytes
Definition:
pagetable.hh:86
RiscvISA::asid
Bitfield< 59, 44 > asid
Definition:
pagetable.hh:43
RiscvISA::TlbEntry::lruSeq
uint64_t lruSeq
Definition:
pagetable.hh:95
RiscvISA::u
Bitfield< 4 > u
Definition:
pagetable.hh:67
Trie< Addr, TlbEntry >
RiscvISA
Definition:
fs_workload.cc:36
RiscvISA::VADDR_BITS
const Addr VADDR_BITS
Definition:
pagetable.hh:55
RiscvISA::TlbEntry::TlbEntry
TlbEntry()
Definition:
pagetable.hh:97
cp
Definition:
cprintf.cc:40
RiscvISA::TlbEntry::pte
PTESv39 pte
Definition:
pagetable.hh:90
RiscvISA::BitUnion64
BitUnion64(SATP) Bitfield< 63
RiscvISA::LEVEL_MASK
const Addr LEVEL_MASK
Definition:
pagetable.hh:57
RiscvISA::perm
Bitfield< 3, 1 > perm
Definition:
pagetable.hh:68
RiscvISA::x
Bitfield< 3 > x
Definition:
pagetable.hh:69
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:142
RiscvISA::v
Bitfield< 0 > v
Definition:
pagetable.hh:72
RiscvISA::ppn1
Bitfield< 27, 19 > ppn1
Definition:
pagetable.hh:62
RiscvISA::LEVEL_BITS
const Addr LEVEL_BITS
Definition:
pagetable.hh:56
RiscvISA::EndBitUnion
EndBitUnion(SATP) enum AddrXlateMode
Definition:
pagetable.hh:45
RiscvISA::ppn2
Bitfield< 53, 28 > ppn2
Definition:
pagetable.hh:61
types.hh
RiscvISA::r
Bitfield< 1 > r
Definition:
pagetable.hh:71
logging.hh
CheckpointOut
std::ostream CheckpointOut
Definition:
serialize.hh:63
RiscvISA::a
Bitfield< 6 > a
Definition:
pagetable.hh:65
RiscvISA::TlbEntry::trieHandle
TlbEntryTrie::Handle trieHandle
Definition:
pagetable.hh:92
CheckpointIn
Definition:
serialize.hh:67
RiscvISA::d
Bitfield< 7 > d
Definition:
pagetable.hh:64
RiscvISA::TlbEntryTrie
Trie< Addr, TlbEntry > TlbEntryTrie
Definition:
pagetable.hh:76
RiscvISA::TlbEntry::vaddr
Addr vaddr
Definition:
pagetable.hh:84
RiscvISA::TlbEntry::paddr
Addr paddr
Definition:
pagetable.hh:81
trie.hh
RiscvISA::TlbEntry::asid
uint16_t asid
Definition:
pagetable.hh:88
RiscvISA::TlbEntry::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition:
pagetable.cc:40
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