gem5  v20.1.0.0
simple_mem.hh
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40 
46 #ifndef __MEM_SIMPLE_MEMORY_HH__
47 #define __MEM_SIMPLE_MEMORY_HH__
48 
49 #include <list>
50 
51 #include "mem/abstract_mem.hh"
52 #include "mem/port.hh"
53 #include "params/SimpleMemory.hh"
54 
62 {
63 
64  private:
65 
71  {
72 
73  public:
74 
75  const Tick tick;
76  const PacketPtr pkt;
77 
78  DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
79  { }
80  };
81 
82  class MemoryPort : public ResponsePort
83  {
84  private:
86 
87  public:
88  MemoryPort(const std::string& _name, SimpleMemory& _memory);
89 
90  protected:
91  Tick recvAtomic(PacketPtr pkt) override;
93  PacketPtr pkt, MemBackdoorPtr &_backdoor) override;
94  void recvFunctional(PacketPtr pkt) override;
95  bool recvTimingReq(PacketPtr pkt) override;
96  void recvRespRetry() override;
97  AddrRangeList getAddrRanges() const override;
98  };
99 
101 
106  const Tick latency;
107 
112 
119 
125  const double bandwidth;
126 
131  bool isBusy;
132 
137  bool retryReq;
138 
143  bool retryResp;
144 
149  void release();
150 
152 
157  void dequeue();
158 
160 
166  Tick getLatency() const;
167 
172  std::unique_ptr<Packet> pendingDelete;
173 
174  public:
175 
176  SimpleMemory(const SimpleMemoryParams *p);
177 
178  DrainState drain() override;
179 
180  Port &getPort(const std::string &if_name,
181  PortID idx=InvalidPortID) override;
182  void init() override;
183 
184  protected:
187  void recvFunctional(PacketPtr pkt);
188  bool recvTimingReq(PacketPtr pkt);
189  void recvRespRetry();
190 };
191 
192 #endif //__MEM_SIMPLE_MEMORY_HH__
SimpleMemory::packetQueue
std::list< DeferredPacket > packetQueue
Internal (unbounded) storage to mimic the delay caused by the actual memory access.
Definition: simple_mem.hh:118
ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:265
MemBackdoor
Definition: backdoor.hh:38
SimpleMemory::dequeueEvent
EventFunctionWrapper dequeueEvent
Definition: simple_mem.hh:159
SimpleMemory::MemoryPort::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
Definition: simple_mem.cc:275
SimpleMemory::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: simple_mem.cc:241
SimpleMemory::port
MemoryPort port
Definition: simple_mem.hh:100
SimpleMemory::release
void release()
Release the memory after being busy and send a retry if a request was rejected in the meanwhile.
Definition: simple_mem.cc:190
SimpleMemory::getLatency
Tick getLatency() const
Detemine the latency.
Definition: simple_mem.cc:226
SimpleMemory::recvRespRetry
void recvRespRetry()
Definition: simple_mem.cc:233
SimpleMemory::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: simple_mem.cc:70
InvalidPortID
const PortID InvalidPortID
Definition: types.hh:238
abstract_mem.hh
SimpleMemory::recvFunctional
void recvFunctional(PacketPtr pkt)
Definition: simple_mem.cc:90
SimpleMemory
The simple memory is a basic single-ported memory controller with a configurable throughput and laten...
Definition: simple_mem.hh:61
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
SimpleMemory::MemoryPort::memory
SimpleMemory & memory
Definition: simple_mem.hh:85
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:237
SimpleMemory::MemoryPort::recvTimingReq
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
Definition: simple_mem.cc:294
SimpleMemory::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Definition: simple_mem.cc:108
SimpleMemory::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: simple_mem.cc:251
SimpleMemory::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: simple_mem.cc:58
SimpleMemory::retryResp
bool retryResp
Remember if we failed to send a response and are awaiting a retry.
Definition: simple_mem.hh:143
SimpleMemory::DeferredPacket::tick
const Tick tick
Definition: simple_mem.hh:75
EventFunctionWrapper
Definition: eventq.hh:1101
SimpleMemory::DeferredPacket::pkt
const PacketPtr pkt
Definition: simple_mem.hh:76
DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:71
SimpleMemory::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
Definition: simple_mem.cc:80
AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:104
SimpleMemory::MemoryPort::recvRespRetry
void recvRespRetry() override
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
Definition: simple_mem.cc:300
SimpleMemory::MemoryPort
Definition: simple_mem.hh:82
SimpleMemory::releaseEvent
EventFunctionWrapper releaseEvent
Definition: simple_mem.hh:151
SimpleMemory::dequeue
void dequeue()
Dequeue a packet from our internal packet queue and move it to the port where it will be sent as soon...
Definition: simple_mem.cc:201
SimpleMemory::DeferredPacket::DeferredPacket
DeferredPacket(PacketPtr _pkt, Tick _tick)
Definition: simple_mem.hh:78
SimpleMemory::SimpleMemory
SimpleMemory(const SimpleMemoryParams *p)
Definition: simple_mem.cc:47
SimpleMemory::retryReq
bool retryReq
Remember if we have to retry an outstanding request that arrived while we were busy.
Definition: simple_mem.hh:137
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
SimpleMemory::DeferredPacket
A deferred packet stores a packet along with its scheduled transmission time.
Definition: simple_mem.hh:70
port.hh
SimpleMemory::isBusy
bool isBusy
Track the state of the memory as either idle or busy, no need for an enum with only two states.
Definition: simple_mem.hh:131
SimpleMemory::MemoryPort::getAddrRanges
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: simple_mem.cc:267
SimpleMemory::bandwidth
const double bandwidth
Bandwidth in ticks per byte.
Definition: simple_mem.hh:125
SimpleMemory::pendingDelete
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition: simple_mem.hh:172
SimpleMemory::MemoryPort::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor) override
Default implementations.
Definition: simple_mem.cc:281
SimpleMemory::MemoryPort::recvFunctional
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
Definition: simple_mem.cc:288
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
SimpleMemory::latency_var
const Tick latency_var
Fudge factor added to the latency.
Definition: simple_mem.hh:111
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
std::list< AddrRange >
SimpleMemory::latency
const Tick latency
Latency from that a request is accepted until the response is ready to be sent.
Definition: simple_mem.hh:106
SimpleMemory::MemoryPort::MemoryPort
MemoryPort(const std::string &_name, SimpleMemory &_memory)
Definition: simple_mem.cc:261

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