gem5  v20.1.0.0
smmu_v3_caches.hh
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37 
38 #ifndef __DEV_ARM_SMMU_V3_CACHES_HH__
39 #define __DEV_ARM_SMMU_V3_CACHES_HH__
40 
41 #include <stdint.h>
42 
43 #include <array>
44 #include <cstddef>
45 #include <string>
46 #include <vector>
47 
48 #include "base/random.hh"
49 #include "base/statistics.hh"
50 #include "base/types.hh"
51 
52 #define WALK_CACHE_LEVELS 4
53 
54 enum {
58 };
59 
61 {
62  protected:
64  size_t nextToReplace;
66  uint32_t useStamp;
67 
70 
73 
76 
78 
80 
81  static int decodePolicyName(const std::string &policy_name);
82 
83  public:
84  SMMUv3BaseCache(const std::string &policy_name, uint32_t seed);
85  virtual ~SMMUv3BaseCache() {}
86 
87  virtual void regStats(const std::string &name);
88 };
89 
90 class SMMUTLB : public SMMUv3BaseCache
91 {
92  public:
93  enum AllocPolicy {
97  };
98 
99  struct Entry
100  {
101  bool valid;
103  mutable uint32_t lastUsed;
104 
105  // TAGS
106  uint32_t sid;
107  uint32_t ssid;
110 
111  // EXTRA TAGS
112  uint16_t asid;
113  uint16_t vmid;
114 
115  // OUTPUTS
117  uint8_t permissions;
118  };
119 
120  SMMUTLB(unsigned numEntries, unsigned _associativity,
121  const std::string &policy);
122  SMMUTLB(const SMMUTLB& tlb) = delete;
123  virtual ~SMMUTLB() {}
124 
125  const Entry *lookup(uint32_t sid, uint32_t ssid, Addr va,
126  bool updStats=true);
127  const Entry *lookupAnyVA(uint32_t sid, uint32_t ssid,
128  bool updStats=true);
129  void store(const Entry &incoming, AllocPolicy alloc);
130 
131  void invalidateSSID(uint32_t sid, uint32_t ssid);
132  void invalidateSID(uint32_t sid);
133  void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
134  void invalidateVAA(Addr va, uint16_t vmid);
135  void invalidateASID(uint16_t asid, uint16_t vmid);
136  void invalidateVMID(uint16_t vmid);
137  void invalidateAll();
138 
139  private:
142 
144 
145  size_t pickSetIdx(uint32_t sid, uint32_t ssid) const;
146  size_t pickSetIdx(Addr va) const;
147  size_t pickEntryIdxToReplace(const Set &set, AllocPolicy alloc);
148 };
149 
151 {
152  public:
153  struct Entry
154  {
155  bool valid;
156  mutable uint32_t lastUsed;
157 
158  // TAGS
161  uint16_t asid;
162  uint16_t vmid;
163 
164  // OUTPUTS
166  uint8_t permissions;
167  };
168 
169  ARMArchTLB(unsigned numEntries, unsigned _associativity,
170  const std::string &policy);
171  virtual ~ARMArchTLB() {}
172 
173  const Entry *lookup(Addr va, uint16_t asid, uint16_t vmid,
174  bool updStats=true);
175 
176  void store(const Entry &incoming);
177 
178  void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
179  void invalidateVAA(Addr va, uint16_t vmid);
180  void invalidateASID(uint16_t asid, uint16_t vmid);
181  void invalidateVMID(uint16_t vmid);
182  void invalidateAll();
183 
184  private:
187 
189 
190  size_t pickSetIdx(Addr va, uint16_t asid, uint16_t vmid) const;
191  size_t pickEntryIdxToReplace(const Set &set);
192 };
193 
194 class IPACache : public SMMUv3BaseCache
195 {
196  public:
197  struct Entry
198  {
199  bool valid;
200  mutable uint32_t lastUsed;
201 
202  // TAGS
205  uint16_t vmid;
206 
207  // OUTPUTS
209  uint8_t permissions;
210  };
211 
212  IPACache(unsigned numEntries, unsigned _associativity,
213  const std::string &policy);
214  virtual ~IPACache() {}
215 
216  const Entry *lookup(Addr ipa, uint16_t vmid, bool updStats=true);
217  void store(const Entry &incoming);
218 
219  void invalidateIPA(Addr ipa, uint16_t vmid);
220  void invalidateIPAA(Addr ipa);
221  void invalidateVMID(uint16_t vmid);
222  void invalidateAll();
223 
224  private:
227 
229 
230  size_t pickSetIdx(Addr ipa, uint16_t vmid) const;
231  size_t pickEntryIdxToReplace(const Set &set);
232 };
233 
235 {
236  public:
237  struct Entry
238  {
239  bool valid;
240  mutable uint32_t lastUsed;
241 
242  // TAGS
243  uint32_t sid;
244  uint32_t ssid;
245 
246  // OUTPUTS
247  bool stage1_en;
248  bool stage2_en;
252  uint16_t asid;
253  uint16_t vmid;
254  uint8_t stage1_tg;
255  uint8_t stage2_tg;
256  uint8_t t0sz;
257  uint8_t s2t0sz;
258  };
259 
260  ConfigCache(unsigned numEntries, unsigned _associativity,
261  const std::string &policy);
262  virtual ~ConfigCache() {}
263 
264  const Entry *lookup(uint32_t sid, uint32_t ssid, bool updStats=true);
265  void store(const Entry &incoming);
266 
267  void invalidateSSID(uint32_t sid, uint32_t ssid);
268  void invalidateSID(uint32_t sid);
269  void invalidateAll();
270 
271  private:
274 
276 
277  size_t pickSetIdx(uint32_t sid, uint32_t ssid) const;
278  size_t pickEntryIdxToReplace(const Set &set);
279 };
280 
282 {
283  public:
284  struct Entry
285  {
286  bool valid;
287  mutable uint32_t lastUsed;
288 
289  // TAGS
292  uint16_t asid;
293  uint16_t vmid;
294  unsigned stage;
295  unsigned level;
296 
297  // OUTPUTS
298  bool leaf;
300  uint8_t permissions;
301  };
302 
303  WalkCache(const std::array<unsigned, 2*WALK_CACHE_LEVELS> &_sizes,
304  unsigned _associativity, const std::string &policy);
305  virtual ~WalkCache() {}
306 
307  const Entry *lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid,
308  unsigned stage, unsigned level, bool updStats=true);
309  void store(const Entry &incoming);
310 
311  void invalidateVA(Addr va, uint16_t asid, uint16_t vmid,
312  const bool leaf_only);
313  void invalidateVAA(Addr va, uint16_t vmid, const bool leaf_only);
314  void invalidateASID(uint16_t asid, uint16_t vmid);
315  void invalidateVMID(uint16_t vmid);
316  void invalidateAll();
317 
318  void regStats(const std::string &name) override;
319 
320  protected:
324 
328 
332 
334 
336 
337  private:
340 
342  std::array<unsigned, 2*WALK_CACHE_LEVELS> sizes;
343  std::array<unsigned, 2*WALK_CACHE_LEVELS> offsets;
344 
345  size_t pickSetIdx(Addr va, Addr vaMask,
346  unsigned stage, unsigned level) const;
347 
348  size_t pickEntryIdxToReplace(const Set &set,
349  unsigned stage, unsigned level);
350 };
351 
352 #endif /* __DEV_ARM_SMMU_V3_CACHES_HH__ */
ConfigCache::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:272
WalkCache::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:287
IPACache::invalidateIPAA
void invalidateIPAA(Addr ipa)
Definition: smmu_v3_caches.cc:721
SMMUTLB::lookup
const Entry * lookup(uint32_t sid, uint32_t ssid, Addr va, bool updStats=true)
Definition: smmu_v3_caches.cc:176
SMMUv3BaseCache::totalLookups
Stats::Scalar totalLookups
Definition: smmu_v3_caches.hh:69
IPACache::Entry::ipaMask
Addr ipaMask
Definition: smmu_v3_caches.hh:204
SMMU_CACHE_REPL_ROUND_ROBIN
@ SMMU_CACHE_REPL_ROUND_ROBIN
Definition: smmu_v3_caches.hh:55
ConfigCache::Entry::stage2_tg
uint8_t stage2_tg
Definition: smmu_v3_caches.hh:255
IPACache::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:200
SMMUv3BaseCache::averageLookups
Stats::Formula averageLookups
Definition: smmu_v3_caches.hh:68
WalkCache::lookup
const Entry * lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level, bool updStats=true)
Definition: smmu_v3_caches.cc:1011
ConfigCache::invalidateSSID
void invalidateSSID(uint32_t sid, uint32_t ssid)
Definition: smmu_v3_caches.cc:887
WalkCache::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:286
WalkCache::pickSetIdx
size_t pickSetIdx(Addr va, Addr vaMask, unsigned stage, unsigned level) const
Definition: smmu_v3_caches.cc:1161
IPACache::lookup
const Entry * lookup(Addr ipa, uint16_t vmid, bool updStats=true)
Definition: smmu_v3_caches.cc:655
WalkCache::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:339
WalkCache::Entry::level
unsigned level
Definition: smmu_v3_caches.hh:295
SMMU_CACHE_REPL_RANDOM
@ SMMU_CACHE_REPL_RANDOM
Definition: smmu_v3_caches.hh:56
IPACache::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:688
SMMUv3BaseCache::~SMMUv3BaseCache
virtual ~SMMUv3BaseCache()
Definition: smmu_v3_caches.hh:85
IPACache::invalidateIPA
void invalidateIPA(Addr ipa, uint16_t vmid)
Definition: smmu_v3_caches.cc:708
SMMUTLB::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:141
WalkCache::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:338
ConfigCache::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:253
ARMArchTLB::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:162
SMMUv3BaseCache::averageMisses
Stats::Formula averageMisses
Definition: smmu_v3_caches.hh:71
SMMUTLB::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:117
ARMArchTLB::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:155
SMMUv3BaseCache
Definition: smmu_v3_caches.hh:60
random.hh
ConfigCache::Entry::httb
Addr httb
Definition: smmu_v3_caches.hh:251
SMMUTLB::invalidateVMID
void invalidateVMID(uint16_t vmid)
Definition: smmu_v3_caches.cc:330
ConfigCache::associativity
size_t associativity
Definition: smmu_v3_caches.hh:275
SMMUTLB::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:113
WalkCache::Entry::pa
Addr pa
Definition: smmu_v3_caches.hh:299
WalkCache::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:1054
WalkCache::missesByStageLevel
unsigned int missesByStageLevel[2][WALK_CACHE_LEVELS]
Definition: smmu_v3_caches.hh:325
WalkCache::lookupsByStageLevel
unsigned int lookupsByStageLevel[2][WALK_CACHE_LEVELS]
Definition: smmu_v3_caches.hh:321
WalkCache::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:1150
ConfigCache::Entry::s2t0sz
uint8_t s2t0sz
Definition: smmu_v3_caches.hh:257
std::vector< Entry >
IPACache::~IPACache
virtual ~IPACache()
Definition: smmu_v3_caches.hh:214
WalkCache::Entry
Definition: smmu_v3_caches.hh:284
ConfigCache::Entry::t0sz
uint8_t t0sz
Definition: smmu_v3_caches.hh:256
ConfigCache::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:867
SMMUTLB::pickSetIdx
size_t pickSetIdx(uint32_t sid, uint32_t ssid) const
Definition: smmu_v3_caches.cc:362
SMMUv3BaseCache::useStamp
uint32_t useStamp
Definition: smmu_v3_caches.hh:66
WalkCache::sizes
std::array< unsigned, 2 *WALK_CACHE_LEVELS > sizes
Definition: smmu_v3_caches.hh:342
SMMUTLB::Entry::va
Addr va
Definition: smmu_v3_caches.hh:108
ARMArchTLB::lookup
const Entry * lookup(Addr va, uint16_t asid, uint16_t vmid, bool updStats=true)
Definition: smmu_v3_caches.cc:456
SMMUTLB::invalidateSSID
void invalidateSSID(uint32_t sid, uint32_t ssid)
Definition: smmu_v3_caches.cc:258
WalkCache::Entry::vaMask
Addr vaMask
Definition: smmu_v3_caches.hh:291
ARMArchTLB::Entry::vaMask
Addr vaMask
Definition: smmu_v3_caches.hh:160
WalkCache::Entry::asid
uint16_t asid
Definition: smmu_v3_caches.hh:292
WalkCache::averageMissesByStageLevel
Stats::Formula averageMissesByStageLevel[2][WALK_CACHE_LEVELS]
Definition: smmu_v3_caches.hh:326
SMMUTLB::Entry
Definition: smmu_v3_caches.hh:99
SMMUTLB::invalidateVA
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:286
SMMU_CACHE_REPL_LRU
@ SMMU_CACHE_REPL_LRU
Definition: smmu_v3_caches.hh:57
SMMUTLB::ALLOC_ANY_WAY
@ ALLOC_ANY_WAY
Definition: smmu_v3_caches.hh:94
WalkCache::invalidateVAA
void invalidateVAA(Addr va, uint16_t vmid, const bool leaf_only)
Definition: smmu_v3_caches.cc:1102
IPACache::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:205
ConfigCache::Entry::stage1_en
bool stage1_en
Definition: smmu_v3_caches.hh:247
Stats::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:2533
IPACache::associativity
size_t associativity
Definition: smmu_v3_caches.hh:228
ARMArchTLB::~ARMArchTLB
virtual ~ARMArchTLB()
Definition: smmu_v3_caches.hh:171
IPACache::Entry
Definition: smmu_v3_caches.hh:197
SMMUTLB::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:345
WalkCache::totalUpdatesByStageLevel
Stats::Scalar totalUpdatesByStageLevel[2][WALK_CACHE_LEVELS]
Definition: smmu_v3_caches.hh:331
SMMUTLB::Entry::asid
uint16_t asid
Definition: smmu_v3_caches.hh:112
SMMUTLB::invalidateVAA
void invalidateVAA(Addr va, uint16_t vmid)
Definition: smmu_v3_caches.cc:302
SMMUTLB::AllocPolicy
AllocPolicy
Definition: smmu_v3_caches.hh:93
WALK_CACHE_LEVELS
#define WALK_CACHE_LEVELS
Definition: smmu_v3_caches.hh:52
WalkCache::invalidateVA
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid, const bool leaf_only)
Definition: smmu_v3_caches.cc:1083
ARMArchTLB::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:185
SMMUv3BaseCache::nextToReplace
size_t nextToReplace
Definition: smmu_v3_caches.hh:64
SMMUv3BaseCache::random
Random random
Definition: smmu_v3_caches.hh:65
Random
Definition: random.hh:58
ARMArchTLB::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:166
ARMArchTLB::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:156
IPACache::IPACache
IPACache(unsigned numEntries, unsigned _associativity, const std::string &policy)
Definition: smmu_v3_caches.cc:625
SMMUTLB::ALLOC_ANY_BUT_LAST_WAY
@ ALLOC_ANY_BUT_LAST_WAY
Definition: smmu_v3_caches.hh:95
ConfigCache
Definition: smmu_v3_caches.hh:234
SMMUTLB::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:103
SMMUTLB::invalidateASID
void invalidateASID(uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:315
WalkCache::Entry::stage
unsigned stage
Definition: smmu_v3_caches.hh:294
SMMUTLB
Definition: smmu_v3_caches.hh:90
SMMUv3BaseCache::averageUpdates
Stats::Formula averageUpdates
Definition: smmu_v3_caches.hh:74
SMMUv3BaseCache::totalUpdates
Stats::Scalar totalUpdates
Definition: smmu_v3_caches.hh:75
ConfigCache::Entry::sid
uint32_t sid
Definition: smmu_v3_caches.hh:243
statistics.hh
SMMUv3BaseCache::insertions
Stats::Scalar insertions
Definition: smmu_v3_caches.hh:79
IPACache::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:209
IPACache::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:751
WalkCache::WalkCache
WalkCache(const std::array< unsigned, 2 *WALK_CACHE_LEVELS > &_sizes, unsigned _associativity, const std::string &policy)
Definition: smmu_v3_caches.cc:969
ConfigCache::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:239
SMMUTLB::ALLOC_LAST_WAY
@ ALLOC_LAST_WAY
Definition: smmu_v3_caches.hh:96
WalkCache::averageHitRateByStageLevel
Stats::Formula averageHitRateByStageLevel[2][WALK_CACHE_LEVELS]
Definition: smmu_v3_caches.hh:333
WalkCache::~WalkCache
virtual ~WalkCache()
Definition: smmu_v3_caches.hh:305
ConfigCache::lookup
const Entry * lookup(uint32_t sid, uint32_t ssid, bool updStats=true)
Definition: smmu_v3_caches.cc:835
SMMUTLB::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:140
ARMArchTLB::ARMArchTLB
ARMArchTLB(unsigned numEntries, unsigned _associativity, const std::string &policy)
Definition: smmu_v3_caches.cc:426
ARMArchTLB::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:489
ConfigCache::Entry::ssid
uint32_t ssid
Definition: smmu_v3_caches.hh:244
ARMArchTLB::Entry
Definition: smmu_v3_caches.hh:153
IPACache::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:225
IPACache::Entry::ipa
Addr ipa
Definition: smmu_v3_caches.hh:203
ConfigCache::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set)
Definition: smmu_v3_caches.cc:932
IPACache::pickSetIdx
size_t pickSetIdx(Addr ipa, uint16_t vmid) const
Definition: smmu_v3_caches.cc:762
IPACache::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set)
Definition: smmu_v3_caches.cc:768
ConfigCache::Entry::ttb1
Addr ttb1
Definition: smmu_v3_caches.hh:250
WalkCache::totalLookupsByStageLevel
Stats::Scalar totalLookupsByStageLevel[2][WALK_CACHE_LEVELS]
Definition: smmu_v3_caches.hh:323
ConfigCache::Entry::ttb0
Addr ttb0
Definition: smmu_v3_caches.hh:249
SMMUTLB::SMMUTLB
SMMUTLB(unsigned numEntries, unsigned _associativity, const std::string &policy)
Definition: smmu_v3_caches.cc:146
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
WalkCache::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:300
WalkCache::averageLookupsByStageLevel
Stats::Formula averageLookupsByStageLevel[2][WALK_CACHE_LEVELS]
Definition: smmu_v3_caches.hh:322
name
const std::string & name()
Definition: trace.cc:50
ConfigCache::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:240
WalkCache::insertionsByStageLevel
Stats::Scalar insertionsByStageLevel[2][WALK_CACHE_LEVELS]
Definition: smmu_v3_caches.hh:335
WalkCache::associativity
size_t associativity
Definition: smmu_v3_caches.hh:341
ARMArchTLB::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set)
Definition: smmu_v3_caches.cc:588
WalkCache::regStats
void regStats(const std::string &name) override
Definition: smmu_v3_caches.cc:1225
WalkCache::Entry::va
Addr va
Definition: smmu_v3_caches.hh:290
IPACache::invalidateVMID
void invalidateVMID(uint16_t vmid)
Definition: smmu_v3_caches.cc:736
ArmISA::asid
asid
Definition: miscregs_types.hh:611
WalkCache::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set, unsigned stage, unsigned level)
Definition: smmu_v3_caches.cc:1189
WalkCache::invalidateASID
void invalidateASID(uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:1120
ConfigCache::invalidateSID
void invalidateSID(uint32_t sid)
Definition: smmu_v3_caches.cc:900
ConfigCache::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:273
X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:47
ARMArchTLB::invalidateASID
void invalidateASID(uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:541
ConfigCache::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:915
SMMUTLB::Entry::ssid
uint32_t ssid
Definition: smmu_v3_caches.hh:107
IPACache::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:199
ARMArchTLB::Entry::asid
uint16_t asid
Definition: smmu_v3_caches.hh:161
WalkCache
Definition: smmu_v3_caches.hh:281
SMMUTLB::store
void store(const Entry &incoming, AllocPolicy alloc)
Definition: smmu_v3_caches.cc:237
types.hh
SMMUTLB::invalidateSID
void invalidateSID(uint32_t sid)
Definition: smmu_v3_caches.cc:271
SMMUv3BaseCache::replacementPolicy
int replacementPolicy
Definition: smmu_v3_caches.hh:63
SMMUv3BaseCache::decodePolicyName
static int decodePolicyName(const std::string &policy_name)
Definition: smmu_v3_caches.cc:69
SMMUTLB::Entry::prefetched
bool prefetched
Definition: smmu_v3_caches.hh:102
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A formula for statistics that is calculated when printed.
Definition: statistics.hh:3037
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Definition: smmu_v3_caches.cc:526
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Definition: smmu_v3_caches.hh:72
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Definition: smmu_v3_caches.cc:368
SMMUv3BaseCache::SMMUv3BaseCache
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Definition: smmu_v3_caches.cc:61
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Definition: smmu_v3_caches.hh:186
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Definition: smmu_v3_caches.hh:226
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Definition: smmu_v3_caches.hh:159
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Definition: smmu_v3_caches.hh:109
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Definition: smmu_v3_caches.hh:194
ARMArchTLB
Definition: smmu_v3_caches.hh:150
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Definition: smmu_v3_caches.hh:208
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Definition: smmu_v3_caches.hh:254
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Definition: smmu_v3_caches.hh:188
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Definition: smmu_v3_caches.hh:101
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Definition: smmu_v3_caches.cc:571
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Definition: smmu_v3_caches.hh:330
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Definition: smmu_v3_caches.hh:343
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Definition: smmu_v3_caches.cc:556
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Definition: smmu_v3_caches.cc:582
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Definition: smmu_v3_caches.cc:805
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Definition: smmu_v3_caches.hh:77
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Definition: smmu_v3_caches.hh:293
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Definition: smmu_v3_caches.cc:510
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Definition: smmu_v3_caches.hh:106
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Definition: smmu_v3_caches.hh:329
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Definition: smmu_v3_caches.cc:83
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Definition: smmu_v3_caches.hh:298
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Definition: smmu_v3_caches.hh:143
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Definition: smmu_v3_caches.cc:926
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Definition: smmu_v3_caches.hh:116
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Definition: smmu_v3_caches.hh:262
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Definition: smmu_v3_caches.hh:237
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Definition: smmu_v3_caches.hh:248
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Definition: miscregs_types.hh:88
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Definition: smmu_v3_caches.hh:123
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Definition: smmu_v3_caches.hh:165
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Definition: miscregs_types.hh:272
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Definition: smmu_v3_caches.hh:252
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Definition: smmu_v3_caches.hh:327
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Definition: smmu_v3_caches.cc:210

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