gem5  v20.1.0.0
standard.hh
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1 /*
2  * Copyright (c) 2015 RISC-V Foundation
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4  * Copyright (c) 2020 Barkhausen Institut
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30 
31 #ifndef __ARCH_RISCV_STANDARD_INST_HH__
32 #define __ARCH_RISCV_STANDARD_INST_HH__
33 
34 #include <string>
35 
38 #include "cpu/exec_context.hh"
39 #include "cpu/static_inst.hh"
40 
41 namespace RiscvISA
42 {
43 
47 class RegOp : public RiscvStaticInst
48 {
49  protected:
50  using RiscvStaticInst::RiscvStaticInst;
51 
52  std::string generateDisassembly(
53  Addr pc, const Loader::SymbolTable *symtab) const override;
54 };
55 
59 template<typename I>
60 class ImmOp : public RiscvStaticInst
61 {
62  protected:
63  I imm;
64 
65  ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
66  : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
67  {}
68 };
69 
73 class SystemOp : public RiscvStaticInst
74 {
75  protected:
76  using RiscvStaticInst::RiscvStaticInst;
77 
78  std::string generateDisassembly(
79  Addr pc, const Loader::SymbolTable *symtab) const override;
80 };
81 
85 class CSROp : public RiscvStaticInst
86 {
87  protected:
88  uint64_t csr;
89  uint64_t uimm;
90 
92  CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
93  : RiscvStaticInst(mnem, _machInst, __opClass),
95  {}
96 
97  std::string generateDisassembly(
98  Addr pc, const Loader::SymbolTable *symtab) const override;
99 };
100 
101 }
102 
103 #endif // __ARCH_RISCV_STANDARD_INST_HH__
RiscvISA::CSROp::CSROp
CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: standard.hh:92
CSRIMM
#define CSRIMM
Definition: bitfields.hh:6
RiscvISA::MachInst
uint32_t MachInst
Definition: types.hh:50
RiscvISA::ImmOp
Base class for operations with immediates (I is the type of immediate)
Definition: standard.hh:60
FUNCT12
#define FUNCT12
Definition: bitfields.hh:7
RiscvISA::CSROp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: standard.cc:59
RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
Loader::SymbolTable
Definition: symtab.hh:59
RiscvISA::SystemOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: standard.cc:76
RiscvISA::ImmOp::imm
I imm
Definition: standard.hh:63
RiscvISA
Definition: fs_workload.cc:36
RiscvISA::RegOp
Base class for operations that work only on registers.
Definition: standard.hh:47
RiscvISA::ImmOp::ImmOp
ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Definition: standard.hh:65
RiscvISA::RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: standard.cc:46
static_inst.hh
static_inst.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:46
RiscvISA::SystemOp
Base class for system operations.
Definition: standard.hh:73
RiscvISA::CSROp::uimm
uint64_t uimm
Definition: standard.hh:89
exec_context.hh
RiscvISA::CSROp
Base class for CSR operations.
Definition: standard.hh:85
RiscvISA::CSROp::csr
uint64_t csr
Definition: standard.hh:88
bitfields.hh

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