gem5
v20.1.0.0
arch
riscv
types.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2013 ARM Limited
3
* Copyright (c) 2014 Sven Karlsson
4
* All rights reserved
5
*
6
* The license below extends only to copyright in the software and shall
7
* not be construed as granting a license to any other intellectual
8
* property including but not limited to intellectual property relating
9
* to a hardware implementation of the functionality of the software
10
* licensed hereunder. You may use the software subject to the license
11
* terms below provided that you ensure that this notice is replicated
12
* unmodified and in its entirety in all distributions of the software,
13
* modified or unmodified, in source code or in binary form.
14
*
15
* Copyright (c) 2017 The University of Virginia
16
* All rights reserved.
17
*
18
* Redistribution and use in source and binary forms, with or without
19
* modification, are permitted provided that the following conditions are
20
* met: redistributions of source code must retain the above copyright
21
* notice, this list of conditions and the following disclaimer;
22
* redistributions in binary form must reproduce the above copyright
23
* notice, this list of conditions and the following disclaimer in the
24
* documentation and/or other materials provided with the distribution;
25
* neither the name of the copyright holders nor the names of its
26
* contributors may be used to endorse or promote products derived from
27
* this software without specific prior written permission.
28
*
29
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40
*/
41
42
#ifndef __ARCH_RISCV_TYPES_HH__
43
#define __ARCH_RISCV_TYPES_HH__
44
45
#include "
arch/generic/types.hh
"
46
47
namespace
RiscvISA
48
{
49
50
typedef
uint32_t
MachInst
;
51
typedef
uint64_t
ExtMachInst
;
52
53
class
PCState
:
public
GenericISA::UPCState
<MachInst>
54
{
55
private
:
56
bool
_compressed
;
57
bool
_rv32
;
58
59
public
:
60
PCState
() :
UPCState
() {
_compressed
=
false
;
_rv32
=
false
; }
61
PCState
(
Addr
val
) :
UPCState
(
val
) {
_compressed
=
false
;
_rv32
=
false
; }
62
63
void
compressed
(
bool
c
) {
_compressed
=
c
; }
64
bool
compressed
() {
return
_compressed
; }
65
66
void
rv32
(
bool
val
) {
_rv32
=
val
; }
67
bool
rv32
()
const
{
return
_rv32
; }
68
69
bool
70
branching
()
const
71
{
72
if
(
_compressed
) {
73
return
npc
() !=
pc
() +
sizeof
(
MachInst
)/2 ||
74
nupc
() !=
upc
() + 1;
75
}
else
{
76
return
npc
() !=
pc
() +
sizeof
(
MachInst
) ||
77
nupc
() !=
upc
() + 1;
78
}
79
}
80
};
81
82
}
83
84
#endif // __ARCH_RISCV_TYPES_HH__
RiscvISA::PCState
Definition:
types.hh:53
RiscvISA::c
Bitfield< 5, 3 > c
Definition:
pra_constants.hh:56
RiscvISA::MachInst
uint32_t MachInst
Definition:
types.hh:50
RiscvISA::PCState::compressed
bool compressed()
Definition:
types.hh:64
RiscvISA::PCState::PCState
PCState(Addr val)
Definition:
types.hh:61
RiscvISA::PCState::rv32
bool rv32() const
Definition:
types.hh:67
GenericISA::UPCState::upc
MicroPC upc() const
Definition:
types.hh:215
RiscvISA::PCState::compressed
void compressed(bool c)
Definition:
types.hh:63
RiscvISA
Definition:
fs_workload.cc:36
GenericISA::SimplePCState::npc
Addr npc() const
Definition:
types.hh:161
RiscvISA::PCState::branching
bool branching() const
Definition:
types.hh:70
RiscvISA::PCState::rv32
void rv32(bool val)
Definition:
types.hh:66
X86ISA::val
Bitfield< 63 > val
Definition:
misc.hh:769
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:142
RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition:
types.hh:51
types.hh
GenericISA::UPCState::nupc
MicroPC nupc() const
Definition:
types.hh:218
RiscvISA::PCState::PCState
PCState()
Definition:
types.hh:60
GenericISA::SimplePCState::pc
Addr pc() const
Definition:
types.hh:158
GenericISA::UPCState::UPCState
UPCState()
Definition:
types.hh:235
RiscvISA::PCState::_compressed
bool _compressed
Definition:
types.hh:56
GenericISA::UPCState
Definition:
types.hh:205
RiscvISA::PCState::_rv32
bool _rv32
Definition:
types.hh:57
Generated on Wed Sep 30 2020 14:02:01 for gem5 by
doxygen
1.8.17