gem5
v20.1.0.0
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#include <fstream>
#include <unordered_map>
#include "arch/arm/registers.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "mem/request.hh"
#include "params/TarmacParser.hh"
#include "sim/insttracer.hh"
#include "tarmac_base.hh"
Go to the source code of this file.
Classes | |
class | Trace::TarmacParserRecord |
struct | Trace::TarmacParserRecord::TarmacParserRecordEvent |
Event triggered to check the value of the destination registers. More... | |
struct | Trace::TarmacParserRecord::ParserInstEntry |
struct | Trace::TarmacParserRecord::ParserRegEntry |
struct | Trace::TarmacParserRecord::ParserMemEntry |
class | Trace::TarmacParser |
Tarmac Parser: this tracer parses an existing Tarmac trace and it diffs it with gem5 simulation status, comparing results and reporting architectural mismatches if any. More... | |
Namespaces | |
Trace | |