gem5
v20.1.0.0
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#include <tarmac_parser.hh>
Classes | |
struct | ParserInstEntry |
struct | ParserMemEntry |
struct | ParserRegEntry |
struct | TarmacParserRecordEvent |
Event triggered to check the value of the destination registers. More... | |
Public Member Functions | |
TarmacParserRecord (Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, ArmISA::PCState _pc, TarmacParser &_parent, const StaticInstPtr _macroStaticInst=NULL) | |
void | dump () override |
bool | readMemNoEffect (Addr addr, uint8_t *data, unsigned size, unsigned flags) |
Performs a memory access to read the value written by a previous write. More... | |
Public Member Functions inherited from Trace::TarmacBaseRecord | |
TarmacBaseRecord (Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, ArmISA::PCState _pc, const StaticInstPtr _macroStaticInst=NULL) | |
Public Member Functions inherited from Trace::InstRecord | |
InstRecord (Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, TheISA::PCState _pc, const StaticInstPtr _macroStaticInst=NULL) | |
virtual | ~InstRecord () |
void | setWhen (Tick new_when) |
void | setMem (Addr a, Addr s, unsigned f) |
template<typename T , size_t N> | |
void | setData (std::array< T, N > d) |
void | setData (uint64_t d) |
void | setData (uint32_t d) |
void | setData (uint16_t d) |
void | setData (uint8_t d) |
void | setData (int64_t d) |
void | setData (int32_t d) |
void | setData (int16_t d) |
void | setData (int8_t d) |
void | setData (double d) |
void | setData (::VecRegContainer< TheISA::VecRegSizeBytes > &d) |
void | setData (::VecPredRegContainer< TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr > &d) |
void | setFetchSeq (InstSeqNum seq) |
void | setCPSeq (InstSeqNum seq) |
void | setPredicate (bool val) |
void | setFaulting (bool val) |
Tick | getWhen () const |
ThreadContext * | getThread () const |
StaticInstPtr | getStaticInst () const |
TheISA::PCState | getPCState () const |
StaticInstPtr | getMacroStaticInst () const |
Addr | getAddr () const |
Addr | getSize () const |
unsigned | getFlags () const |
bool | getMemValid () const |
uint64_t | getIntData () const |
double | getFloatData () const |
int | getDataStatus () const |
InstSeqNum | getFetchSeq () const |
bool | getFetchSeqValid () const |
InstSeqNum | getCpSeq () const |
bool | getCpSeqValid () const |
bool | getFaulting () const |
Static Public Member Functions | |
static void | printMismatchHeader (const StaticInstPtr inst, ArmISA::PCState pc) |
Print a mismatch header containing the instruction fields as reported by gem5. More... | |
Static Public Member Functions inherited from Trace::TarmacBaseRecord | |
static ISetState | pcToISetState (ArmISA::PCState pc) |
Returns the Instruction Set State according to the current PCState. More... | |
Static Public Attributes | |
static const int | MaxLineLength = 256 |
Protected Attributes | |
TarmacParser & | parent |
Protected Attributes inherited from Trace::InstRecord | |
Tick | when |
ThreadContext * | thread |
StaticInstPtr | staticInst |
TheISA::PCState | pc |
StaticInstPtr | macroStaticInst |
Addr | addr |
The address that was accessed. More... | |
Addr | size |
The size of the memory request. More... | |
unsigned | flags |
The flags that were assigned to the request. More... | |
union { | |
uint64_t as_int | |
double as_double | |
::VecRegContainer< TheISA::VecRegSizeBytes > * as_vec | |
::VecPredRegContainer< TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr > * as_pred | |
} | data |
InstSeqNum | fetch_seq |
InstSeqNum | cp_seq |
enum Trace::InstRecord::DataStatus | data_status |
bool | mem_valid |
bool | fetch_seq_valid |
bool | cp_seq_valid |
bool | predicate |
is the predicate for execution this inst true or false (not execed)? More... | |
bool | faulting |
Did the execution of this instruction fault? (requires ExecFaulting to be enabled) More... | |
Private Types | |
using | MiscRegMap = std::unordered_map< std::string, RegIndex > |
Map from misc. More... | |
Private Member Functions | |
bool | advanceTrace () |
Advances the TARMAC trace up to the next instruction, register, or memory access record. More... | |
const char * | iSetStateToStr (ISetState isetstate) const |
Returns the string representation of an instruction set state. More... | |
Private Attributes | |
bool | parsingStarted |
True if a TARMAC instruction record has already been parsed for this instruction. More... | |
bool | mismatch |
True if a mismatch has been detected for this instruction. More... | |
bool | mismatchOnPcOrOpcode |
True if a mismatch has been detected for this instruction on PC or opcode. More... | |
RequestPtr | memReq |
Request for memory write checks. More... | |
Static Private Attributes | |
static ParserInstEntry | instRecord |
Buffer for instruction trace records. More... | |
static ParserRegEntry | regRecord |
Buffer for register trace records. More... | |
static ParserMemEntry | memRecord |
Buffer for memory access trace records (stores only). More... | |
static TarmacRecordType | currRecordType |
Type of last parsed record. More... | |
static char | buf [MaxLineLength] |
Buffer used for trace file parsing. More... | |
static std::list< ParserRegEntry > | destRegRecords |
List of records of destination registers. More... | |
static MiscRegMap | miscRegMap |
static int8_t | maxVectorLength = 0 |
Max. More... | |
Additional Inherited Members | |
Public Types inherited from Trace::TarmacBaseRecord | |
enum | TarmacRecordType { TARMAC_INST, TARMAC_REG, TARMAC_MEM, TARMAC_UNSUPPORTED } |
TARMAC trace record type. More... | |
enum | ISetState { ISET_ARM, ISET_THUMB, ISET_A64, ISET_UNSUPPORTED } |
ARM instruction set state. More... | |
enum | RegType { REG_R, REG_X, REG_S, REG_D, REG_P, REG_Q, REG_Z, REG_MISC } |
ARM register type. More... | |
Protected Types inherited from Trace::InstRecord | |
enum | DataStatus { DataInvalid = 0, DataInt8 = 1, DataInt16 = 2, DataInt32 = 4, DataInt64 = 8, DataDouble = 3, DataVec = 5, DataVecPred = 6 } |
Definition at line 64 of file tarmac_parser.hh.
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private |
Trace::TarmacParserRecord::TarmacParserRecord | ( | Tick | _when, |
ThreadContext * | _thread, | ||
const StaticInstPtr | _staticInst, | ||
ArmISA::PCState | _pc, | ||
TarmacParser & | _parent, | ||
const StaticInstPtr | _macroStaticInst = NULL |
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) |
Definition at line 956 of file tarmac_parser.cc.
References maxVectorLength, and memReq.
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private |
Advances the TARMAC trace up to the next instruction, register, or memory access record.
The collected data is stored in one of {inst/reg/mem}_record.
Definition at line 1080 of file tarmac_parser.cc.
References buf, ArmISA::c, Trace::TarmacParser::cpuId, currRecordType, Trace::InstRecord::data, ArmISA::i, Trace::TarmacBaseRecord::RegEntry::index, instRecord, ArmISA::INTREG_ABT(), ArmISA::INTREG_FIQ(), ArmISA::INTREG_HYP(), ArmISA::INTREG_IRQ(), ArmISA::INTREG_MON(), ArmISA::INTREG_SP0, ArmISA::INTREG_SVC(), ArmISA::INTREG_UND(), ArmISA::INTREG_USR(), Trace::TarmacBaseRecord::ISET_A64, Trace::TarmacBaseRecord::ISET_ARM, Trace::TarmacBaseRecord::ISET_THUMB, Trace::TarmacBaseRecord::ISET_UNSUPPORTED, ArmISA::lo, MaxLineLength, maxVectorLength, memRecord, Trace::TarmacParser::memWrCheck, miscRegMap, parent, parsingStarted, Trace::TarmacBaseRecord::REG_D, Trace::TarmacBaseRecord::REG_MISC, Trace::TarmacBaseRecord::REG_P, Trace::TarmacBaseRecord::REG_Q, Trace::TarmacBaseRecord::REG_R, Trace::TarmacBaseRecord::REG_S, Trace::TarmacBaseRecord::REG_X, Trace::TarmacBaseRecord::REG_Z, regRecord, Trace::TarmacParserRecord::ParserRegEntry::repr, Trace::TarmacParserRecord::ParserInstEntry::seq_num, Trace::TarmacBaseRecord::TARMAC_INST, Trace::TarmacBaseRecord::TARMAC_MEM, Trace::TarmacBaseRecord::TARMAC_REG, Trace::TarmacBaseRecord::TARMAC_UNSUPPORTED, Trace::TarmacParser::trace, Trace::TarmacBaseRecord::RegEntry::type, ArmISA::v, Trace::TarmacBaseRecord::RegEntry::values, and warn.
Referenced by dump().
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overridevirtual |
Implements Trace::TarmacBaseRecord.
Definition at line 973 of file tarmac_parser.cc.
References advanceTrace(), ArmISA::TLB::AllowUnaligned, currRecordType, curTick(), destRegRecords, MipsISA::event, Trace::TarmacParser::exitOnDiff, Trace::TarmacParser::exitOnInsnDiff, exitSimLoop(), RefCountingPtr< T >::get(), instRecord, Trace::TarmacBaseRecord::ISET_UNSUPPORTED, iSetStateToStr(), StaticInst::isLastMicroop(), StaticInst::isMicroop(), Trace::TarmacParser::macroopInProgress, mainEventQueue, memRecord, mismatch, mismatchOnPcOrOpcode, Trace::output(), panic, parent, parsingStarted, Trace::InstRecord::pc, Trace::TarmacBaseRecord::pcToISetState(), printMismatchHeader(), readMemNoEffect(), regRecord, Trace::InstRecord::staticInst, Trace::TarmacBaseRecord::TARMAC_INST, Trace::TarmacBaseRecord::TARMAC_MEM, Trace::TarmacBaseRecord::TARMAC_REG, Trace::TarmacBaseRecord::TARMAC_UNSUPPORTED, and Trace::InstRecord::thread.
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private |
Returns the string representation of an instruction set state.
Definition at line 1351 of file tarmac_parser.cc.
References Trace::TarmacBaseRecord::ISET_A64, Trace::TarmacBaseRecord::ISET_ARM, and Trace::TarmacBaseRecord::ISET_THUMB.
Referenced by dump().
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static |
Print a mismatch header containing the instruction fields as reported by gem5.
Definition at line 943 of file tarmac_parser.cc.
References curTick(), StaticInst::disassemble(), StaticInst::machInst, Trace::output(), and MipsISA::pc.
Referenced by dump().
bool Trace::TarmacParserRecord::readMemNoEffect | ( | Addr | addr, |
uint8_t * | data, | ||
unsigned | size, | ||
unsigned | flags | ||
) |
Performs a memory access to read the value written by a previous write.
Definition at line 1283 of file tarmac_parser.cc.
References Trace::InstRecord::addr, AddrRange::contains(), Trace::InstRecord::data, Trace::InstRecord::flags, Request::funcRequestorId, ThreadContext::getDTBPtr(), ThreadContext::getVirtProxy(), Trace::TarmacParser::ignoredAddrRange, memReq, Request::NO_ACCESS, NoFault, parent, ThreadContext::pcState(), BaseTLB::Read, PortProxy::readBlob(), Trace::InstRecord::size, Trace::InstRecord::thread, and ArmISA::TLB::translateAtomic().
Referenced by dump().
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staticprivate |
Buffer used for trace file parsing.
Definition at line 173 of file tarmac_parser.hh.
Referenced by advanceTrace().
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staticprivate |
Type of last parsed record.
Definition at line 170 of file tarmac_parser.hh.
Referenced by advanceTrace(), and dump().
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staticprivate |
List of records of destination registers.
Definition at line 176 of file tarmac_parser.hh.
Referenced by dump().
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staticprivate |
Buffer for instruction trace records.
Definition at line 161 of file tarmac_parser.hh.
Referenced by advanceTrace(), and dump().
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static |
Definition at line 124 of file tarmac_parser.hh.
Referenced by advanceTrace(), and Trace::TarmacParser::advanceTraceToStartPc().
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staticprivate |
Max.
vector length (SVE).
Definition at line 201 of file tarmac_parser.hh.
Referenced by advanceTrace(), and TarmacParserRecord().
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staticprivate |
Buffer for memory access trace records (stores only).
Definition at line 167 of file tarmac_parser.hh.
Referenced by advanceTrace(), and dump().
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private |
Request for memory write checks.
Definition at line 198 of file tarmac_parser.hh.
Referenced by readMemNoEffect(), and TarmacParserRecord().
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staticprivate |
Definition at line 180 of file tarmac_parser.hh.
Referenced by advanceTrace().
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private |
True if a mismatch has been detected for this instruction.
Definition at line 189 of file tarmac_parser.hh.
Referenced by dump().
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True if a mismatch has been detected for this instruction on PC or opcode.
Definition at line 195 of file tarmac_parser.hh.
Referenced by dump().
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protected |
Definition at line 204 of file tarmac_parser.hh.
Referenced by advanceTrace(), dump(), and readMemNoEffect().
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private |
True if a TARMAC instruction record has already been parsed for this instruction.
Definition at line 186 of file tarmac_parser.hh.
Referenced by advanceTrace(), and dump().
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staticprivate |
Buffer for register trace records.
Definition at line 164 of file tarmac_parser.hh.
Referenced by advanceTrace(), and dump().