gem5
v20.1.0.0
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#include "arch/x86/interrupts.hh"
#include <list>
#include <memory>
#include "arch/x86/intmessage.hh"
#include "arch/x86/regs/apic.hh"
#include "cpu/base.hh"
#include "debug/LocalApic.hh"
#include "dev/x86/i82094aa.hh"
#include "dev/x86/pc.hh"
#include "dev/x86/south_bridge.hh"
#include "mem/packet_access.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"
Go to the source code of this file.
Namespaces | |
X86ISA | |
This is exposed globally, independent of the ISA. | |
Functions | |
int | divideFromConf (uint32_t conf) |
ApicRegIndex | X86ISA::decodeAddr (Addr paddr) |
int divideFromConf | ( | uint32_t | conf | ) |
Definition at line 67 of file interrupts.cc.
References ArmISA::shift.
Referenced by X86ISA::Interrupts::readReg(), and X86ISA::Interrupts::setReg().