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systemc
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2.5
T_2_5.h
Go to the documentation of this file.
1
/*****************************************************************************
2
3
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4
more contributor license agreements. See the NOTICE file distributed
5
with this work for additional information regarding copyright ownership.
6
Accellera licenses this file to you under the Apache License, Version 2.0
7
(the "License"); you may not use this file except in compliance with the
8
License. You may obtain a copy of the License at
9
10
http://www.apache.org/licenses/LICENSE-2.0
11
12
Unless required by applicable law or agreed to in writing, software
13
distributed under the License is distributed on an "AS IS" BASIS,
14
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15
implied. See the License for the specific language governing
16
permissions and limitations under the License.
17
18
*****************************************************************************/
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20
/*****************************************************************************
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T_2_5.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26
*****************************************************************************/
27
28
/*****************************************************************************
29
30
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31
changes you are making here.
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33
Name, Affiliation, Date:
34
Description of Modification:
35
36
*****************************************************************************/
37
38
SC_MODULE
( MYNAME )
39
{
40
SC_HAS_PROCESS
( MYNAME );
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sc_in_clk
clk;
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const
signal_vector&
x
;
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const
signal_vector& y;
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signal_vector&
z
;
47
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sc_bigint<WIDTH>
a1
;
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sc_bigint<WIDTH+2> a2;
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sc_biguint<WIDTH>
b1
;
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sc_biguint<WIDTH+2>
b2
;
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sc_bv<WIDTH> c1;
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sc_bv<WIDTH+2>
c2
;
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sc_lv<WIDTH> d1;
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sc_lv<WIDTH+2> d2;
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MYNAME( sc_module_name NAME,
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sc_clock& CLK,
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const
signal_vector&
X
,
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const
signal_vector& Y,
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signal_vector& Z )
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:
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x
(
X
), y(Y),
z
(Z)
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{
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clk(CLK);
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SC_CTHREAD
( entry, clk.pos() );
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}
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void
entry();
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};
QARMA::b1
Bitfield< 7, 4 > b1
Definition:
qarma.hh:62
X86ISA::X
Bitfield< 15, 0 > X
Definition:
int.hh:53
MipsISA::c2
Bitfield< 6 > c2
Definition:
pra_constants.hh:238
ArmISA::z
Bitfield< 11 > z
Definition:
miscregs_types.hh:370
RiscvISA::x
Bitfield< 3 > x
Definition:
pagetable.hh:69
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
QARMA::b2
Bitfield< 11, 8 > b2
Definition:
qarma.hh:61
SC_MODULE
SC_MODULE(MYNAME)
Definition:
T_2_5.h:38
ArmISA::a1
Bitfield< 22 > a1
Definition:
miscregs_types.hh:495
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