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isa.cc
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37 
38 #include "arch/arm/isa.hh"
39 
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/htm.hh"
42 #include "arch/arm/interrupts.hh"
43 #include "arch/arm/pmu.hh"
44 #include "arch/arm/self_debug.hh"
45 #include "arch/arm/system.hh"
46 #include "arch/arm/tlb.hh"
47 #include "arch/arm/tlbi_op.hh"
48 #include "cpu/base.hh"
49 #include "cpu/checker/cpu.hh"
50 #include "debug/Arm.hh"
51 #include "debug/MiscRegs.hh"
52 #include "dev/arm/generic_timer.hh"
53 #include "dev/arm/gic_v3.hh"
54 #include "dev/arm/gic_v3_cpu_interface.hh"
55 #include "params/ArmISA.hh"
56 #include "sim/faults.hh"
57 #include "sim/stat_control.hh"
58 #include "sim/system.hh"
59 
60 namespace ArmISA
61 {
62 
63 ISA::ISA(Params *p) : BaseISA(p), system(NULL),
64  _decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full),
65  pmu(p->pmu), impdefAsNop(p->impdef_nop),
66  afterStartup(false)
67 {
68  miscRegs[MISCREG_SCTLR_RST] = 0;
69 
70  // Hook up a dummy device if we haven't been configured with a
71  // real PMU. By using a dummy device, we don't need to check that
72  // the PMU exist every time we try to access a PMU register.
73  if (!pmu)
74  pmu = &dummyDevice;
75 
76  // Give all ISA devices a pointer to this ISA
77  pmu->setISA(this);
78 
79  system = dynamic_cast<ArmSystem *>(p->system);
80 
81  // Cache system-level properties
82  if (FullSystem && system) {
83  highestELIs64 = system->highestELIs64();
84  haveSecurity = system->haveSecurity();
85  haveLPAE = system->haveLPAE();
86  haveCrypto = system->haveCrypto();
87  haveVirtualization = system->haveVirtualization();
88  haveLargeAsid64 = system->haveLargeAsid64();
89  physAddrRange = system->physAddrRange();
90  haveSVE = system->haveSVE();
91  haveVHE = system->haveVHE();
92  havePAN = system->havePAN();
93  haveSecEL2 = system->haveSecEL2();
94  sveVL = system->sveVL();
95  haveLSE = system->haveLSE();
96  haveTME = system->haveTME();
97  } else {
98  highestELIs64 = true; // ArmSystem::highestELIs64 does the same
99  haveSecurity = haveLPAE = haveVirtualization = false;
100  haveCrypto = true;
101  haveLargeAsid64 = false;
102  physAddrRange = 32; // dummy value
103  haveSVE = true;
104  haveVHE = false;
105  havePAN = false;
106  haveSecEL2 = true;
107  sveVL = p->sve_vl_se;
108  haveLSE = true;
109  haveTME = true;
110  }
111 
112  // Initial rename mode depends on highestEL
113  const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
114  highestELIs64 ? Enums::Full : Enums::Elem;
115 
116  selfDebug = new SelfDebug();
117  initializeMiscRegMetadata();
118  preUnflattenMiscReg();
119 
120  clear();
121 }
122 
123 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
124 
125 const ArmISAParams *
126 ISA::params() const
127 {
128  return dynamic_cast<const Params *>(_params);
129 }
130 
131 void
132 ISA::clear()
133 {
134  const Params *p(params());
135 
136  // Invalidate cached copies of miscregs in the TLBs
137  if (tc) {
138  getITBPtr(tc)->invalidateMiscReg();
139  getDTBPtr(tc)->invalidateMiscReg();
140  }
141 
142  SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
143  memset(miscRegs, 0, sizeof(miscRegs));
144 
145  initID32(p);
146 
147  // We always initialize AArch64 ID registers even
148  // if we are in AArch32. This is done since if we
149  // are in SE mode we don't know if our ArmProcess is
150  // AArch32 or AArch64
151  initID64(p);
152 
153  // Start with an event in the mailbox
154  miscRegs[MISCREG_SEV_MAILBOX] = 1;
155 
156  // Separate Instruction and Data TLBs
157  miscRegs[MISCREG_TLBTR] = 1;
158 
159  MVFR0 mvfr0 = 0;
160  mvfr0.advSimdRegisters = 2;
161  mvfr0.singlePrecision = 2;
162  mvfr0.doublePrecision = 2;
163  mvfr0.vfpExceptionTrapping = 0;
164  mvfr0.divide = 1;
165  mvfr0.squareRoot = 1;
166  mvfr0.shortVectors = 1;
167  mvfr0.roundingModes = 1;
168  miscRegs[MISCREG_MVFR0] = mvfr0;
169 
170  MVFR1 mvfr1 = 0;
171  mvfr1.flushToZero = 1;
172  mvfr1.defaultNaN = 1;
173  mvfr1.advSimdLoadStore = 1;
174  mvfr1.advSimdInteger = 1;
175  mvfr1.advSimdSinglePrecision = 1;
176  mvfr1.advSimdHalfPrecision = 1;
177  mvfr1.vfpHalfPrecision = 1;
178  miscRegs[MISCREG_MVFR1] = mvfr1;
179 
180  // Reset values of PRRR and NMRR are implementation dependent
181 
182  // @todo: PRRR and NMRR in secure state?
183  miscRegs[MISCREG_PRRR_NS] =
184  (1 << 19) | // 19
185  (0 << 18) | // 18
186  (0 << 17) | // 17
187  (1 << 16) | // 16
188  (2 << 14) | // 15:14
189  (0 << 12) | // 13:12
190  (2 << 10) | // 11:10
191  (2 << 8) | // 9:8
192  (2 << 6) | // 7:6
193  (2 << 4) | // 5:4
194  (1 << 2) | // 3:2
195  0; // 1:0
196 
197  miscRegs[MISCREG_NMRR_NS] =
198  (1 << 30) | // 31:30
199  (0 << 26) | // 27:26
200  (0 << 24) | // 25:24
201  (3 << 22) | // 23:22
202  (2 << 20) | // 21:20
203  (0 << 18) | // 19:18
204  (0 << 16) | // 17:16
205  (1 << 14) | // 15:14
206  (0 << 12) | // 13:12
207  (2 << 10) | // 11:10
208  (0 << 8) | // 9:8
209  (3 << 6) | // 7:6
210  (2 << 4) | // 5:4
211  (0 << 2) | // 3:2
212  0; // 1:0
213 
214  if (FullSystem && system->highestELIs64()) {
215  // Initialize AArch64 state
216  clear64(p);
217  return;
218  }
219 
220  // Initialize AArch32 state...
221  clear32(p, sctlr_rst);
222 }
223 
224 void
225 ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
226 {
227  CPSR cpsr = 0;
228  cpsr.mode = MODE_USER;
229 
230  if (FullSystem) {
231  miscRegs[MISCREG_MVBAR] = system->resetAddr();
232  }
233 
234  miscRegs[MISCREG_CPSR] = cpsr;
235  updateRegMap(cpsr);
236 
237  SCTLR sctlr = 0;
238  sctlr.te = (bool) sctlr_rst.te;
239  sctlr.nmfi = (bool) sctlr_rst.nmfi;
240  sctlr.v = (bool) sctlr_rst.v;
241  sctlr.u = 1;
242  sctlr.xp = 1;
243  sctlr.rao2 = 1;
244  sctlr.rao3 = 1;
245  sctlr.rao4 = 0xf; // SCTLR[6:3]
246  sctlr.uci = 1;
247  sctlr.dze = 1;
248  miscRegs[MISCREG_SCTLR_NS] = sctlr;
249  miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
250  miscRegs[MISCREG_HCPTR] = 0;
251 
252  miscRegs[MISCREG_CPACR] = 0;
253 
254  miscRegs[MISCREG_FPSID] = p->fpsid;
255 
256  if (haveLPAE) {
257  TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
258  ttbcr.eae = 0;
259  miscRegs[MISCREG_TTBCR_NS] = ttbcr;
260  // Enforce consistency with system-level settings
261  miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
262  }
263 
264  if (haveSecurity) {
265  miscRegs[MISCREG_SCTLR_S] = sctlr;
266  miscRegs[MISCREG_SCR] = 0;
267  miscRegs[MISCREG_VBAR_S] = 0;
268  } else {
269  // we're always non-secure
270  miscRegs[MISCREG_SCR] = 1;
271  }
272 
273  //XXX We need to initialize the rest of the state.
274 }
275 
276 void
277 ISA::clear64(const ArmISAParams *p)
278 {
279  CPSR cpsr = 0;
280  Addr rvbar = system->resetAddr();
281  switch (system->highestEL()) {
282  // Set initial EL to highest implemented EL using associated stack
283  // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
284  // value
285  case EL3:
286  cpsr.mode = MODE_EL3H;
287  miscRegs[MISCREG_RVBAR_EL3] = rvbar;
288  break;
289  case EL2:
290  cpsr.mode = MODE_EL2H;
291  miscRegs[MISCREG_RVBAR_EL2] = rvbar;
292  break;
293  case EL1:
294  cpsr.mode = MODE_EL1H;
295  miscRegs[MISCREG_RVBAR_EL1] = rvbar;
296  break;
297  default:
298  panic("Invalid highest implemented exception level");
299  break;
300  }
301 
302  // Initialize rest of CPSR
303  cpsr.daif = 0xf; // Mask all interrupts
304  cpsr.ss = 0;
305  cpsr.il = 0;
306  miscRegs[MISCREG_CPSR] = cpsr;
307  updateRegMap(cpsr);
308 
309  // Initialize other control registers
310  miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
311  if (haveSecurity) {
312  miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
313  miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
314  } else if (haveVirtualization) {
315  // also MISCREG_SCTLR_EL2 (by mapping)
316  miscRegs[MISCREG_HSCTLR] = 0x30c50830;
317  } else {
318  // also MISCREG_SCTLR_EL1 (by mapping)
319  miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
320  // Always non-secure
321  miscRegs[MISCREG_SCR_EL3] = 1;
322  }
323 }
324 
325 void
326 ISA::initID32(const ArmISAParams *p)
327 {
328  // Initialize configurable default values
329 
330  uint32_t midr;
331  if (p->midr != 0x0)
332  midr = p->midr;
333  else if (highestELIs64)
334  // Cortex-A57 TRM r0p0 MIDR
335  midr = 0x410fd070;
336  else
337  // Cortex-A15 TRM r0p0 MIDR
338  midr = 0x410fc0f0;
339 
340  miscRegs[MISCREG_MIDR] = midr;
341  miscRegs[MISCREG_MIDR_EL1] = midr;
342  miscRegs[MISCREG_VPIDR] = midr;
343 
344  miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
345  miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
346  miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
347  miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
348  miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
349  miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
350 
351  miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
352  miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
353  miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
354  miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
355 
356  miscRegs[MISCREG_ID_ISAR5] = insertBits(
357  miscRegs[MISCREG_ID_ISAR5], 19, 4,
358  haveCrypto ? 0x1112 : 0x0);
359 }
360 
361 void
362 ISA::initID64(const ArmISAParams *p)
363 {
364  // Initialize configurable id registers
365  miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
366  miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
367  miscRegs[MISCREG_ID_AA64DFR0_EL1] =
368  (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
369  (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
370 
371  miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
372  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
373  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
374  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
375  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
376  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
377 
378  miscRegs[MISCREG_ID_DFR0_EL1] =
379  (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
380 
381  miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
382 
383  // SVE
384  miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
385  if (haveSecurity) {
386  miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
387  } else if (haveVirtualization) {
388  miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
389  } else {
390  miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
391  }
392 
393  // Enforce consistency with system-level settings...
394 
395  // EL3
396  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
397  miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
398  haveSecurity ? 0x2 : 0x0);
399  // EL2
400  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
401  miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
402  haveVirtualization ? 0x2 : 0x0);
403  // SVE
404  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
405  miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
406  haveSVE ? 0x1 : 0x0);
407  // SecEL2
408  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
409  miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
410  haveSecEL2 ? 0x1 : 0x0);
411  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
412  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 39, 36,
413  haveSecEL2 ? 0x1 : 0x0);
414  // Large ASID support
415  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
416  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
417  haveLargeAsid64 ? 0x2 : 0x0);
418  // Physical address size
419  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
420  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
421  encodePhysAddrRange64(physAddrRange));
422  // Crypto
423  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
424  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
425  haveCrypto ? 0x1112 : 0x0);
426  // LSE
427  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
428  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
429  haveLSE ? 0x2 : 0x0);
430  // VHE
431  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
432  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
433  haveVHE ? 0x1 : 0x0);
434  // PAN
435  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
436  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
437  havePAN ? 0x1 : 0x0);
438  // TME
439  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
440  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,
441  haveTME ? 0x1 : 0x0);
442 }
443 
444 void
445 ISA::startup()
446 {
447  BaseISA::startup();
448 
449  if (tc) {
450  setupThreadContext();
451 
452  if (haveTME) {
453  std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
454  tc->setHtmCheckpointPtr(std::move(cpt));
455  }
456  }
457 
458  afterStartup = true;
459 }
460 
461 void
462 ISA::setupThreadContext()
463 {
464  pmu->setThreadContext(tc);
465 
466  if (!system)
467  return;
468 
469  selfDebug->init(tc);
470 
471  Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
472  if (!gicv3)
473  return;
474 
475  if (!gicv3CpuInterface)
476  gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
477 
478  gicv3CpuInterface->setISA(this);
479  gicv3CpuInterface->setThreadContext(tc);
480 }
481 
482 void
483 ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
484 {
485  tc = new_tc;
486  setupThreadContext();
487 }
488 
489 RegVal
490 ISA::readMiscRegNoEffect(int misc_reg) const
491 {
492  assert(misc_reg < NumMiscRegs);
493 
494  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
495  const auto &map = getMiscIndices(misc_reg);
496  int lower = map.first, upper = map.second;
497  // NB!: apply architectural masks according to desired register,
498  // despite possibly getting value from different (mapped) register.
499  auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
500  |(miscRegs[upper] << 32));
501  if (val & reg.res0()) {
502  DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
503  miscRegName[misc_reg], val & reg.res0());
504  }
505  if ((val & reg.res1()) != reg.res1()) {
506  DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
507  miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
508  }
509  return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
510 }
511 
512 
513 RegVal
514 ISA::readMiscReg(int misc_reg)
515 {
516  CPSR cpsr = 0;
517  PCState pc = 0;
518  SCR scr = 0;
519 
520  if (misc_reg == MISCREG_CPSR) {
521  cpsr = miscRegs[misc_reg];
522  pc = tc->pcState();
523  cpsr.j = pc.jazelle() ? 1 : 0;
524  cpsr.t = pc.thumb() ? 1 : 0;
525  return cpsr;
526  }
527 
528 #ifndef NDEBUG
529  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
530  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
531  warn("Unimplemented system register %s read.\n",
532  miscRegName[misc_reg]);
533  else
534  panic("Unimplemented system register %s read.\n",
535  miscRegName[misc_reg]);
536  }
537 #endif
538  misc_reg = redirectRegVHE(tc, misc_reg);
539 
540  switch (unflattenMiscReg(misc_reg)) {
541  case MISCREG_HCR:
542  case MISCREG_HCR2:
543  if (!haveVirtualization)
544  return 0;
545  break;
546  case MISCREG_CPACR:
547  {
548  const uint32_t ones = (uint32_t)(-1);
549  CPACR cpacrMask = 0;
550  // Only cp10, cp11, and ase are implemented, nothing else should
551  // be readable? (straight copy from the write code)
552  cpacrMask.cp10 = ones;
553  cpacrMask.cp11 = ones;
554  cpacrMask.asedis = ones;
555 
556  // Security Extensions may limit the readability of CPACR
557  if (haveSecurity) {
558  scr = readMiscRegNoEffect(MISCREG_SCR);
559  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
560  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
561  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
562  // NB: Skipping the full loop, here
563  if (!nsacr.cp10) cpacrMask.cp10 = 0;
564  if (!nsacr.cp11) cpacrMask.cp11 = 0;
565  }
566  }
567  RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
568  val &= cpacrMask;
569  DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
570  miscRegName[misc_reg], val);
571  return val;
572  }
573  case MISCREG_MPIDR:
574  case MISCREG_MPIDR_EL1:
575  return readMPIDR(system, tc);
576  case MISCREG_VMPIDR:
577  case MISCREG_VMPIDR_EL2:
578  // top bit defined as RES1
579  return readMiscRegNoEffect(misc_reg) | 0x80000000;
580  case MISCREG_ID_AFR0: // not implemented, so alias MIDR
581  case MISCREG_REVIDR: // not implemented, so alias MIDR
582  case MISCREG_MIDR:
583  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
584  scr = readMiscRegNoEffect(MISCREG_SCR);
585  if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
586  return readMiscRegNoEffect(misc_reg);
587  } else {
588  return readMiscRegNoEffect(MISCREG_VPIDR);
589  }
590  break;
591  case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
592  case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
593  case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
594  case MISCREG_AIDR: // AUX ID set to 0
595  case MISCREG_TCMTR: // No TCM's
596  return 0;
597 
598  case MISCREG_CLIDR:
599  warn_once("The clidr register always reports 0 caches.\n");
600  warn_once("clidr LoUIS field of 0b001 to match current "
601  "ARM implementations.\n");
602  return 0x00200000;
603  case MISCREG_CCSIDR:
604  warn_once("The ccsidr register isn't implemented and "
605  "always reads as 0.\n");
606  break;
607  case MISCREG_CTR: // AArch32, ARMv7, top bit set
608  case MISCREG_CTR_EL0: // AArch64
609  {
610  //all caches have the same line size in gem5
611  //4 byte words in ARM
612  unsigned lineSizeWords =
613  tc->getSystemPtr()->cacheLineSize() / 4;
614  unsigned log2LineSizeWords = 0;
615 
616  while (lineSizeWords >>= 1) {
617  ++log2LineSizeWords;
618  }
619 
620  CTR ctr = 0;
621  //log2 of minimun i-cache line size (words)
622  ctr.iCacheLineSize = log2LineSizeWords;
623  //b11 - gem5 uses pipt
624  ctr.l1IndexPolicy = 0x3;
625  //log2 of minimum d-cache line size (words)
626  ctr.dCacheLineSize = log2LineSizeWords;
627  //log2 of max reservation size (words)
628  ctr.erg = log2LineSizeWords;
629  //log2 of max writeback size (words)
630  ctr.cwg = log2LineSizeWords;
631  //b100 - gem5 format is ARMv7
632  ctr.format = 0x4;
633 
634  return ctr;
635  }
636  case MISCREG_ACTLR:
637  warn("Not doing anything for miscreg ACTLR\n");
638  break;
639 
640  case MISCREG_PMXEVTYPER_PMCCFILTR:
641  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
642  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
643  case MISCREG_PMCR ... MISCREG_PMOVSSET:
644  return pmu->readMiscReg(misc_reg);
645 
646  case MISCREG_CPSR_Q:
647  panic("shouldn't be reading this register seperately\n");
648  case MISCREG_FPSCR_QC:
649  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
650  case MISCREG_FPSCR_EXC:
651  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
652  case MISCREG_FPSR:
653  {
654  const uint32_t ones = (uint32_t)(-1);
655  FPSCR fpscrMask = 0;
656  fpscrMask.ioc = ones;
657  fpscrMask.dzc = ones;
658  fpscrMask.ofc = ones;
659  fpscrMask.ufc = ones;
660  fpscrMask.ixc = ones;
661  fpscrMask.idc = ones;
662  fpscrMask.qc = ones;
663  fpscrMask.v = ones;
664  fpscrMask.c = ones;
665  fpscrMask.z = ones;
666  fpscrMask.n = ones;
667  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
668  }
669  case MISCREG_FPCR:
670  {
671  const uint32_t ones = (uint32_t)(-1);
672  FPSCR fpscrMask = 0;
673  fpscrMask.len = ones;
674  fpscrMask.fz16 = ones;
675  fpscrMask.stride = ones;
676  fpscrMask.rMode = ones;
677  fpscrMask.fz = ones;
678  fpscrMask.dn = ones;
679  fpscrMask.ahp = ones;
680  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
681  }
682  case MISCREG_NZCV:
683  {
684  CPSR cpsr = 0;
685  cpsr.nz = tc->readCCReg(CCREG_NZ);
686  cpsr.c = tc->readCCReg(CCREG_C);
687  cpsr.v = tc->readCCReg(CCREG_V);
688  return cpsr;
689  }
690  case MISCREG_DAIF:
691  {
692  CPSR cpsr = 0;
693  cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
694  return cpsr;
695  }
696  case MISCREG_SP_EL0:
697  {
698  return tc->readIntReg(INTREG_SP0);
699  }
700  case MISCREG_SP_EL1:
701  {
702  return tc->readIntReg(INTREG_SP1);
703  }
704  case MISCREG_SP_EL2:
705  {
706  return tc->readIntReg(INTREG_SP2);
707  }
708  case MISCREG_SPSEL:
709  {
710  return miscRegs[MISCREG_CPSR] & 0x1;
711  }
712  case MISCREG_CURRENTEL:
713  {
714  return miscRegs[MISCREG_CPSR] & 0xc;
715  }
716  case MISCREG_PAN:
717  {
718  return miscRegs[MISCREG_CPSR] & 0x400000;
719  }
720  case MISCREG_L2CTLR:
721  {
722  // mostly unimplemented, just set NumCPUs field from sim and return
723  L2CTLR l2ctlr = 0;
724  // b00:1CPU to b11:4CPUs
725  l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
726  return l2ctlr;
727  }
728  case MISCREG_DBGDIDR:
729  /* For now just implement the version number.
730  * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
731  */
732  return 0x5 << 16;
733  case MISCREG_DBGDSCRint:
734  return readMiscRegNoEffect(MISCREG_DBGDSCRint);
735  case MISCREG_ISR:
736  {
737  auto ic = dynamic_cast<ArmISA::Interrupts *>(
738  tc->getCpuPtr()->getInterruptController(tc->threadId()));
739  return ic->getISR(
740  readMiscRegNoEffect(MISCREG_HCR),
741  readMiscRegNoEffect(MISCREG_CPSR),
742  readMiscRegNoEffect(MISCREG_SCR));
743  }
744  case MISCREG_ISR_EL1:
745  {
746  auto ic = dynamic_cast<ArmISA::Interrupts *>(
747  tc->getCpuPtr()->getInterruptController(tc->threadId()));
748  return ic->getISR(
749  readMiscRegNoEffect(MISCREG_HCR_EL2),
750  readMiscRegNoEffect(MISCREG_CPSR),
751  readMiscRegNoEffect(MISCREG_SCR_EL3));
752  }
753  case MISCREG_DCZID_EL0:
754  return 0x04; // DC ZVA clear 64-byte chunks
755  case MISCREG_HCPTR:
756  {
757  RegVal val = readMiscRegNoEffect(misc_reg);
758  // The trap bit associated with CP14 is defined as RAZ
759  val &= ~(1 << 14);
760  // If a CP bit in NSACR is 0 then the corresponding bit in
761  // HCPTR is RAO/WI
762  bool secure_lookup = haveSecurity && isSecure(tc);
763  if (!secure_lookup) {
764  RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
765  val |= (mask ^ 0x7FFF) & 0xBFFF;
766  }
767  // Set the bits for unimplemented coprocessors to RAO/WI
768  val |= 0x33FF;
769  return (val);
770  }
771  case MISCREG_HDFAR: // alias for secure DFAR
772  return readMiscRegNoEffect(MISCREG_DFAR_S);
773  case MISCREG_HIFAR: // alias for secure IFAR
774  return readMiscRegNoEffect(MISCREG_IFAR_S);
775 
776  case MISCREG_ID_PFR0:
777  // !ThumbEE | !Jazelle | Thumb | ARM
778  return 0x00000031;
779  case MISCREG_ID_PFR1:
780  { // Timer | Virti | !M Profile | TrustZone | ARMv4
781  bool haveTimer = (system->getGenericTimer() != NULL);
782  return 0x00000001
783  | (haveSecurity ? 0x00000010 : 0x0)
784  | (haveVirtualization ? 0x00001000 : 0x0)
785  | (haveTimer ? 0x00010000 : 0x0);
786  }
787  case MISCREG_ID_AA64PFR0_EL1:
788  return 0x0000000000000002 | // AArch{64,32} supported at EL0
789  0x0000000000000020 | // EL1
790  (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
791  (haveSecurity ? 0x0000000000002000 : 0) | // EL3
792  (haveSVE ? 0x0000000100000000 : 0) | // SVE
793  (haveSecEL2 ? 0x0000001000000000 : 0) | // SecEL2
794  (gicv3CpuInterface ? 0x0000000001000000 : 0);
795  case MISCREG_ID_AA64PFR1_EL1:
796  return 0; // bits [63:0] RES0 (reserved for future use)
797 
798  // Generic Timer registers
799  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
800  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
801  return getGenericTimer().readMiscReg(misc_reg);
802 
803  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
804  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
805  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
806  return getGICv3CPUInterface().readMiscReg(misc_reg);
807 
808  default:
809  break;
810 
811  }
812  return readMiscRegNoEffect(misc_reg);
813 }
814 
815 void
816 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
817 {
818  assert(misc_reg < NumMiscRegs);
819 
820  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
821  const auto &map = getMiscIndices(misc_reg);
822  int lower = map.first, upper = map.second;
823 
824  auto v = (val & ~reg.wi()) | reg.rao();
825  if (upper > 0) {
826  miscRegs[lower] = bits(v, 31, 0);
827  miscRegs[upper] = bits(v, 63, 32);
828  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
829  miscRegName[misc_reg], misc_reg, lower, upper, v);
830  } else {
831  miscRegs[lower] = v;
832  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
833  miscRegName[misc_reg], misc_reg, lower, v);
834  }
835 }
836 
837 void
838 ISA::setMiscReg(int misc_reg, RegVal val)
839 {
840 
841  RegVal newVal = val;
842  bool secure_lookup;
843  SCR scr;
844 
845  if (misc_reg == MISCREG_CPSR) {
846  updateRegMap(val);
847 
848 
849  CPSR old_cpsr = miscRegs[MISCREG_CPSR];
850  int old_mode = old_cpsr.mode;
851  CPSR cpsr = val;
852  if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
853  getITBPtr(tc)->invalidateMiscReg();
854  getDTBPtr(tc)->invalidateMiscReg();
855  }
856 
857  if (cpsr.pan != old_cpsr.pan) {
858  getDTBPtr(tc)->invalidateMiscReg();
859  }
860 
861  DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
862  miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
863  PCState pc = tc->pcState();
864  pc.nextThumb(cpsr.t);
865  pc.nextJazelle(cpsr.j);
866  pc.illegalExec(cpsr.il == 1);
867  selfDebug->setDebugMask(cpsr.d == 1);
868 
869  tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
870 
871  // Follow slightly different semantics if a CheckerCPU object
872  // is connected
873  CheckerCPU *checker = tc->getCheckerCpuPtr();
874  if (checker) {
875  tc->pcStateNoRecord(pc);
876  } else {
877  tc->pcState(pc);
878  }
879  } else {
880 #ifndef NDEBUG
881  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
882  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
883  warn("Unimplemented system register %s write with %#x.\n",
884  miscRegName[misc_reg], val);
885  else
886  panic("Unimplemented system register %s write with %#x.\n",
887  miscRegName[misc_reg], val);
888  }
889 #endif
890  misc_reg = redirectRegVHE(tc, misc_reg);
891 
892  switch (unflattenMiscReg(misc_reg)) {
893  case MISCREG_CPACR:
894  {
895 
896  const uint32_t ones = (uint32_t)(-1);
897  CPACR cpacrMask = 0;
898  // Only cp10, cp11, and ase are implemented, nothing else should
899  // be writable
900  cpacrMask.cp10 = ones;
901  cpacrMask.cp11 = ones;
902  cpacrMask.asedis = ones;
903 
904  // Security Extensions may limit the writability of CPACR
905  if (haveSecurity) {
906  scr = readMiscRegNoEffect(MISCREG_SCR);
907  CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
908  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
909  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
910  // NB: Skipping the full loop, here
911  if (!nsacr.cp10) cpacrMask.cp10 = 0;
912  if (!nsacr.cp11) cpacrMask.cp11 = 0;
913  }
914  }
915 
916  RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
917  newVal &= cpacrMask;
918  newVal |= old_val & ~cpacrMask;
919  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
920  miscRegName[misc_reg], newVal);
921  }
922  break;
923  case MISCREG_CPACR_EL1:
924  {
925  const uint32_t ones = (uint32_t)(-1);
926  CPACR cpacrMask = 0;
927  cpacrMask.tta = ones;
928  cpacrMask.fpen = ones;
929  if (haveSVE) {
930  cpacrMask.zen = ones;
931  }
932  newVal &= cpacrMask;
933  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
934  miscRegName[misc_reg], newVal);
935  }
936  break;
937  case MISCREG_CPTR_EL2:
938  {
939  const uint32_t ones = (uint32_t)(-1);
940  CPTR cptrMask = 0;
941  cptrMask.tcpac = ones;
942  cptrMask.tta = ones;
943  cptrMask.tfp = ones;
944  if (haveSVE) {
945  cptrMask.tz = ones;
946  }
947  newVal &= cptrMask;
948  cptrMask = 0;
949  cptrMask.res1_13_12_el2 = ones;
950  cptrMask.res1_7_0_el2 = ones;
951  if (!haveSVE) {
952  cptrMask.res1_8_el2 = ones;
953  }
954  cptrMask.res1_9_el2 = ones;
955  newVal |= cptrMask;
956  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
957  miscRegName[misc_reg], newVal);
958  }
959  break;
960  case MISCREG_CPTR_EL3:
961  {
962  const uint32_t ones = (uint32_t)(-1);
963  CPTR cptrMask = 0;
964  cptrMask.tcpac = ones;
965  cptrMask.tta = ones;
966  cptrMask.tfp = ones;
967  if (haveSVE) {
968  cptrMask.ez = ones;
969  }
970  newVal &= cptrMask;
971  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
972  miscRegName[misc_reg], newVal);
973  }
974  break;
975  case MISCREG_CSSELR:
976  warn_once("The csselr register isn't implemented.\n");
977  return;
978 
979  case MISCREG_DC_ZVA_Xt:
980  warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
981  return;
982 
983  case MISCREG_FPSCR:
984  {
985  const uint32_t ones = (uint32_t)(-1);
986  FPSCR fpscrMask = 0;
987  fpscrMask.ioc = ones;
988  fpscrMask.dzc = ones;
989  fpscrMask.ofc = ones;
990  fpscrMask.ufc = ones;
991  fpscrMask.ixc = ones;
992  fpscrMask.idc = ones;
993  fpscrMask.ioe = ones;
994  fpscrMask.dze = ones;
995  fpscrMask.ofe = ones;
996  fpscrMask.ufe = ones;
997  fpscrMask.ixe = ones;
998  fpscrMask.ide = ones;
999  fpscrMask.len = ones;
1000  fpscrMask.fz16 = ones;
1001  fpscrMask.stride = ones;
1002  fpscrMask.rMode = ones;
1003  fpscrMask.fz = ones;
1004  fpscrMask.dn = ones;
1005  fpscrMask.ahp = ones;
1006  fpscrMask.qc = ones;
1007  fpscrMask.v = ones;
1008  fpscrMask.c = ones;
1009  fpscrMask.z = ones;
1010  fpscrMask.n = ones;
1011  newVal = (newVal & (uint32_t)fpscrMask) |
1012  (readMiscRegNoEffect(MISCREG_FPSCR) &
1013  ~(uint32_t)fpscrMask);
1014  tc->getDecoderPtr()->setContext(newVal);
1015  }
1016  break;
1017  case MISCREG_FPSR:
1018  {
1019  const uint32_t ones = (uint32_t)(-1);
1020  FPSCR fpscrMask = 0;
1021  fpscrMask.ioc = ones;
1022  fpscrMask.dzc = ones;
1023  fpscrMask.ofc = ones;
1024  fpscrMask.ufc = ones;
1025  fpscrMask.ixc = ones;
1026  fpscrMask.idc = ones;
1027  fpscrMask.qc = ones;
1028  fpscrMask.v = ones;
1029  fpscrMask.c = ones;
1030  fpscrMask.z = ones;
1031  fpscrMask.n = ones;
1032  newVal = (newVal & (uint32_t)fpscrMask) |
1033  (readMiscRegNoEffect(MISCREG_FPSCR) &
1034  ~(uint32_t)fpscrMask);
1035  misc_reg = MISCREG_FPSCR;
1036  }
1037  break;
1038  case MISCREG_FPCR:
1039  {
1040  const uint32_t ones = (uint32_t)(-1);
1041  FPSCR fpscrMask = 0;
1042  fpscrMask.len = ones;
1043  fpscrMask.fz16 = ones;
1044  fpscrMask.stride = ones;
1045  fpscrMask.rMode = ones;
1046  fpscrMask.fz = ones;
1047  fpscrMask.dn = ones;
1048  fpscrMask.ahp = ones;
1049  newVal = (newVal & (uint32_t)fpscrMask) |
1050  (readMiscRegNoEffect(MISCREG_FPSCR) &
1051  ~(uint32_t)fpscrMask);
1052  misc_reg = MISCREG_FPSCR;
1053  }
1054  break;
1055  case MISCREG_CPSR_Q:
1056  {
1057  assert(!(newVal & ~CpsrMaskQ));
1058  newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1059  misc_reg = MISCREG_CPSR;
1060  }
1061  break;
1062  case MISCREG_FPSCR_QC:
1063  {
1064  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1065  (newVal & FpscrQcMask);
1066  misc_reg = MISCREG_FPSCR;
1067  }
1068  break;
1069  case MISCREG_FPSCR_EXC:
1070  {
1071  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1072  (newVal & FpscrExcMask);
1073  misc_reg = MISCREG_FPSCR;
1074  }
1075  break;
1076  case MISCREG_FPEXC:
1077  {
1078  // vfpv3 architecture, section B.6.1 of DDI04068
1079  // bit 29 - valid only if fpexc[31] is 0
1080  const uint32_t fpexcMask = 0x60000000;
1081  newVal = (newVal & fpexcMask) |
1082  (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1083  }
1084  break;
1085  case MISCREG_HCR2:
1086  if (!haveVirtualization)
1087  return;
1088  break;
1089  case MISCREG_HCR:
1090  {
1091  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1092  selfDebug->setenableTDETGE((HCR)val, mdcr);
1093  if (!haveVirtualization)
1094  return;
1095  }
1096  break;
1097 
1098  case MISCREG_HDCR:
1099  {
1100  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1101  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1102  }
1103  break;
1104  case MISCREG_DBGOSLAR:
1105  {
1106  OSL r = tc->readMiscReg(MISCREG_DBGOSLSR);
1107  const uint32_t temp = (val == 0xC5ACCE55)? 0x1 : 0x0;
1108  selfDebug->updateOSLock((RegVal) temp);
1109  r.oslk = bits(temp,0);
1110  tc->setMiscReg(MISCREG_DBGOSLSR, r);
1111  }
1112  break;
1113  case MISCREG_DBGBCR0:
1114  selfDebug->updateDBGBCR(0, val);
1115  break;
1116  case MISCREG_DBGBCR1:
1117  selfDebug->updateDBGBCR(1, val);
1118  break;
1119  case MISCREG_DBGBCR2:
1120  selfDebug->updateDBGBCR(2, val);
1121  break;
1122  case MISCREG_DBGBCR3:
1123  selfDebug->updateDBGBCR(3, val);
1124  break;
1125  case MISCREG_DBGBCR4:
1126  selfDebug->updateDBGBCR(4, val);
1127  break;
1128  case MISCREG_DBGBCR5:
1129  selfDebug->updateDBGBCR(5, val);
1130  break;
1131  case MISCREG_DBGBCR6:
1132  selfDebug->updateDBGBCR(6, val);
1133  break;
1134  case MISCREG_DBGBCR7:
1135  selfDebug->updateDBGBCR(7, val);
1136  break;
1137  case MISCREG_DBGBCR8:
1138  selfDebug->updateDBGBCR(8, val);
1139  break;
1140  case MISCREG_DBGBCR9:
1141  selfDebug->updateDBGBCR(9, val);
1142  break;
1143  case MISCREG_DBGBCR10:
1144  selfDebug->updateDBGBCR(10, val);
1145  break;
1146  case MISCREG_DBGBCR11:
1147  selfDebug->updateDBGBCR(11, val);
1148  break;
1149  case MISCREG_DBGBCR12:
1150  selfDebug->updateDBGBCR(12, val);
1151  break;
1152  case MISCREG_DBGBCR13:
1153  selfDebug->updateDBGBCR(13, val);
1154  break;
1155  case MISCREG_DBGBCR14:
1156  selfDebug->updateDBGBCR(14, val);
1157  break;
1158  case MISCREG_DBGBCR15:
1159  selfDebug->updateDBGBCR(15, val);
1160  break;
1161  case MISCREG_DBGWCR0:
1162  selfDebug->updateDBGWCR(0, val);
1163  break;
1164  case MISCREG_DBGWCR1:
1165  selfDebug->updateDBGWCR(1, val);
1166  break;
1167  case MISCREG_DBGWCR2:
1168  selfDebug->updateDBGWCR(2, val);
1169  break;
1170  case MISCREG_DBGWCR3:
1171  selfDebug->updateDBGWCR(3, val);
1172  break;
1173  case MISCREG_DBGWCR4:
1174  selfDebug->updateDBGWCR(4, val);
1175  break;
1176  case MISCREG_DBGWCR5:
1177  selfDebug->updateDBGWCR(5, val);
1178  break;
1179  case MISCREG_DBGWCR6:
1180  selfDebug->updateDBGWCR(6, val);
1181  break;
1182  case MISCREG_DBGWCR7:
1183  selfDebug->updateDBGWCR(7, val);
1184  break;
1185  case MISCREG_DBGWCR8:
1186  selfDebug->updateDBGWCR(8, val);
1187  break;
1188  case MISCREG_DBGWCR9:
1189  selfDebug->updateDBGWCR(9, val);
1190  break;
1191  case MISCREG_DBGWCR10:
1192  selfDebug->updateDBGWCR(10, val);
1193  break;
1194  case MISCREG_DBGWCR11:
1195  selfDebug->updateDBGWCR(11, val);
1196  break;
1197  case MISCREG_DBGWCR12:
1198  selfDebug->updateDBGWCR(12, val);
1199  break;
1200  case MISCREG_DBGWCR13:
1201  selfDebug->updateDBGWCR(13, val);
1202  break;
1203  case MISCREG_DBGWCR14:
1204  selfDebug->updateDBGWCR(14, val);
1205  break;
1206  case MISCREG_DBGWCR15:
1207  selfDebug->updateDBGWCR(15, val);
1208  break;
1209 
1210  case MISCREG_MDCR_EL2:
1211  {
1212  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1213  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1214  }
1215  break;
1216  case MISCREG_SDCR:
1217  case MISCREG_MDCR_EL3:
1218  {
1219  selfDebug->setbSDD(val);
1220  }
1221  break;
1222  case MISCREG_DBGDSCRext:
1223  {
1224  selfDebug->setMDBGen(val);
1225  DBGDS32 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1226  DBGDS32 v = val;
1227  r.moe = v.moe;
1228  r.udccdis = v.udccdis;
1229  r.mdbgen = v.mdbgen;
1230  tc->setMiscReg(MISCREG_DBGDSCRint, r);
1231  r = tc->readMiscReg(MISCREG_DBGDSCRint);
1232  }
1233 
1234  break;
1235  case MISCREG_MDSCR_EL1:
1236  {
1237  selfDebug->setMDSCRvals(val);
1238  }
1239  break;
1240 
1241  case MISCREG_OSLAR_EL1:
1242  {
1243  selfDebug->updateOSLock(val);
1244  OSL r = tc->readMiscReg(MISCREG_OSLSR_EL1);
1245  r.oslk = bits(val, 0);
1246  r.oslm_3 = 1;
1247  tc->setMiscReg(MISCREG_OSLSR_EL1, r);
1248  }
1249  break;
1250 
1251  case MISCREG_DBGBCR0_EL1:
1252  selfDebug->updateDBGBCR(0, val);
1253  break;
1254  case MISCREG_DBGBCR1_EL1:
1255  selfDebug->updateDBGBCR(1, val);
1256  break;
1257  case MISCREG_DBGBCR2_EL1:
1258  selfDebug->updateDBGBCR(2, val);
1259  break;
1260  case MISCREG_DBGBCR3_EL1:
1261  selfDebug->updateDBGBCR(3, val);
1262  break;
1263  case MISCREG_DBGBCR4_EL1:
1264  selfDebug->updateDBGBCR(4, val);
1265  break;
1266  case MISCREG_DBGBCR5_EL1:
1267  selfDebug->updateDBGBCR(5, val);
1268  break;
1269  case MISCREG_DBGBCR6_EL1:
1270  selfDebug->updateDBGBCR(6, val);
1271  break;
1272  case MISCREG_DBGBCR7_EL1:
1273  selfDebug->updateDBGBCR(7, val);
1274  break;
1275  case MISCREG_DBGBCR8_EL1:
1276  selfDebug->updateDBGBCR(8, val);
1277  break;
1278  case MISCREG_DBGBCR9_EL1:
1279  selfDebug->updateDBGBCR(9, val);
1280  break;
1281  case MISCREG_DBGBCR10_EL1:
1282  selfDebug->updateDBGBCR(10, val);
1283  break;
1284  case MISCREG_DBGBCR11_EL1:
1285  selfDebug->updateDBGBCR(11, val);
1286  break;
1287  case MISCREG_DBGBCR12_EL1:
1288  selfDebug->updateDBGBCR(12, val);
1289  break;
1290  case MISCREG_DBGBCR13_EL1:
1291  selfDebug->updateDBGBCR(13, val);
1292  break;
1293  case MISCREG_DBGBCR14_EL1:
1294  selfDebug->updateDBGBCR(14, val);
1295  break;
1296  case MISCREG_DBGBCR15_EL1:
1297  selfDebug->updateDBGBCR(15, val);
1298  break;
1299  case MISCREG_DBGWCR0_EL1:
1300  selfDebug->updateDBGWCR(0, val);
1301  break;
1302  case MISCREG_DBGWCR1_EL1:
1303  selfDebug->updateDBGWCR(1, val);
1304  break;
1305  case MISCREG_DBGWCR2_EL1:
1306  selfDebug->updateDBGWCR(2, val);
1307  break;
1308  case MISCREG_DBGWCR3_EL1:
1309  selfDebug->updateDBGWCR(3, val);
1310  break;
1311  case MISCREG_DBGWCR4_EL1:
1312  selfDebug->updateDBGWCR(4, val);
1313  break;
1314  case MISCREG_DBGWCR5_EL1:
1315  selfDebug->updateDBGWCR(5, val);
1316  break;
1317  case MISCREG_DBGWCR6_EL1:
1318  selfDebug->updateDBGWCR(6, val);
1319  break;
1320  case MISCREG_DBGWCR7_EL1:
1321  selfDebug->updateDBGWCR(7, val);
1322  break;
1323  case MISCREG_DBGWCR8_EL1:
1324  selfDebug->updateDBGWCR(8, val);
1325  break;
1326  case MISCREG_DBGWCR9_EL1:
1327  selfDebug->updateDBGWCR(9, val);
1328  break;
1329  case MISCREG_DBGWCR10_EL1:
1330  selfDebug->updateDBGWCR(10, val);
1331  break;
1332  case MISCREG_DBGWCR11_EL1:
1333  selfDebug->updateDBGWCR(11, val);
1334  break;
1335  case MISCREG_DBGWCR12_EL1:
1336  selfDebug->updateDBGWCR(12, val);
1337  break;
1338  case MISCREG_DBGWCR13_EL1:
1339  selfDebug->updateDBGWCR(13, val);
1340  break;
1341  case MISCREG_DBGWCR14_EL1:
1342  selfDebug->updateDBGWCR(14, val);
1343  break;
1344  case MISCREG_DBGWCR15_EL1:
1345  selfDebug->updateDBGWCR(15, val);
1346  break;
1347  case MISCREG_IFSR:
1348  {
1349  // ARM ARM (ARM DDI 0406C.b) B4.1.96
1350  const uint32_t ifsrMask =
1351  mask(31, 13) | mask(11, 11) | mask(8, 6);
1352  newVal = newVal & ~ifsrMask;
1353  }
1354  break;
1355  case MISCREG_DFSR:
1356  {
1357  // ARM ARM (ARM DDI 0406C.b) B4.1.52
1358  const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1359  newVal = newVal & ~dfsrMask;
1360  }
1361  break;
1362  case MISCREG_AMAIR0:
1363  case MISCREG_AMAIR1:
1364  {
1365  // ARM ARM (ARM DDI 0406C.b) B4.1.5
1366  // Valid only with LPAE
1367  if (!haveLPAE)
1368  return;
1369  DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1370  }
1371  break;
1372  case MISCREG_SCR:
1373  getITBPtr(tc)->invalidateMiscReg();
1374  getDTBPtr(tc)->invalidateMiscReg();
1375  break;
1376  case MISCREG_SCTLR:
1377  {
1378  DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1379  scr = readMiscRegNoEffect(MISCREG_SCR);
1380 
1381  MiscRegIndex sctlr_idx;
1382  if (haveSecurity && !highestELIs64 && !scr.ns) {
1383  sctlr_idx = MISCREG_SCTLR_S;
1384  } else {
1385  sctlr_idx = MISCREG_SCTLR_NS;
1386  }
1387 
1388  SCTLR sctlr = miscRegs[sctlr_idx];
1389  SCTLR new_sctlr = newVal;
1390  new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1391  miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1392  getITBPtr(tc)->invalidateMiscReg();
1393  getDTBPtr(tc)->invalidateMiscReg();
1394  }
1395  case MISCREG_MIDR:
1396  case MISCREG_ID_PFR0:
1397  case MISCREG_ID_PFR1:
1398  case MISCREG_ID_DFR0:
1399  case MISCREG_ID_MMFR0:
1400  case MISCREG_ID_MMFR1:
1401  case MISCREG_ID_MMFR2:
1402  case MISCREG_ID_MMFR3:
1403  case MISCREG_ID_ISAR0:
1404  case MISCREG_ID_ISAR1:
1405  case MISCREG_ID_ISAR2:
1406  case MISCREG_ID_ISAR3:
1407  case MISCREG_ID_ISAR4:
1408  case MISCREG_ID_ISAR5:
1409 
1410  case MISCREG_MPIDR:
1411  case MISCREG_FPSID:
1412  case MISCREG_TLBTR:
1413  case MISCREG_MVFR0:
1414  case MISCREG_MVFR1:
1415 
1416  case MISCREG_ID_AA64AFR0_EL1:
1417  case MISCREG_ID_AA64AFR1_EL1:
1418  case MISCREG_ID_AA64DFR0_EL1:
1419  case MISCREG_ID_AA64DFR1_EL1:
1420  case MISCREG_ID_AA64ISAR0_EL1:
1421  case MISCREG_ID_AA64ISAR1_EL1:
1422  case MISCREG_ID_AA64MMFR0_EL1:
1423  case MISCREG_ID_AA64MMFR1_EL1:
1424  case MISCREG_ID_AA64MMFR2_EL1:
1425  case MISCREG_ID_AA64PFR0_EL1:
1426  case MISCREG_ID_AA64PFR1_EL1:
1427  // ID registers are constants.
1428  return;
1429 
1430  // TLB Invalidate All
1431  case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1432  {
1433  assert32();
1434  scr = readMiscReg(MISCREG_SCR);
1435 
1436  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1437  tlbiOp(tc);
1438  return;
1439  }
1440  // TLB Invalidate All, Inner Shareable
1441  case MISCREG_TLBIALLIS:
1442  {
1443  assert32();
1444  scr = readMiscReg(MISCREG_SCR);
1445 
1446  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1447  tlbiOp.broadcast(tc);
1448  return;
1449  }
1450  // Instruction TLB Invalidate All
1451  case MISCREG_ITLBIALL:
1452  {
1453  assert32();
1454  scr = readMiscReg(MISCREG_SCR);
1455 
1456  ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1457  tlbiOp(tc);
1458  return;
1459  }
1460  // Data TLB Invalidate All
1461  case MISCREG_DTLBIALL:
1462  {
1463  assert32();
1464  scr = readMiscReg(MISCREG_SCR);
1465 
1466  DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1467  tlbiOp(tc);
1468  return;
1469  }
1470  // TLB Invalidate by VA
1471  // mcr tlbimval(is) is invalidating all matching entries
1472  // regardless of the level of lookup, since in gem5 we cache
1473  // in the tlb the last level of lookup only.
1474  case MISCREG_TLBIMVA:
1475  case MISCREG_TLBIMVAL:
1476  {
1477  assert32();
1478  scr = readMiscReg(MISCREG_SCR);
1479 
1480  TLBIMVA tlbiOp(EL1,
1481  haveSecurity && !scr.ns,
1482  mbits(newVal, 31, 12),
1483  bits(newVal, 7,0));
1484 
1485  tlbiOp(tc);
1486  return;
1487  }
1488  // TLB Invalidate by VA, Inner Shareable
1489  case MISCREG_TLBIMVAIS:
1490  case MISCREG_TLBIMVALIS:
1491  {
1492  assert32();
1493  scr = readMiscReg(MISCREG_SCR);
1494 
1495  TLBIMVA tlbiOp(EL1,
1496  haveSecurity && !scr.ns,
1497  mbits(newVal, 31, 12),
1498  bits(newVal, 7,0));
1499 
1500  tlbiOp.broadcast(tc);
1501  return;
1502  }
1503  // TLB Invalidate by ASID match
1504  case MISCREG_TLBIASID:
1505  {
1506  assert32();
1507  scr = readMiscReg(MISCREG_SCR);
1508 
1509  TLBIASID tlbiOp(EL1,
1510  haveSecurity && !scr.ns,
1511  bits(newVal, 7,0));
1512 
1513  tlbiOp(tc);
1514  return;
1515  }
1516  // TLB Invalidate by ASID match, Inner Shareable
1517  case MISCREG_TLBIASIDIS:
1518  {
1519  assert32();
1520  scr = readMiscReg(MISCREG_SCR);
1521 
1522  TLBIASID tlbiOp(EL1,
1523  haveSecurity && !scr.ns,
1524  bits(newVal, 7,0));
1525 
1526  tlbiOp.broadcast(tc);
1527  return;
1528  }
1529  // mcr tlbimvaal(is) is invalidating all matching entries
1530  // regardless of the level of lookup, since in gem5 we cache
1531  // in the tlb the last level of lookup only.
1532  // TLB Invalidate by VA, All ASID
1533  case MISCREG_TLBIMVAA:
1534  case MISCREG_TLBIMVAAL:
1535  {
1536  assert32();
1537  scr = readMiscReg(MISCREG_SCR);
1538 
1539  TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1540  mbits(newVal, 31,12));
1541 
1542  tlbiOp(tc);
1543  return;
1544  }
1545  // TLB Invalidate by VA, All ASID, Inner Shareable
1546  case MISCREG_TLBIMVAAIS:
1547  case MISCREG_TLBIMVAALIS:
1548  {
1549  assert32();
1550  scr = readMiscReg(MISCREG_SCR);
1551 
1552  TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1553  mbits(newVal, 31,12));
1554 
1555  tlbiOp.broadcast(tc);
1556  return;
1557  }
1558  // mcr tlbimvalh(is) is invalidating all matching entries
1559  // regardless of the level of lookup, since in gem5 we cache
1560  // in the tlb the last level of lookup only.
1561  // TLB Invalidate by VA, Hyp mode
1562  case MISCREG_TLBIMVAH:
1563  case MISCREG_TLBIMVALH:
1564  {
1565  assert32();
1566  scr = readMiscReg(MISCREG_SCR);
1567 
1568  TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1569  mbits(newVal, 31,12));
1570 
1571  tlbiOp(tc);
1572  return;
1573  }
1574  // TLB Invalidate by VA, Hyp mode, Inner Shareable
1575  case MISCREG_TLBIMVAHIS:
1576  case MISCREG_TLBIMVALHIS:
1577  {
1578  assert32();
1579  scr = readMiscReg(MISCREG_SCR);
1580 
1581  TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1582  mbits(newVal, 31,12));
1583 
1584  tlbiOp.broadcast(tc);
1585  return;
1586  }
1587  // mcr tlbiipas2l(is) is invalidating all matching entries
1588  // regardless of the level of lookup, since in gem5 we cache
1589  // in the tlb the last level of lookup only.
1590  // TLB Invalidate by Intermediate Physical Address, Stage 2
1591  case MISCREG_TLBIIPAS2:
1592  case MISCREG_TLBIIPAS2L:
1593  {
1594  assert32();
1595  scr = readMiscReg(MISCREG_SCR);
1596 
1597  TLBIIPA tlbiOp(EL1,
1598  haveSecurity && !scr.ns,
1599  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1600 
1601  tlbiOp(tc);
1602  return;
1603  }
1604  // TLB Invalidate by Intermediate Physical Address, Stage 2,
1605  // Inner Shareable
1606  case MISCREG_TLBIIPAS2IS:
1607  case MISCREG_TLBIIPAS2LIS:
1608  {
1609  assert32();
1610  scr = readMiscReg(MISCREG_SCR);
1611 
1612  TLBIIPA tlbiOp(EL1,
1613  haveSecurity && !scr.ns,
1614  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1615 
1616  tlbiOp.broadcast(tc);
1617  return;
1618  }
1619  // Instruction TLB Invalidate by VA
1620  case MISCREG_ITLBIMVA:
1621  {
1622  assert32();
1623  scr = readMiscReg(MISCREG_SCR);
1624 
1625  ITLBIMVA tlbiOp(EL1,
1626  haveSecurity && !scr.ns,
1627  mbits(newVal, 31, 12),
1628  bits(newVal, 7,0));
1629 
1630  tlbiOp(tc);
1631  return;
1632  }
1633  // Data TLB Invalidate by VA
1634  case MISCREG_DTLBIMVA:
1635  {
1636  assert32();
1637  scr = readMiscReg(MISCREG_SCR);
1638 
1639  DTLBIMVA tlbiOp(EL1,
1640  haveSecurity && !scr.ns,
1641  mbits(newVal, 31, 12),
1642  bits(newVal, 7,0));
1643 
1644  tlbiOp(tc);
1645  return;
1646  }
1647  // Instruction TLB Invalidate by ASID match
1648  case MISCREG_ITLBIASID:
1649  {
1650  assert32();
1651  scr = readMiscReg(MISCREG_SCR);
1652 
1653  ITLBIASID tlbiOp(EL1,
1654  haveSecurity && !scr.ns,
1655  bits(newVal, 7,0));
1656 
1657  tlbiOp(tc);
1658  return;
1659  }
1660  // Data TLB Invalidate by ASID match
1661  case MISCREG_DTLBIASID:
1662  {
1663  assert32();
1664  scr = readMiscReg(MISCREG_SCR);
1665 
1666  DTLBIASID tlbiOp(EL1,
1667  haveSecurity && !scr.ns,
1668  bits(newVal, 7,0));
1669 
1670  tlbiOp(tc);
1671  return;
1672  }
1673  // TLB Invalidate All, Non-Secure Non-Hyp
1674  case MISCREG_TLBIALLNSNH:
1675  {
1676  assert32();
1677 
1678  TLBIALLN tlbiOp(EL1);
1679  tlbiOp(tc);
1680  return;
1681  }
1682  // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1683  case MISCREG_TLBIALLNSNHIS:
1684  {
1685  assert32();
1686 
1687  TLBIALLN tlbiOp(EL1);
1688  tlbiOp.broadcast(tc);
1689  return;
1690  }
1691  // TLB Invalidate All, Hyp mode
1692  case MISCREG_TLBIALLH:
1693  {
1694  assert32();
1695 
1696  TLBIALLN tlbiOp(EL2);
1697  tlbiOp(tc);
1698  return;
1699  }
1700  // TLB Invalidate All, Hyp mode, Inner Shareable
1701  case MISCREG_TLBIALLHIS:
1702  {
1703  assert32();
1704 
1705  TLBIALLN tlbiOp(EL2);
1706  tlbiOp.broadcast(tc);
1707  return;
1708  }
1709  // AArch64 TLB Invalidate All, EL3
1710  case MISCREG_TLBI_ALLE3:
1711  {
1712  assert64();
1713 
1714  TLBIALL tlbiOp(EL3, true);
1715  tlbiOp(tc);
1716  return;
1717  }
1718  // AArch64 TLB Invalidate All, EL3, Inner Shareable
1719  case MISCREG_TLBI_ALLE3IS:
1720  {
1721  assert64();
1722 
1723  TLBIALL tlbiOp(EL3, true);
1724  tlbiOp.broadcast(tc);
1725  return;
1726  }
1727  // AArch64 TLB Invalidate All, EL2, Inner Shareable
1728  case MISCREG_TLBI_ALLE2:
1729  case MISCREG_TLBI_ALLE2IS:
1730  {
1731  assert64();
1732  scr = readMiscReg(MISCREG_SCR);
1733 
1734  TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
1735  tlbiOp(tc);
1736  return;
1737  }
1738  // AArch64 TLB Invalidate All, EL1
1739  case MISCREG_TLBI_ALLE1:
1740  case MISCREG_TLBI_VMALLS12E1:
1741  // @todo: handle VMID and stage 2 to enable Virtualization
1742  {
1743  assert64();
1744  scr = readMiscReg(MISCREG_SCR);
1745 
1746  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1747  tlbiOp(tc);
1748  return;
1749  }
1750  case MISCREG_TLBI_VMALLE1:
1751  // @todo: handle VMID and stage 2 to enable Virtualization
1752  {
1753  assert64();
1754  scr = readMiscReg(MISCREG_SCR);
1755 
1756  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1757  bool is_host = (hcr.tge && hcr.e2h);
1758  ExceptionLevel target_el = is_host ? EL2 : EL1;
1759  TLBIALL tlbiOp(target_el, haveSecurity && !scr.ns);
1760  tlbiOp(tc);
1761  return;
1762  }
1763  // AArch64 TLB Invalidate All, EL1, Inner Shareable
1764  case MISCREG_TLBI_ALLE1IS:
1765  case MISCREG_TLBI_VMALLS12E1IS:
1766  // @todo: handle VMID and stage 2 to enable Virtualization
1767  {
1768  assert64();
1769  scr = readMiscReg(MISCREG_SCR);
1770 
1771  TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1772  tlbiOp.broadcast(tc);
1773  return;
1774  }
1775  case MISCREG_TLBI_VMALLE1IS:
1776  // @todo: handle VMID and stage 2 to enable Virtualization
1777  {
1778  assert64();
1779  scr = readMiscReg(MISCREG_SCR);
1780 
1781  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1782  bool is_host = (hcr.tge && hcr.e2h);
1783  ExceptionLevel target_el = is_host ? EL2 : EL1;
1784  TLBIALL tlbiOp(target_el, haveSecurity && !scr.ns);
1785  tlbiOp.broadcast(tc);
1786  return;
1787  }
1788  // VAEx(IS) and VALEx(IS) are the same because TLBs
1789  // only store entries
1790  // from the last level of translation table walks
1791  // @todo: handle VMID to enable Virtualization
1792  // AArch64 TLB Invalidate by VA, EL3
1793  case MISCREG_TLBI_VAE3_Xt:
1794  case MISCREG_TLBI_VALE3_Xt:
1795  {
1796  assert64();
1797 
1798  TLBIMVA tlbiOp(EL3, true,
1799  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1800  0xbeef);
1801  tlbiOp(tc);
1802  return;
1803  }
1804  // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1805  case MISCREG_TLBI_VAE3IS_Xt:
1806  case MISCREG_TLBI_VALE3IS_Xt:
1807  {
1808  assert64();
1809 
1810  TLBIMVA tlbiOp(EL3, true,
1811  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1812  0xbeef);
1813 
1814  tlbiOp.broadcast(tc);
1815  return;
1816  }
1817  // AArch64 TLB Invalidate by VA, EL2
1818  case MISCREG_TLBI_VAE2_Xt:
1819  case MISCREG_TLBI_VALE2_Xt:
1820  {
1821  assert64();
1822  scr = readMiscReg(MISCREG_SCR);
1823 
1824  TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1825  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1826  0xbeef);
1827  tlbiOp(tc);
1828  return;
1829  }
1830  // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1831  case MISCREG_TLBI_VAE2IS_Xt:
1832  case MISCREG_TLBI_VALE2IS_Xt:
1833  {
1834  assert64();
1835  scr = readMiscReg(MISCREG_SCR);
1836 
1837  TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1838  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1839  0xbeef);
1840 
1841  tlbiOp.broadcast(tc);
1842  return;
1843  }
1844  // AArch64 TLB Invalidate by VA, EL1
1845  case MISCREG_TLBI_VAE1_Xt:
1846  case MISCREG_TLBI_VALE1_Xt:
1847  {
1848  assert64();
1849  scr = readMiscReg(MISCREG_SCR);
1850  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1851  bits(newVal, 55, 48);
1852 
1853  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1854  bool is_host = (hcr.tge && hcr.e2h);
1855  ExceptionLevel target_el = is_host ? EL2 : EL1;
1856  TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1857  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1858  asid);
1859 
1860  tlbiOp(tc);
1861  return;
1862  }
1863  // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1864  case MISCREG_TLBI_VAE1IS_Xt:
1865  case MISCREG_TLBI_VALE1IS_Xt:
1866  {
1867  assert64();
1868  scr = readMiscReg(MISCREG_SCR);
1869  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1870  bits(newVal, 55, 48);
1871 
1872  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1873  bool is_host = (hcr.tge && hcr.e2h);
1874  ExceptionLevel target_el = is_host ? EL2 : EL1;
1875  TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1876  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1877  asid);
1878 
1879  tlbiOp.broadcast(tc);
1880  return;
1881  }
1882  // AArch64 TLB Invalidate by ASID, EL1
1883  // @todo: handle VMID to enable Virtualization
1884  case MISCREG_TLBI_ASIDE1_Xt:
1885  {
1886  assert64();
1887  scr = readMiscReg(MISCREG_SCR);
1888  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1889  bits(newVal, 55, 48);
1890 
1891  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1892  bool is_host = (hcr.tge && hcr.e2h);
1893  ExceptionLevel target_el = is_host ? EL2 : EL1;
1894  TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1895  tlbiOp(tc);
1896  return;
1897  }
1898  // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1899  case MISCREG_TLBI_ASIDE1IS_Xt:
1900  {
1901  assert64();
1902  scr = readMiscReg(MISCREG_SCR);
1903  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1904  bits(newVal, 55, 48);
1905 
1906  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1907  bool is_host = (hcr.tge && hcr.e2h);
1908  ExceptionLevel target_el = is_host ? EL2 : EL1;
1909  TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1910  tlbiOp.broadcast(tc);
1911  return;
1912  }
1913  // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1914  // entries from the last level of translation table walks
1915  // AArch64 TLB Invalidate by VA, All ASID, EL1
1916  case MISCREG_TLBI_VAAE1_Xt:
1917  case MISCREG_TLBI_VAALE1_Xt:
1918  {
1919  assert64();
1920  scr = readMiscReg(MISCREG_SCR);
1921 
1922  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1923  bool is_host = (hcr.tge && hcr.e2h);
1924  ExceptionLevel target_el = is_host ? EL2 : EL1;
1925  TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1926  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1927 
1928  tlbiOp(tc);
1929  return;
1930  }
1931  // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1932  case MISCREG_TLBI_VAAE1IS_Xt:
1933  case MISCREG_TLBI_VAALE1IS_Xt:
1934  {
1935  assert64();
1936  scr = readMiscReg(MISCREG_SCR);
1937 
1938  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1939  bool is_host = (hcr.tge && hcr.e2h);
1940  ExceptionLevel target_el = is_host ? EL2 : EL1;
1941  TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1942  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1943 
1944  tlbiOp.broadcast(tc);
1945  return;
1946  }
1947  // AArch64 TLB Invalidate by Intermediate Physical Address,
1948  // Stage 2, EL1
1949  case MISCREG_TLBI_IPAS2E1_Xt:
1950  case MISCREG_TLBI_IPAS2LE1_Xt:
1951  {
1952  assert64();
1953  scr = readMiscReg(MISCREG_SCR);
1954 
1955  TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1956  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1957 
1958  tlbiOp(tc);
1959  return;
1960  }
1961  // AArch64 TLB Invalidate by Intermediate Physical Address,
1962  // Stage 2, EL1, Inner Shareable
1963  case MISCREG_TLBI_IPAS2E1IS_Xt:
1964  case MISCREG_TLBI_IPAS2LE1IS_Xt:
1965  {
1966  assert64();
1967  scr = readMiscReg(MISCREG_SCR);
1968 
1969  TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1970  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1971 
1972  tlbiOp.broadcast(tc);
1973  return;
1974  }
1975  case MISCREG_ACTLR:
1976  warn("Not doing anything for write of miscreg ACTLR\n");
1977  break;
1978 
1979  case MISCREG_PMXEVTYPER_PMCCFILTR:
1980  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1981  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1982  case MISCREG_PMCR ... MISCREG_PMOVSSET:
1983  pmu->setMiscReg(misc_reg, newVal);
1984  break;
1985 
1986 
1987  case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1988  {
1989  HSTR hstrMask = 0;
1990  hstrMask.tjdbx = 1;
1991  newVal &= ~((uint32_t) hstrMask);
1992  break;
1993  }
1994  case MISCREG_HCPTR:
1995  {
1996  // If a CP bit in NSACR is 0 then the corresponding bit in
1997  // HCPTR is RAO/WI. Same applies to NSASEDIS
1998  secure_lookup = haveSecurity && isSecure(tc);
1999  if (!secure_lookup) {
2000  RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
2001  RegVal mask =
2002  (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
2003  newVal = (newVal & ~mask) | (oldValue & mask);
2004  }
2005  break;
2006  }
2007  case MISCREG_HDFAR: // alias for secure DFAR
2008  misc_reg = MISCREG_DFAR_S;
2009  break;
2010  case MISCREG_HIFAR: // alias for secure IFAR
2011  misc_reg = MISCREG_IFAR_S;
2012  break;
2013  case MISCREG_ATS1CPR:
2014  addressTranslation(TLB::S1CTran, BaseTLB::Read, 0, val);
2015  return;
2016  case MISCREG_ATS1CPW:
2017  addressTranslation(TLB::S1CTran, BaseTLB::Write, 0, val);
2018  return;
2019  case MISCREG_ATS1CUR:
2020  addressTranslation(TLB::S1CTran, BaseTLB::Read,
2021  TLB::UserMode, val);
2022  return;
2023  case MISCREG_ATS1CUW:
2024  addressTranslation(TLB::S1CTran, BaseTLB::Write,
2025  TLB::UserMode, val);
2026  return;
2027  case MISCREG_ATS12NSOPR:
2028  if (!haveSecurity)
2029  panic("Security Extensions required for ATS12NSOPR");
2030  addressTranslation(TLB::S1S2NsTran, BaseTLB::Read, 0, val);
2031  return;
2032  case MISCREG_ATS12NSOPW:
2033  if (!haveSecurity)
2034  panic("Security Extensions required for ATS12NSOPW");
2035  addressTranslation(TLB::S1S2NsTran, BaseTLB::Write, 0, val);
2036  return;
2037  case MISCREG_ATS12NSOUR:
2038  if (!haveSecurity)
2039  panic("Security Extensions required for ATS12NSOUR");
2040  addressTranslation(TLB::S1S2NsTran, BaseTLB::Read,
2041  TLB::UserMode, val);
2042  return;
2043  case MISCREG_ATS12NSOUW:
2044  if (!haveSecurity)
2045  panic("Security Extensions required for ATS12NSOUW");
2046  addressTranslation(TLB::S1S2NsTran, BaseTLB::Write,
2047  TLB::UserMode, val);
2048  return;
2049  case MISCREG_ATS1HR:
2050  addressTranslation(TLB::HypMode, BaseTLB::Read, 0, val);
2051  return;
2052  case MISCREG_ATS1HW:
2053  addressTranslation(TLB::HypMode, BaseTLB::Write, 0, val);
2054  return;
2055  case MISCREG_TTBCR:
2056  {
2057  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2058  const uint32_t ones = (uint32_t)(-1);
2059  TTBCR ttbcrMask = 0;
2060  TTBCR ttbcrNew = newVal;
2061 
2062  // ARM DDI 0406C.b, ARMv7-32
2063  ttbcrMask.n = ones; // T0SZ
2064  if (haveSecurity) {
2065  ttbcrMask.pd0 = ones;
2066  ttbcrMask.pd1 = ones;
2067  }
2068  ttbcrMask.epd0 = ones;
2069  ttbcrMask.irgn0 = ones;
2070  ttbcrMask.orgn0 = ones;
2071  ttbcrMask.sh0 = ones;
2072  ttbcrMask.ps = ones; // T1SZ
2073  ttbcrMask.a1 = ones;
2074  ttbcrMask.epd1 = ones;
2075  ttbcrMask.irgn1 = ones;
2076  ttbcrMask.orgn1 = ones;
2077  ttbcrMask.sh1 = ones;
2078  if (haveLPAE)
2079  ttbcrMask.eae = ones;
2080 
2081  if (haveLPAE && ttbcrNew.eae) {
2082  newVal = newVal & ttbcrMask;
2083  } else {
2084  newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
2085  }
2086  // Invalidate TLB MiscReg
2087  getITBPtr(tc)->invalidateMiscReg();
2088  getDTBPtr(tc)->invalidateMiscReg();
2089  break;
2090  }
2091  case MISCREG_TTBR0:
2092  case MISCREG_TTBR1:
2093  {
2094  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2095  if (haveLPAE) {
2096  if (ttbcr.eae) {
2097  // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
2098  // ARMv8 AArch32 bit 63-56 only
2099  uint64_t ttbrMask = mask(63,56) | mask(47,40);
2100  newVal = (newVal & (~ttbrMask));
2101  }
2102  }
2103  // Invalidate TLB MiscReg
2104  getITBPtr(tc)->invalidateMiscReg();
2105  getDTBPtr(tc)->invalidateMiscReg();
2106  break;
2107  }
2108  case MISCREG_SCTLR_EL1:
2109  case MISCREG_CONTEXTIDR:
2110  case MISCREG_PRRR:
2111  case MISCREG_NMRR:
2112  case MISCREG_MAIR0:
2113  case MISCREG_MAIR1:
2114  case MISCREG_DACR:
2115  case MISCREG_VTTBR:
2116  case MISCREG_SCR_EL3:
2117  case MISCREG_TCR_EL1:
2118  case MISCREG_TCR_EL2:
2119  case MISCREG_TCR_EL3:
2120  case MISCREG_SCTLR_EL2:
2121  case MISCREG_SCTLR_EL3:
2122  case MISCREG_HSCTLR:
2123  case MISCREG_TTBR0_EL1:
2124  case MISCREG_TTBR1_EL1:
2125  case MISCREG_TTBR0_EL2:
2126  case MISCREG_TTBR1_EL2:
2127  case MISCREG_TTBR0_EL3:
2128  getITBPtr(tc)->invalidateMiscReg();
2129  getDTBPtr(tc)->invalidateMiscReg();
2130  break;
2131  case MISCREG_HCR_EL2:
2132  {
2133  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
2134  selfDebug->setenableTDETGE((HCR)val, mdcr);
2135  getITBPtr(tc)->invalidateMiscReg();
2136  getDTBPtr(tc)->invalidateMiscReg();
2137  }
2138  break;
2139  case MISCREG_NZCV:
2140  {
2141  CPSR cpsr = val;
2142 
2143  tc->setCCReg(CCREG_NZ, cpsr.nz);
2144  tc->setCCReg(CCREG_C, cpsr.c);
2145  tc->setCCReg(CCREG_V, cpsr.v);
2146  }
2147  break;
2148  case MISCREG_DAIF:
2149  {
2150  CPSR cpsr = miscRegs[MISCREG_CPSR];
2151  cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
2152  newVal = cpsr;
2153  misc_reg = MISCREG_CPSR;
2154  }
2155  break;
2156  case MISCREG_SP_EL0:
2157  tc->setIntReg(INTREG_SP0, newVal);
2158  break;
2159  case MISCREG_SP_EL1:
2160  tc->setIntReg(INTREG_SP1, newVal);
2161  break;
2162  case MISCREG_SP_EL2:
2163  tc->setIntReg(INTREG_SP2, newVal);
2164  break;
2165  case MISCREG_SPSEL:
2166  {
2167  CPSR cpsr = miscRegs[MISCREG_CPSR];
2168  cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
2169  newVal = cpsr;
2170  misc_reg = MISCREG_CPSR;
2171  }
2172  break;
2173  case MISCREG_CURRENTEL:
2174  {
2175  CPSR cpsr = miscRegs[MISCREG_CPSR];
2176  cpsr.el = (uint8_t) ((CPSR) newVal).el;
2177  newVal = cpsr;
2178  misc_reg = MISCREG_CPSR;
2179  }
2180  break;
2181  case MISCREG_PAN:
2182  {
2183  // PAN is affecting data accesses
2184  getDTBPtr(tc)->invalidateMiscReg();
2185 
2186  CPSR cpsr = miscRegs[MISCREG_CPSR];
2187  cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
2188  newVal = cpsr;
2189  misc_reg = MISCREG_CPSR;
2190  }
2191  break;
2192  case MISCREG_AT_S1E1R_Xt:
2193  addressTranslation64(TLB::S1E1Tran, BaseTLB::Read, 0, val);
2194  return;
2195  case MISCREG_AT_S1E1W_Xt:
2196  addressTranslation64(TLB::S1E1Tran, BaseTLB::Write, 0, val);
2197  return;
2198  case MISCREG_AT_S1E0R_Xt:
2199  addressTranslation64(TLB::S1E0Tran, BaseTLB::Read,
2200  TLB::UserMode, val);
2201  return;
2202  case MISCREG_AT_S1E0W_Xt:
2203  addressTranslation64(TLB::S1E0Tran, BaseTLB::Write,
2204  TLB::UserMode, val);
2205  return;
2206  case MISCREG_AT_S1E2R_Xt:
2207  addressTranslation64(TLB::S1E2Tran, BaseTLB::Read, 0, val);
2208  return;
2209  case MISCREG_AT_S1E2W_Xt:
2210  addressTranslation64(TLB::S1E2Tran, BaseTLB::Write, 0, val);
2211  return;
2212  case MISCREG_AT_S12E1R_Xt:
2213  addressTranslation64(TLB::S12E1Tran, BaseTLB::Read, 0, val);
2214  return;
2215  case MISCREG_AT_S12E1W_Xt:
2216  addressTranslation64(TLB::S12E1Tran, BaseTLB::Write, 0, val);
2217  return;
2218  case MISCREG_AT_S12E0R_Xt:
2219  addressTranslation64(TLB::S12E0Tran, BaseTLB::Read,
2220  TLB::UserMode, val);
2221  return;
2222  case MISCREG_AT_S12E0W_Xt:
2223  addressTranslation64(TLB::S12E0Tran, BaseTLB::Write,
2224  TLB::UserMode, val);
2225  return;
2226  case MISCREG_AT_S1E3R_Xt:
2227  addressTranslation64(TLB::S1E3Tran, BaseTLB::Read, 0, val);
2228  return;
2229  case MISCREG_AT_S1E3W_Xt:
2230  addressTranslation64(TLB::S1E3Tran, BaseTLB::Write, 0, val);
2231  return;
2232  case MISCREG_SPSR_EL3:
2233  case MISCREG_SPSR_EL2:
2234  case MISCREG_SPSR_EL1:
2235  {
2236  RegVal spsr_mask = havePAN ?
2237  ~(0x2 << 22) : ~(0x3 << 22);
2238 
2239  newVal = val & spsr_mask;
2240  break;
2241  }
2242  case MISCREG_L2CTLR:
2243  warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2244  miscRegName[misc_reg], uint32_t(val));
2245  break;
2246 
2247  // Generic Timer registers
2248  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
2249  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
2250  getGenericTimer().setMiscReg(misc_reg, newVal);
2251  break;
2252  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
2253  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
2254  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2255  getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
2256  return;
2257  case MISCREG_ZCR_EL3:
2258  case MISCREG_ZCR_EL2:
2259  case MISCREG_ZCR_EL1:
2260  tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
2261  break;
2262  }
2263  }
2264  setMiscRegNoEffect(misc_reg, newVal);
2265 }
2266 
2267 BaseISADevice &
2268 ISA::getGenericTimer()
2269 {
2270  // We only need to create an ISA interface the first time we try
2271  // to access the timer.
2272  if (timer)
2273  return *timer.get();
2274 
2275  assert(system);
2276  GenericTimer *generic_timer(system->getGenericTimer());
2277  if (!generic_timer) {
2278  panic("Trying to get a generic timer from a system that hasn't "
2279  "been configured to use a generic timer.\n");
2280  }
2281 
2282  timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2283  timer->setThreadContext(tc);
2284 
2285  return *timer.get();
2286 }
2287 
2288 BaseISADevice &
2289 ISA::getGICv3CPUInterface()
2290 {
2291  panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2292  return *gicv3CpuInterface.get();
2293 }
2294 
2295 unsigned
2296 ISA::getCurSveVecLenInBits() const
2297 {
2298  if (!FullSystem) {
2299  return sveVL * 128;
2300  }
2301 
2302  panic_if(!tc,
2303  "A ThreadContext is needed to determine the SVE vector length "
2304  "in full-system mode");
2305 
2306  CPSR cpsr = miscRegs[MISCREG_CPSR];
2307  ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2308 
2309  unsigned len = 0;
2310 
2311  if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2312  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2313  }
2314 
2315  if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2316  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2317  } else if (haveVirtualization && !isSecure(tc) &&
2318  (el == EL0 || el == EL1)) {
2319  len = std::min(
2320  len,
2321  static_cast<unsigned>(
2322  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2323  }
2324 
2325  if (el == EL3) {
2326  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2327  } else if (haveSecurity) {
2328  len = std::min(
2329  len,
2330  static_cast<unsigned>(
2331  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2332  }
2333 
2334  len = std::min(len, sveVL - 1);
2335 
2336  return (len + 1) * 128;
2337 }
2338 
2339 void
2340 ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
2341 {
2342  auto vv = vc.as<uint64_t>();
2343  for (int i = 2; i < eCount; ++i) {
2344  vv[i] = 0;
2345  }
2346 }
2347 
2348 void
2349 ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
2350  BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2351 {
2352  // If we're in timing mode then doing the translation in
2353  // functional mode then we're slightly distorting performance
2354  // results obtained from simulations. The translation should be
2355  // done in the same mode the core is running in. NOTE: This
2356  // can't be an atomic translation because that causes problems
2357  // with unexpected atomic snoop requests.
2358  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2359 
2360  auto req = std::make_shared<Request>(
2361  val, 0, flags, Request::funcRequestorId,
2362  tc->pcState().pc(), tc->contextId());
2363 
2364  Fault fault = getDTBPtr(tc)->translateFunctional(
2365  req, tc, mode, tran_type);
2366 
2367  PAR par = 0;
2368  if (fault == NoFault) {
2369  Addr paddr = req->getPaddr();
2370  uint64_t attr = getDTBPtr(tc)->getAttr();
2371  uint64_t attr1 = attr >> 56;
2372  if (!attr1 || attr1 ==0x44) {
2373  attr |= 0x100;
2374  attr &= ~ uint64_t(0x80);
2375  }
2376  par = (paddr & mask(47, 12)) | attr;
2377  DPRINTF(MiscRegs,
2378  "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2379  val, par);
2380  } else {
2381  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2382  arm_fault->update(tc);
2383  // Set fault bit and FSR
2384  FSR fsr = arm_fault->getFsr(tc);
2385 
2386  par.f = 1; // F bit
2387  par.fst = fsr.status; // FST
2388  par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
2389  par.s = arm_fault->isStage2() ? 1 : 0; // S
2390 
2391  DPRINTF(MiscRegs,
2392  "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2393  val, fsr, par);
2394  }
2395  setMiscRegNoEffect(MISCREG_PAR_EL1, par);
2396  return;
2397 }
2398 
2399 void
2400 ISA::addressTranslation(TLB::ArmTranslationType tran_type,
2401  BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2402 {
2403  // If we're in timing mode then doing the translation in
2404  // functional mode then we're slightly distorting performance
2405  // results obtained from simulations. The translation should be
2406  // done in the same mode the core is running in. NOTE: This
2407  // can't be an atomic translation because that causes problems
2408  // with unexpected atomic snoop requests.
2409  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2410 
2411  auto req = std::make_shared<Request>(
2412  val, 0, flags, Request::funcRequestorId,
2413  tc->pcState().pc(), tc->contextId());
2414 
2415  Fault fault = getDTBPtr(tc)->translateFunctional(
2416  req, tc, mode, tran_type);
2417 
2418  PAR par = 0;
2419  if (fault == NoFault) {
2420  Addr paddr = req->getPaddr();
2421  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2422  HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
2423 
2424  uint8_t max_paddr_bit = 0;
2425  if (haveLPAE && (ttbcr.eae || tran_type & TLB::HypMode ||
2426  ((tran_type & TLB::S1S2NsTran) && hcr.vm) )) {
2427 
2428  max_paddr_bit = 39;
2429  } else {
2430  max_paddr_bit = 31;
2431  }
2432 
2433  par = (paddr & mask(max_paddr_bit, 12)) |
2434  (getDTBPtr(tc)->getAttr());
2435 
2436  DPRINTF(MiscRegs,
2437  "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2438  val, par);
2439  } else {
2440  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2441  arm_fault->update(tc);
2442  // Set fault bit and FSR
2443  FSR fsr = arm_fault->getFsr(tc);
2444 
2445  par.f = 0x1; // F bit
2446  par.lpae = fsr.lpae;
2447  par.ptw = (arm_fault->iss() >> 7) & 0x1;
2448  par.s = arm_fault->isStage2() ? 1 : 0;
2449 
2450  if (par.lpae) {
2451  // LPAE - rearange fault status
2452  par.fst = fsr.status;
2453  } else {
2454  // VMSA - rearange fault status
2455  par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
2456  par.fs5 = fsr.ext;
2457  }
2458  DPRINTF(MiscRegs,
2459  "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2460  val, fsr, par);
2461  }
2462  setMiscRegNoEffect(MISCREG_PAR, par);
2463  return;
2464 }
2465 
2466 ISA::MiscRegLUTEntryInitializer::chain
2467 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2468 {
2469  switch (FullSystem ? sys->highestEL() : EL1) {
2470  case EL0:
2471  case EL1: priv(); break;
2472  case EL2: hyp(); break;
2473  case EL3: mon(); break;
2474  }
2475  return *this;
2476 }
2477 
2478 } // namespace ArmISA
2479 
2480 ArmISA::ISA *
2481 ArmISAParams::create()
2482 {
2483  return new ArmISA::ISA(this);
2484 }
ArmISA::ISA::setupThreadContext
void setupThreadContext()
Definition: isa.cc:462
ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: miscregs.hh:315
ArmISA::SelfDebug
Definition: self_debug.hh:273
ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: miscregs.hh:668
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gic_v3_cpu_interface.hh
ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: miscregs.hh:471
ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: miscregs.hh:92
ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: miscregs.hh:183
ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: miscregs.hh:814
ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:392
GenericTimerISA
Definition: generic_timer.hh:378
ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: miscregs.hh:874
ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: miscregs.hh:682
ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: miscregs.hh:558
ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: miscregs.hh:302
ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1404
ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: miscregs.hh:669
ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: miscregs.hh:127
ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: miscregs.hh:387
ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: miscregs.hh:313
ArmISA::ISA::getMiscIndices
std::pair< int, int > getMiscIndices(int misc_reg) const
Definition: isa.hh:786
ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:642
ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: miscregs.hh:318
ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: miscregs.hh:470
ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: miscregs.cc:3384
warn
#define warn(...)
Definition: logging.hh:239
ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: miscregs.hh:560
ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: miscregs.hh:1092
ArmISA::SelfDebug::init
void init(ThreadContext *tc)
Definition: self_debug.cc:330
ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: miscregs.hh:504
ArmISA::EL2
@ EL2
Definition: types.hh:624
ArmISA::ISA::clear
void clear()
Definition: isa.cc:132
ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: miscregs.hh:1048
ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: miscregs.hh:507
ArmISA::TLB::UserMode
@ UserMode
Definition: tlb.hh:115
ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: miscregs.hh:245
system.hh
ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: miscregs.hh:248
ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: miscregs.hh:132
ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: miscregs.hh:567
ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: ccregs.hh:45
BaseTLB::Read
@ Read
Definition: tlb.hh:57
ArmISA::ISA::haveVHE
bool haveVHE
Definition: isa.hh:97
ArmISA::daif
Bitfield< 9, 6 > daif
Definition: miscregs_types.hh:66
ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: miscregs.hh:336
ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: miscregs.hh:782
ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: miscregs.hh:150
ArmSystem::haveCrypto
bool haveCrypto() const
Returns true if this system implements the Crypto Extension.
Definition: system.hh:178
ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: miscregs.hh:522
ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:257
ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: miscregs.hh:509
ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: miscregs.hh:500
ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: miscregs.hh:675
ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:58
ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: miscregs.hh:223
ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: miscregs.cc:1347
ArmISA::TLB::ArmTranslationType
ArmTranslationType
Definition: tlb.hh:118
ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:207
ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: miscregs.hh:647
ArmISA::ISA::miscRegs
RegVal miscRegs[NumMiscRegs]
Definition: isa.hh:413
ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:222
ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: miscregs.hh:511
warn_once
#define warn_once(...)
Definition: logging.hh:243
ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: miscregs.hh:1046
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: miscregs.hh:559
ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: miscregs.hh:570
ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: miscregs.hh:745
ArmISA::ISA::haveLPAE
bool haveLPAE
Definition: isa.hh:90
Loader::Arm
@ Arm
Definition: object_file.hh:52
ArmISA::EL0
@ EL0
Definition: types.hh:622
ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: miscregs.hh:331
ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: miscregs.hh:514
ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: miscregs.hh:255
ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: miscregs.hh:673
ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:635
ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: miscregs.hh:322
Flags< FlagsType >
ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: miscregs.hh:483
ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: miscregs.hh:502
ArmISA::SelfDebug::setMDBGen
void setMDBGen(RegVal val)
Definition: self_debug.hh:387
ArmISA::ISA::gicv3CpuInterface
std::unique_ptr< BaseISADevice > gicv3CpuInterface
Definition: isa.hh:85
ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: miscregs.hh:211
ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: miscregs.hh:198
ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: miscregs.hh:515
ArmISA::BaseISADevice::setThreadContext
virtual void setThreadContext(ThreadContext *tc)
Definition: isa_device.hh:65
ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: miscregs.hh:610
ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: miscregs.hh:298
ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: miscregs.hh:614
ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: miscregs.hh:195
ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: miscregs.hh:589
ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: miscregs.hh:877
ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: miscregs.hh:612
ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: miscregs.hh:328
ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: miscregs.hh:213
ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: miscregs.hh:568
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: miscregs.hh:316
ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: miscregs.hh:676
BaseTLB::Mode
Mode
Definition: tlb.hh:57
ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: miscregs.hh:222
ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: miscregs.hh:206
ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: miscregs.hh:473
ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: miscregs.hh:695
ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: miscregs.hh:698
ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: miscregs.hh:829
ArmISA::SelfDebug::updateDBGWCR
void updateDBGWCR(int index, DBGWCR val)
Definition: self_debug.hh:411
ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: miscregs.hh:717
ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: miscregs.hh:235
ArmISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:838
ArmISA::TLB::HypMode
@ HypMode
Definition: tlb.hh:121
ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: miscregs.hh:370
ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: miscregs.hh:699
ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: miscregs.hh:69
ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:190
ArmISA::HTMCheckpoint
Definition: htm.hh:54
ArmISA::CCREG_V
@ CCREG_V
Definition: ccregs.hh:47
ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: miscregs.hh:588
ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: miscregs.hh:672
ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: miscregs.hh:77
ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: miscregs.hh:99
ArmSystem::haveSVE
bool haveSVE() const
Returns true if SVE is implemented (ARMv8)
Definition: system.hh:234
ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: miscregs.hh:683
CheckerCPU
CheckerCPU class.
Definition: cpu.hh:85
ArmISA::DTLBIALL
Data TLB Invalidate All.
Definition: tlbi_op.hh:105
ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: miscregs.hh:654
ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: miscregs.hh:76
ArmISA::ArmFault::isStage2
virtual bool isStage2() const
Definition: faults.hh:249
ArmISA::TLBIOp::broadcast
void broadcast(ThreadContext *tc)
Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
Definition: tlbi_op.hh:69
tlb.hh
std::vector
STL vector class.
Definition: stl.hh:37
ArmISA::TLB::getAttr
uint64_t getAttr() const
Definition: tlb.hh:349
ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: miscregs.hh:512
ArmISA::ISA::redirectRegVHE
int redirectRegVHE(ThreadContext *tc, int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
Definition: isa.hh:709
GenericTimer
Definition: generic_timer.hh:276
ArmISA::EL3
@ EL3
Definition: types.hh:625
ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: miscregs.hh:126
ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: miscregs.hh:731
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: miscregs.hh:330
ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: miscregs.hh:218
ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: miscregs.hh:390
ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: miscregs.hh:596
ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: miscregs.hh:212
ArmISA::ISA
Definition: isa.hh:65
ArmISA::TLB::S1S2NsTran
@ S1S2NsTran
Definition: tlb.hh:124
ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: miscregs.hh:221
ArmSystem::getGIC
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition: system.hh:200
mbits
T mbits(T val, int first, int last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:104
ArmSystem::getGenericTimer
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
Definition: system.hh:197
ArmISA::Interrupts
Definition: interrupts.hh:69
system.hh
ThreadContext::setHtmCheckpointPtr
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:118
ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: miscregs.hh:1043
ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: miscregs.cc:1363
ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: miscregs.hh:1050
ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: miscregs.hh:513
ArmISA::miscRegName
const char *const miscRegName[]
Definition: miscregs.hh:1159
ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: miscregs.hh:652
faults.hh
ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: miscregs.hh:284
ArmISA::ISA::sveVL
unsigned sveVL
SVE vector length in quadwords.
Definition: isa.hh:103
ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: miscregs.hh:88
ArmISA
Definition: ccregs.hh:41
ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: miscregs.hh:129
ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: miscregs.hh:687
ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: miscregs.hh:602
ArmISA::ISA::haveSecEL2
bool haveSecEL2
Definition: isa.hh:99
ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: miscregs.hh:667
ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: miscregs.hh:205
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:173
ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: miscregs.hh:320
ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: miscregs.hh:130
ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: miscregs.hh:300
ArmISA::ISA::Params
ArmISAParams Params
Definition: isa.hh:855
ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: miscregs.hh:164
ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:490
ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: miscregs.hh:334
ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: miscregs.hh:228
ArmISA::ISA::zeroSveVecRegUpperPart
static void zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
Definition: isa.cc:2340
ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: miscregs.hh:407
ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: miscregs.hh:482
ArmISA::ISA::takeOverFrom
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
Definition: isa.cc:483
ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: miscregs.hh:561
ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: miscregs.hh:505
ArmISA::ISA::assert32
void assert32()
Definition: isa.hh:458
ThreadContext::threadId
virtual int threadId() const =0
ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:69
ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: miscregs.hh:327
ArmISA::ISA::addressTranslation
void addressTranslation(TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2400
ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: miscregs.hh:557
iGbReg::TxdOp::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:250
ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: miscregs.hh:131
ArmISA::ISA::timer
std::unique_ptr< BaseISADevice > timer
Definition: isa.hh:82
ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: miscregs.hh:239
VecRegContainer::as
VecRegT< VecElem, NumElems, true > as() const
View interposers.
Definition: vec_reg.hh:386
ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: miscregs.hh:337
ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: miscregs.hh:556
ArmISA::ISA::_vecRegRenameMode
const Enums::VecRegRenameMode _vecRegRenameMode
Definition: isa.hh:73
ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: miscregs.hh:664
ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: miscregs.hh:364
SimObject::startup
virtual void startup()
startup() is the final initialization call before simulation.
Definition: sim_object.cc:96
ArmISA::ISA::haveLargeAsid64
bool haveLargeAsid64
Definition: isa.hh:93
ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: miscregs.hh:469
ArmISA::ISA::haveLSE
bool haveLSE
Definition: isa.hh:96
ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: miscregs.hh:375
ArmISA::CCREG_C
@ CCREG_C
Definition: ccregs.hh:46
ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: miscregs.hh:344
ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: miscregs.hh:468
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: miscregs.hh:133
ArmISA::SelfDebug::setDebugMask
void setDebugMask(bool mask)
Definition: self_debug.hh:417
ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: miscregs.hh:279
ArmISA::TLB::S1CTran
@ S1CTran
Definition: tlb.hh:120
ArmISA::ISA::assert64
void assert64()
Definition: isa.hh:459
htm.hh
ArmISA::ISA::haveTME
bool haveTME
Definition: isa.hh:100
ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: miscregs.hh:155
ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: miscregs.hh:523
ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: miscregs.hh:214
ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: miscregs.hh:657
ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: miscregs.hh:697
ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:383
ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: miscregs.hh:288
ArmISA::TLB::S12E0Tran
@ S12E0Tran
Definition: tlb.hh:133
ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: miscregs.hh:393
ArmISA::BaseISADevice::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: miscregs.hh:207
ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: miscregs.hh:388
ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: miscregs.hh:951
ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: miscregs.hh:202
ArmISA::SelfDebug::setbSDD
void setbSDD(RegVal val)
Definition: self_debug.hh:373
ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: miscregs.hh:553
interrupts.hh
ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: miscregs.hh:282
ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: miscregs.hh:325
ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:164
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: miscregs.hh:87
ArmISA::ISA::haveSVE
bool haveSVE
Definition: isa.hh:95
ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:631
ArmISA::ISA::dummyDevice
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
Definition: isa.hh:76
ArmSystem::haveLPAE
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.
Definition: system.hh:168
ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: miscregs.hh:378
ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: miscregs.hh:503
ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: miscregs.hh:339
ArmSystem::haveLSE
bool haveLSE() const
Returns true if LSE is implemented (ARMv8.1)
Definition: system.hh:240
ArmISA::ArmFault
Definition: faults.hh:60
ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: miscregs.hh:156
ArmISA::TLB::S1E2Tran
@ S1E2Tran
Definition: tlb.hh:131
ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: miscregs.hh:449
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: miscregs.hh:242
ThreadContext::pcStateNoRecord
virtual void pcStateNoRecord(const TheISA::PCState &val)=0
ArmISA::ISA::clear32
void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
Definition: isa.cc:225
ArmSystem::havePAN
bool havePAN() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:246
ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: miscregs.hh:301
ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: miscregs.hh:671
ArmISA::ISA::haveCrypto
bool haveCrypto
Definition: isa.hh:92
BaseISA::tc
ThreadContext * tc
Definition: isa.hh:52
ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:621
ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: miscregs.hh:360
ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: miscregs.hh:204
ArmISA::SelfDebug::setMDSCRvals
void setMDSCRvals(RegVal val)
Definition: self_debug.hh:379
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: miscregs.hh:162
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: miscregs.hh:666
ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: miscregs.hh:538
ArmISA::ISA::ISA
ISA(Params *p)
Definition: isa.cc:63
ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: miscregs.hh:562
isa.hh
ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: miscregs.hh:663
ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: miscregs.hh:653
MipsISA::r
r
Definition: pra_constants.hh:95
cpu.hh
ArmISA::FpscrExcMask
static const uint32_t FpscrExcMask
Definition: miscregs.hh:2196
ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: miscregs.hh:608
ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: miscregs.hh:216
ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: miscregs.hh:593
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: miscregs.hh:219
ArmISA::el
Bitfield< 3, 2 > el
Definition: miscregs_types.hh:69
ArmISA::ISA::getGICv3CPUInterface
BaseISADevice & getGICv3CPUInterface()
Definition: isa.cc:2289
ArmISA::TLB::S1E0Tran
@ S1E0Tran
Definition: tlb.hh:129
ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: miscregs.hh:730
ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: miscregs.hh:361
ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: miscregs.hh:335
ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: miscregs.hh:254
ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: miscregs.hh:262
ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: miscregs.hh:555
ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: miscregs.hh:152
ArmISA::getDTBPtr
TLB * getDTBPtr(T *tc)
Definition: tlb.hh:479
ArmISA::attr
attr
Definition: miscregs_types.hh:649
ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: miscregs.hh:477
ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: miscregs.hh:688
ArmSystem::sveVL
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
Definition: system.hh:237
ArmSystem::haveSecEL2
bool haveSecEL2() const
Returns true if Priviledge Access Never is implemented.
Definition: system.hh:249
tlbi_op.hh
System::Threads::size
int size() const
Definition: system.hh:204
ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: miscregs.hh:231
ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: miscregs.hh:120
ThreadContext::contextId
virtual ContextID contextId() const =0
ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: miscregs.hh:332
ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: miscregs.hh:679
ArmISA::ISA::clear64
void clear64(const ArmISAParams *p)
Definition: isa.cc:277
ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: miscregs.hh:232
ArmISA::ISA::selfDebug
SelfDebug * selfDebug
Definition: isa.hh:113
ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: miscregs.hh:595
ArmISA::INTREG_SP0
@ INTREG_SP0
Definition: intregs.hh:118
ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: miscregs.hh:670
ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: miscregs.hh:342
Gicv3
Definition: gic_v3.hh:53
ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: miscregs.hh:780
ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: miscregs.hh:305
ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: miscregs.hh:259
ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: miscregs.hh:230
ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: miscregs.hh:692
ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: miscregs.hh:506
ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: miscregs.hh:304
ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: miscregs.hh:479
ArmISA::TLB::invalidateMiscReg
void invalidateMiscReg()
Definition: tlb.hh:446
ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:175
ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: miscregs.hh:159
ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: miscregs.hh:601
ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: miscregs.hh:510
faults.hh
ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: miscregs.hh:321
generic_timer.hh
ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: miscregs.hh:317
ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: miscregs.hh:243
ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: miscregs.hh:160
ArmISA::ISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: isa.cc:2467
ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: miscregs.hh:578
ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:816
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: miscregs.hh:696
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: miscregs.hh:591
ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: miscregs.hh:91
ArmISA::sp
Bitfield< 0 > sp
Definition: miscregs_types.hh:71
ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: miscregs.hh:626
ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: miscregs.hh:265
ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: miscregs.hh:326
ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: miscregs.hh:71
ArmISA::EL1
@ EL1
Definition: types.hh:623
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: miscregs.hh:735
ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: miscregs.hh:303
ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: miscregs.hh:340
ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: miscregs.hh:1095
ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: miscregs.hh:240
ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:236
ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: miscregs.hh:329
ArmISA::SelfDebug::updateOSLock
void updateOSLock(RegVal val)
Definition: self_debug.hh:399
ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: miscregs.hh:153
ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: miscregs.hh:203
ArmISA::ISA::afterStartup
bool afterStartup
Definition: isa.hh:111
ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:279
ArmISA::ISA::updateRegMap
void updateRegMap(CPSR cpsr)
Definition: isa.hh:417
ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: miscregs.hh:651
ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: miscregs.hh:68
ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: miscregs.hh:481
ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:81
ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: miscregs.hh:1047
ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: miscregs.hh:369
ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: miscregs.hh:125
ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: miscregs.hh:701
ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: miscregs.hh:619
ArmISA::ISA::getGenericTimer
BaseISADevice & getGenericTimer()
Definition: isa.cc:2268
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
ArmISA::CpsrMaskQ
static const uint32_t CpsrMaskQ
Definition: miscregs.hh:2175
ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: miscregs.hh:251
Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:248
ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: miscregs.hh:1085
ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: miscregs.hh:694
ArmISA::asid
asid
Definition: miscregs_types.hh:611
ArmISA::ISA::haveVirtualization
bool haveVirtualization
Definition: isa.hh:91
ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
BaseTLB::Write
@ Write
Definition: tlb.hh:57
ArmISA::ISA::MiscRegLUTEntryInitializer::chain
const typedef MiscRegLUTEntryInitializer & chain
Definition: isa.hh:143
ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: miscregs.hh:363
ArmISA::DTLBIMVA
Data TLB Invalidate by VA.
Definition: tlbi_op.hh:224
ArmSystem
Definition: system.hh:59
ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: miscregs.hh:475
ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: miscregs.hh:677
ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: miscregs.hh:343
ArmISA::ITLBIALL
Instruction TLB Invalidate All.
Definition: tlbi_op.hh:92
ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: miscregs.hh:585
ArmISA::ISA::haveSecurity
bool haveSecurity
Definition: isa.hh:89
ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: miscregs.hh:209
ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: miscregs.hh:580
stat_control.hh
ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: miscregs.hh:163
ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: miscregs.hh:609
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
System::threads
Threads threads
Definition: system.hh:309
ArmISA::getITBPtr
TLB * getITBPtr(T *tc)
Definition: tlb.hh:470
ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: miscregs.hh:372
ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: miscregs.hh:236
ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: miscregs.hh:184
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
ArmISA::TLB::S1E1Tran
@ S1E1Tran
Definition: tlb.hh:130
ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: miscregs.hh:674
ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: miscregs.hh:472
ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: miscregs.hh:613
ArmISA::ISA::physAddrRange
uint8_t physAddrRange
Definition: isa.hh:94
ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: miscregs.hh:662
ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: miscregs.hh:128
ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)=0
base.hh
ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:436
ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: miscregs.hh:165
ArmISA::ISA::pmu
BaseISADevice * pmu
Definition: isa.hh:79
ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: miscregs.hh:684
ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: miscregs.hh:686
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: miscregs.hh:579
SimObject::_params
const SimObjectParams * _params
Cached copy of the object parameters.
Definition: sim_object.hh:110
ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: miscregs.hh:210
ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: miscregs.hh:700
ArmISA::ISA::initID64
void initID64(const ArmISAParams *p)
Definition: isa.cc:362
Gicv3::getCPUInterface
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
Definition: gic_v3.hh:137
ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: miscregs.hh:341
ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: miscregs.hh:319
ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:211
ArmISA::pan
Bitfield< 22 > pan
Definition: miscregs_types.hh:55
insertBits
T insertBits(T val, int first, int last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:147
ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: miscregs.hh:123
ArmISA::ArmFault::getFsr
virtual FSR getFsr(ThreadContext *tc) const
Definition: faults.hh:250
ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: miscregs.hh:1088
ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: miscregs.hh:217
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: miscregs.hh:86
ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: miscregs.hh:906
ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: miscregs.hh:681
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
ArmISA::MiscRegIndex
MiscRegIndex
Definition: miscregs.hh:56
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: miscregs.hh:246
ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: miscregs.hh:533
ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: miscregs.hh:227
ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: miscregs.hh:154
ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: miscregs.hh:215
ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: miscregs.hh:534
ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: miscregs.hh:324
ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: miscregs.hh:323
ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: miscregs.hh:508
ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: miscregs.hh:474
ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: miscregs.hh:208
ArmISA::TLBIIPA
TLB Invalidate by Intermediate Physical Address.
Definition: tlbi_op.hh:242
pmu.hh
ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: miscregs.hh:67
ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: miscregs.hh:733
ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: miscregs.hh:689
ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: miscregs.hh:366
ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:640
ArmISA::FpscrQcMask
static const uint32_t FpscrQcMask
Definition: miscregs.hh:2192
ArmISA::ISA::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: isa.cc:445
ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: miscregs.hh:161
ArmISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:514
ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: miscregs.hh:283
ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: miscregs.hh:121
ArmISA::SelfDebug::updateDBGBCR
void updateDBGBCR(int index, DBGBCR val)
Definition: self_debug.hh:405
ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:317
ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: miscregs.hh:124
ArmISA::ISA::addressTranslation64
void addressTranslation64(TLB::ArmTranslationType tran_type, BaseTLB::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2349
ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: miscregs.hh:812
ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: miscregs.hh:229
ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2296
ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: miscregs.hh:665
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
self_debug.hh
ArmISA::TLB::S1E3Tran
@ S1E3Tran
Definition: tlb.hh:132
ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: miscregs.hh:693
ArmISA::DTLBIASID
Data TLB Invalidate by ASID match.
Definition: tlbi_op.hh:148
ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: miscregs.hh:611
ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: miscregs.hh:574
ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: miscregs.hh:122
ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: miscregs.hh:480
ArmISA::ISA::initID32
void initID32(const ArmISAParams *p)
Definition: isa.cc:326
System::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: system.hh:307
ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:636
ArmISA::ITLBIASID
Instruction TLB Invalidate by ASID match.
Definition: tlbi_op.hh:132
ArmISA::ISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: isa.hh:246
ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: miscregs.hh:793
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: miscregs.hh:201
ArmISA::INTREG_SP1
@ INTREG_SP1
Definition: intregs.hh:119
ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: miscregs.hh:624
ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: miscregs.hh:583
ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: miscregs.hh:157
ArmSystem::haveTME
bool haveTME() const
Returns true if this system implements the transactional memory extension (ARMv9)
Definition: system.hh:231
ArmISA::ISA::havePAN
bool havePAN
Definition: isa.hh:98
ArmISA::SelfDebug::setenableTDETGE
void setenableTDETGE(HCR hcr, HDCR mdcr)
Definition: self_debug.hh:393
ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: miscregs.hh:151
ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: miscregs.hh:691
ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: miscregs.hh:197
ArmISA::BaseISADevice::setISA
virtual void setISA(ISA *isa)
Definition: isa_device.cc:51
ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: miscregs.hh:333
ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: miscregs.hh:690
ArmISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:85
ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: miscregs.hh:237
ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: miscregs.hh:244
ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: miscregs.hh:476
ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: miscregs.hh:680
ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: miscregs.hh:478
ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: miscregs.hh:427
ArmISA::TLB::S12E1Tran
@ S12E1Tran
Definition: tlb.hh:134
ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:633
BaseISA
Definition: isa.hh:47
ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: miscregs.hh:587
ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: miscregs.hh:617
ArmISA::miscRegInfo
bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: miscregs.cc:3381
ArmISA::ISA::params
const Params * params() const
Definition: isa.cc:126
BaseCPU::getInterruptController
BaseInterrupts * getInterruptController(ThreadID tid)
Definition: base.hh:219
ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: miscregs.hh:576
ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: miscregs.hh:554
ArmSystem::haveVHE
bool haveVHE() const
Returns true if Virtualization Host Extensions is implemented.
Definition: system.hh:243
ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: miscregs.hh:338
gic_v3.hh
ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:88
ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: miscregs.hh:501
ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: miscregs.hh:442
ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: miscregs.hh:314
ArmISA::ITLBIMVA
Instruction TLB Invalidate by VA.
Definition: tlbi_op.hh:206
ArmISA::v
Bitfield< 28 > v
Definition: miscregs_types.hh:51
ArmISA::TLB::translateFunctional
bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr)
Do a functional lookup on the TLB (for debugging) and don't modify any internal state.
Definition: tlb.cc:117
ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: miscregs.hh:118
ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: miscregs.hh:75
ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: miscregs.hh:119
ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: miscregs.hh:224
ULL
#define ULL(N)
uint64_t constant
Definition: types.hh:50
ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: miscregs.hh:685
RegVal
uint64_t RegVal
Definition: types.hh:168
ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: miscregs.hh:345
ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: miscregs.hh:220
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:156
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: miscregs.hh:571
ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:174
ArmISA::ISA::lookUpMiscReg
static std::vector< struct MiscRegLUTEntry > lookUpMiscReg
Metadata table accessible via the value of the register.
Definition: isa.hh:138
ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: miscregs.hh:158
ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:226
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:164
ArmISA::BaseISADevice::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: miscregs.hh:678
ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: miscregs.hh:702
ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: miscregs.hh:70
ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: miscregs.hh:299
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75
ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: miscregs.hh:604
ArmISA::INTREG_SP2
@ INTREG_SP2
Definition: intregs.hh:120
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