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rdy_gen.h
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2 
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements. See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
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18  *****************************************************************************/
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20 /*****************************************************************************
21 
22  rdy_gen.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 /******************************************************************************/
39 /*************************** RDY_GEN **********************/
40 /******************************************************************************/
41 
42 SC_MODULE( RDY_GEN )
43 {
44  SC_HAS_PROCESS( RDY_GEN );
45 
46  sc_in_clk clk;
47 
48  sc_signal<bool>& ready; // Output
49 
50  RDY_GEN ( sc_module_name NAME,
51  sc_clock& TICK_P,
52  sc_signal<bool>& READY )
53 
54  :
55  ready (READY)
56 
57  {
58  clk (TICK_P);
59  SC_CTHREAD( entry, clk.pos() );
60  }
61 
62  void entry();
63 
64 };
65 
66 void
67 RDY_GEN::entry()
68 {
69  ready.write(1);
70  wait();
71  cout << sc_time_stamp() << " : "
72  << "WRITING ready = 1" << endl;
73 
74  ready.write(0);
75  wait();
76  cout << sc_time_stamp() << " : "
77  << "WRITING ready = 0" << endl;
78 
79  ready.write(1);
80  wait();
81  cout << sc_time_stamp() << " : "
82  << "WRITING ready = 1" << endl;
83 }
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
SC_MODULE
SC_MODULE(RDY_GEN)
Definition: rdy_gen.h:42
sc_core::wait
void wait()
Definition: sc_module.cc:653
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition: sc_main.cc:128
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