gem5
v21.1.0.0
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#include <mmu.hh>
Classes | |
class | Translation |
Public Types | |
enum | Mode { Read, Write, Execute } |
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typedef SimObjectParams | Params |
Public Member Functions | |
virtual void | flushAll () |
void | demapPage (Addr vaddr, uint64_t asn) |
Fault | translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode) |
void | translateTiming (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) |
Fault | translateFunctional (const RequestPtr &req, ThreadContext *tc, Mode mode) |
Fault | finalizePhysical (const RequestPtr &req, ThreadContext *tc, Mode mode) const |
virtual void | takeOverFrom (BaseMMU *old_mmu) |
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const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. More... | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. More... | |
virtual void | regProbePoints () |
Register probe points for this object. More... | |
virtual void | regProbeListeners () |
Register probe listeners for this object. More... | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. More... | |
virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
Get a port with a given name and index. More... | |
virtual void | startup () |
startup() is the final initialization call before simulation. More... | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. More... | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. More... | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. More... | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
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EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More... | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. More... | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. More... | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. More... | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. More... | |
virtual void | notifyFork () |
Notify a child process of a fork. More... | |
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Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. More... | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. More... | |
virtual void | resetStats () |
Callback to reset stats. More... | |
virtual void | preDumpStats () |
Callback before stats are dumped. More... | |
void | addStat (statistics::Info *info) |
Register a stat with this group. More... | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. More... | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. More... | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. More... | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. More... | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. More... | |
Group ()=delete | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
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Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
Public Attributes | |
BaseTLB * | dtb |
BaseTLB * | itb |
Protected Types | |
typedef BaseMMUParams | Params |
Protected Member Functions | |
BaseMMU (const Params &p) | |
BaseTLB * | getTlb (Mode mode) const |
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Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. More... | |
void | signalDrainDone () const |
Signal that an object is drained. More... | |
Additional Inherited Members | |
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static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. More... | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. More... | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More... | |
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static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. More... | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. More... | |
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const SimObjectParams & | _params |
Cached copy of the object parameters. More... | |
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EventQueue * | eventq |
A pointer to this object's event queue. More... | |
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protected |
enum gem5::BaseMMU::Mode |
void gem5::BaseMMU::demapPage | ( | Addr | vaddr, |
uint64_t | asn | ||
) |
Definition at line 58 of file mmu.cc.
References gem5::BaseTLB::demapPage(), dtb, itb, and gem5::MipsISA::vaddr.
Referenced by gem5::SimpleThread::demapPage(), gem5::o3::CPU::demapPage(), gem5::minor::ExecContext::demapPage(), gem5::CheckerCPU::demapPage(), and gem5::X86ISA::PageFault::invoke().
Fault gem5::BaseMMU::finalizePhysical | ( | const RequestPtr & | req, |
ThreadContext * | tc, | ||
BaseMMU::Mode | mode | ||
) | const |
Definition at line 86 of file mmu.cc.
References gem5::BaseTLB::finalizePhysical(), getTlb(), and gem5::ArmISA::mode.
Referenced by gem5::BaseKvmCPU::doMMIOAccess().
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virtual |
Reimplemented in gem5::ArmISA::MMU.
Definition at line 51 of file mmu.cc.
References dtb, gem5::BaseTLB::flushAll(), and itb.
Referenced by gem5::X86ISA::copyMiscRegs(), gem5::ArmISA::MMU::flushAll(), gem5::BaseCPU::flushTLBs(), gem5::GPUComputeDriver::ioctl(), and gem5::X86ISA::ISA::setMiscReg().
Definition at line 92 of file mmu.hh.
References dtb, Execute, itb, and gem5::ArmISA::mode.
Referenced by finalizePhysical(), translateAtomic(), translateFunctional(), and translateTiming().
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virtual |
Reimplemented in gem5::RiscvISA::MMU.
Definition at line 93 of file mmu.cc.
References dtb, gem5::BaseTLB::getTableWalkerPort(), itb, gem5::BaseTLB::takeOverFrom(), and gem5::Port::takeOverFrom().
Referenced by gem5::RiscvISA::MMU::takeOverFrom(), and gem5::BaseCPU::takeOverFrom().
Fault gem5::BaseMMU::translateAtomic | ( | const RequestPtr & | req, |
ThreadContext * | tc, | ||
BaseMMU::Mode | mode | ||
) |
Definition at line 65 of file mmu.cc.
References getTlb(), gem5::ArmISA::mode, and gem5::BaseTLB::translateAtomic().
Referenced by gem5::AtomicSimpleCPU::amoMem(), gem5::BaseCPU::mwaitAtomic(), gem5::AtomicSimpleCPU::readMem(), gem5::AtomicSimpleCPU::tick(), and gem5::AtomicSimpleCPU::writeMem().
Fault gem5::BaseMMU::translateFunctional | ( | const RequestPtr & | req, |
ThreadContext * | tc, | ||
BaseMMU::Mode | mode | ||
) |
Definition at line 79 of file mmu.cc.
References getTlb(), gem5::ArmISA::mode, and gem5::BaseTLB::translateFunctional().
Referenced by gem5::CheckerCPU::readMem(), gem5::TranslatingPortProxy::tryTLBsOnce(), gem5::tryTranslate(), and gem5::CheckerCPU::writeMem().
void gem5::BaseMMU::translateTiming | ( | const RequestPtr & | req, |
ThreadContext * | tc, | ||
BaseMMU::Translation * | translation, | ||
BaseMMU::Mode | mode | ||
) |
Definition at line 72 of file mmu.cc.
References getTlb(), gem5::ArmISA::mode, and gem5::BaseTLB::translateTiming().
Referenced by gem5::TimingSimpleCPU::fetch(), gem5::o3::Fetch::fetchCacheLine(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::minor::LSQ::SplitDataRequest::sendNextFragmentToTranslation(), gem5::minor::LSQ::SingleDataRequest::startAddrTranslation(), and gem5::TimingSimpleCPU::writeMem().
BaseTLB* gem5::BaseMMU::dtb |
Definition at line 120 of file mmu.hh.
Referenced by demapPage(), flushAll(), gem5::X86ISA::MMU::flushNonGlobal(), gem5::X86ISA::MMU::getDataWalker(), gem5::RiscvISA::MMU::getDataWalker(), gem5::ArmISA::MMU::getDTBPtr(), gem5::RiscvISA::MMU::getMemPriv(), gem5::RiscvISA::MMU::getPMP(), getTlb(), gem5::SparcISA::MMU::insertDtlbEntry(), and takeOverFrom().
BaseTLB* gem5::BaseMMU::itb |
Definition at line 121 of file mmu.hh.
Referenced by demapPage(), gem5::SparcISA::TLB::doMmuRegRead(), gem5::SparcISA::TLB::doMmuRegWrite(), flushAll(), gem5::X86ISA::MMU::flushNonGlobal(), gem5::ArmISA::MMU::getITBPtr(), getTlb(), gem5::SparcISA::TLB::GetTsbPtr(), gem5::SparcISA::MMU::insertItlbEntry(), and takeOverFrom().