cpu.hh

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/*
 * Copyright (c) 2011-2013, 2016-2020 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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 *
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 *
 * Copyright (c) 2004-2005 The Regents of The University of Michigan
 * Copyright (c) 2011 Regents of the University of California
 * All rights reserved.
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#ifndef __CPU_O3_CPU_HH__
#define __CPU_O3_CPU_HH__
 
#include <iostream>
#include <list>
#include <queue>
#include <set>
#include <vector>
 
#include "arch/generic/types.hh"
#include "arch/pcstate.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/decode.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/fetch.hh"
#include "cpu/o3/free_list.hh"
#include "cpu/o3/iew.hh"
#include "cpu/o3/limits.hh"
#include "cpu/o3/rename.hh"
#include "cpu/o3/rob.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/thread_state.hh"
#include "cpu/activity.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/timebuf.hh"
#include "params/O3CPU.hh"
#include "sim/process.hh"
 
namespace gem5
{
 
template <class>
class Checker;
class ThreadContext;
 
class Checkpoint;
class Process;
 
namespace o3
{
 
class ThreadContext;
 
class CPU : public BaseCPU
{
  public:
    typedef std::list<DynInstPtr>::iterator ListIt;
 
    friend class ThreadContext;
 
  public:
    enum Status
    {
        Running,
        Idle,
        Halted,
        Blocked,
        SwitchedOut
    };
 
    BaseMMU *mmu;
    using LSQRequest = LSQ::LSQRequest;
 
    Status _status;
 
  private:
 
    EventFunctionWrapper tickEvent;
 
    EventFunctionWrapper threadExitEvent;
 
    void scheduleTickEvent(Cycles delay)
    {
        if (tickEvent.squashed())
            reschedule(tickEvent, clockEdge(delay));
        else if (!tickEvent.scheduled())
            schedule(tickEvent, clockEdge(delay));
    }
 
    void unscheduleTickEvent()
    {
        if (tickEvent.scheduled())
            tickEvent.squash();
    }
 
    bool tryDrain();
 
    void drainSanityCheck() const;
 
    bool isCpuDrained() const;
 
  public:
    CPU(const O3CPUParams &params);
 
    ProbePointArg<PacketPtr> *ppInstAccessComplete;
    ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
 
    void regProbePoints() override;
 
    void
    demapPage(Addr vaddr, uint64_t asn)
    {
        mmu->demapPage(vaddr, asn);
    }
 
    void tick();
 
    void init() override;
 
    void startup() override;
 
    int numActiveThreads()
    { return activeThreads.size(); }
 
    void activateThread(ThreadID tid);
 
    void deactivateThread(ThreadID tid);
 
    void insertThread(ThreadID tid);
 
    void removeThread(ThreadID tid);
 
    Counter totalInsts() const override;
 
    Counter totalOps() const override;
 
    void activateContext(ThreadID tid) override;
 
    void suspendContext(ThreadID tid) override;
 
    void haltContext(ThreadID tid) override;
 
    void updateThreadPriority();
 
    bool isDraining() const { return drainState() == DrainState::Draining; }
 
    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
    void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 
    void addThreadToExitingList(ThreadID tid);
 
    bool isThreadExiting(ThreadID tid) const;
 
    void scheduleThreadExitEvent(ThreadID tid);
 
    void exitThreads();
 
  public:
    DrainState drain() override;
 
    void drainResume() override;
 
    void commitDrained(ThreadID tid);
 
    void switchOut() override;
 
    void takeOverFrom(BaseCPU *oldCPU) override;
 
    void verifyMemoryMode() const override;
 
    InstSeqNum getAndIncrementInstSeq()
    { return globalSeqNum++; }
 
    void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
 
    void setVectorsAsReady(ThreadID tid);
 
    void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
 
    Fault getInterrupts();
 
    void processInterrupts(const Fault &interrupt);
 
    void halt() { panic("Halt not implemented!\n"); }
 
    RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
 
    RegVal readMiscReg(int misc_reg, ThreadID tid);
 
    void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
 
    void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
 
    RegVal readIntReg(PhysRegIdPtr phys_reg);
 
    RegVal readFloatReg(PhysRegIdPtr phys_reg);
 
    const TheISA::VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
 
    TheISA::VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
 
    enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
 
    void vecRenameMode(enums::VecRegRenameMode vec_mode)
    { vecMode = vec_mode; }
 
    const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
 
    const TheISA::VecPredRegContainer&
        readVecPredReg(PhysRegIdPtr reg_idx) const;
 
    TheISA::VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
 
    RegVal readCCReg(PhysRegIdPtr phys_reg);
 
    void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
 
    void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
 
    void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer& val);
 
    void setVecElem(PhysRegIdPtr reg_idx, const TheISA::VecElem& val);
 
    void setVecPredReg(PhysRegIdPtr reg_idx,
            const TheISA::VecPredRegContainer& val);
 
    void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
 
    RegVal readArchIntReg(int reg_idx, ThreadID tid);
 
    RegVal readArchFloatReg(int reg_idx, ThreadID tid);
 
    const TheISA::VecRegContainer&
        readArchVecReg(int reg_idx, ThreadID tid) const;
    TheISA::VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
 
    const TheISA::VecElem& readArchVecElem(const RegIndex& reg_idx,
            const ElemIndex& ldx, ThreadID tid) const;
 
    const TheISA::VecPredRegContainer& readArchVecPredReg(
            int reg_idx, ThreadID tid) const;
 
    TheISA::VecPredRegContainer&
        getWritableArchVecPredReg(int reg_idx, ThreadID tid);
 
    RegVal readArchCCReg(int reg_idx, ThreadID tid);
 
    void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
 
    void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
 
    void setArchVecPredReg(int reg_idx, const TheISA::VecPredRegContainer& val,
                           ThreadID tid);
 
    void setArchVecReg(int reg_idx, const TheISA::VecRegContainer& val,
            ThreadID tid);
 
    void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
                        const TheISA::VecElem& val, ThreadID tid);
 
    void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
 
    void pcState(const TheISA::PCState &newPCState, ThreadID tid);
 
    TheISA::PCState pcState(ThreadID tid);
 
    Addr instAddr(ThreadID tid);
 
    MicroPC microPC(ThreadID tid);
 
    Addr nextInstAddr(ThreadID tid);
 
    void squashFromTC(ThreadID tid);
 
    ListIt addInst(const DynInstPtr &inst);
 
    void instDone(ThreadID tid, const DynInstPtr &inst);
 
    void removeFrontInst(const DynInstPtr &inst);
 
    void removeInstsNotInROB(ThreadID tid);
 
    void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
 
    void squashInstIt(const ListIt &instIt, ThreadID tid);
 
    void cleanUpRemovedInsts();
 
    void dumpInsts();
 
  public:
#ifndef NDEBUG
 
    int instcount;
#endif
 
    std::list<DynInstPtr> instList;
 
    std::queue<ListIt> removeList;
 
#ifdef DEBUG
 
    std::set<InstSeqNum> snList;
#endif
 
    bool removeInstsThisCycle;
 
  protected:
    Fetch fetch;
 
    Decode decode;
 
    Rename rename;
 
    IEW iew;
 
    Commit commit;
 
    enums::VecRegRenameMode vecMode;
 
    PhysRegFile regFile;
 
    UnifiedFreeList freeList;
 
    UnifiedRenameMap renameMap[MaxThreads];
 
    UnifiedRenameMap commitRenameMap[MaxThreads];
 
    ROB rob;
 
    std::list<ThreadID> activeThreads;
 
    std::unordered_map<ThreadID, bool> exitingThreads;
 
    Scoreboard scoreboard;
 
    std::vector<TheISA::ISA *> isa;
 
  public:
    enum StageIdx
    {
        FetchIdx,
        DecodeIdx,
        RenameIdx,
        IEWIdx,
        CommitIdx,
        NumStages
    };
 
    TimeBuffer<TimeStruct> timeBuffer;
 
    TimeBuffer<FetchStruct> fetchQueue;
 
    TimeBuffer<DecodeStruct> decodeQueue;
 
    TimeBuffer<RenameStruct> renameQueue;
 
    TimeBuffer<IEWStruct> iewQueue;
 
  private:
    ActivityRecorder activityRec;
 
  public:
    void activityThisCycle() { activityRec.activity(); }
 
    void activateStage(const StageIdx idx)
    { activityRec.activateStage(idx); }
 
    void deactivateStage(const StageIdx idx)
    { activityRec.deactivateStage(idx); }
 
    void wakeCPU();
 
    virtual void wakeup(ThreadID tid) override;
 
    ThreadID getFreeTid();
 
  public:
    gem5::ThreadContext *
    tcBase(ThreadID tid)
    {
        return thread[tid]->getTC();
    }
 
    InstSeqNum globalSeqNum;//[MaxThreads];
 
    gem5::Checker<DynInstPtr> *checker;
 
    System *system;
 
    std::vector<ThreadState *> thread;
 
    std::list<int> cpuWaitList;
 
    Cycles lastRunningCycle;
 
    Tick lastActivatedCycle;
 
    std::map<ThreadID, unsigned> threadMap;
 
    std::vector<ThreadID> tids;
 
    Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
                      unsigned int size, Addr addr, Request::Flags flags,
                      uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr,
                      const std::vector<bool>& byte_enable =
                          std::vector<bool>())
 
    {
        return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
                flags, res, std::move(amo_op), byte_enable);
    }
 
    Fault read(LSQRequest* req, int load_idx)
    {
        return iew.ldstQueue.read(req, load_idx);
    }
 
    Fault write(LSQRequest* req, uint8_t *data, int store_idx)
    {
        return iew.ldstQueue.write(req, data, store_idx);
    }
 
    Port &
    getInstPort() override
    {
        return fetch.getInstPort();
    }
 
    Port &
    getDataPort() override
    {
        return iew.ldstQueue.getDataPort();
    }
 
    struct CPUStats : public statistics::Group
    {
        CPUStats(CPU *cpu);
 
        statistics::Scalar timesIdled;
        statistics::Scalar idleCycles;
        statistics::Scalar quiesceCycles;
        statistics::Vector committedInsts;
        statistics::Vector committedOps;
        statistics::Formula cpi;
        statistics::Formula totalCpi;
        statistics::Formula ipc;
        statistics::Formula totalIpc;
 
        //number of integer register file accesses
        statistics::Scalar intRegfileReads;
        statistics::Scalar intRegfileWrites;
        //number of float register file accesses
        statistics::Scalar fpRegfileReads;
        statistics::Scalar fpRegfileWrites;
        //number of vector register file accesses
        mutable statistics::Scalar vecRegfileReads;
        statistics::Scalar vecRegfileWrites;
        //number of predicate register file accesses
        mutable statistics::Scalar vecPredRegfileReads;
        statistics::Scalar vecPredRegfileWrites;
        //number of CC register file accesses
        statistics::Scalar ccRegfileReads;
        statistics::Scalar ccRegfileWrites;
        //number of misc
        statistics::Scalar miscRegfileReads;
        statistics::Scalar miscRegfileWrites;
    } cpuStats;
 
  public:
    // hardware transactional memory
    void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
                            HtmFailureFaultCause cause);
};
 
} // namespace o3
} // namespace gem5
 
#endif // __CPU_O3_CPU_HH__