fetch.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2010-2012, 2014 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __CPU_O3_FETCH_HH__
#define __CPU_O3_FETCH_HH__
 
#include "arch/decoder.hh"
#include "arch/generic/mmu.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/limits.hh"
#include "cpu/pc_event.hh"
#include "cpu/pred/bpred_unit.hh"
#include "cpu/timebuf.hh"
#include "cpu/translation.hh"
#include "enums/SMTFetchPolicy.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
 
namespace gem5
{
 
struct O3CPUParams;
 
namespace o3
{
 
class CPU;
 
class Fetch
{
  public:
    class IcachePort : public RequestPort
    {
      protected:
        Fetch *fetch;
 
      public:
        IcachePort(Fetch *_fetch, CPU *_cpu);
 
      protected:
 
        virtual bool recvTimingResp(PacketPtr pkt);
 
        virtual void recvReqRetry();
    };
 
    class FetchTranslation : public BaseMMU::Translation
    {
      protected:
        Fetch *fetch;
 
      public:
        FetchTranslation(Fetch *_fetch) : fetch(_fetch) {}
 
        void markDelayed() {}
 
        void
        finish(const Fault &fault, const RequestPtr &req,
            gem5::ThreadContext *tc, BaseMMU::Mode mode)
        {
            assert(mode == BaseMMU::Execute);
            fetch->finishTranslation(fault, req);
            delete this;
        }
    };
 
  private:
    /* Event to delay delivery of a fetch translation result in case of
     * a fault and the nop to carry the fault cannot be generated
     * immediately */
    class FinishTranslationEvent : public Event
    {
      private:
        Fetch *fetch;
        Fault fault;
        RequestPtr req;
 
      public:
        FinishTranslationEvent(Fetch *_fetch)
            : fetch(_fetch), req(nullptr)
        {}
 
        void setFault(Fault _fault) { fault = _fault; }
        void setReq(const RequestPtr &_req) { req = _req; }
 
        void
        process()
        {
            assert(fetch->numInst < fetch->fetchWidth);
            fetch->finishTranslation(fault, req);
        }
 
        const char *
        description() const
        {
            return "CPU FetchFinishTranslation";
        }
      };
 
  public:
    enum FetchStatus
    {
        Active,
        Inactive
    };
 
    enum ThreadStatus
    {
        Running,
        Idle,
        Squashing,
        Blocked,
        Fetching,
        TrapPending,
        QuiescePending,
        ItlbWait,
        IcacheWaitResponse,
        IcacheWaitRetry,
        IcacheAccessComplete,
        NoGoodAddr
    };
 
  private:
    FetchStatus _status;
 
    ThreadStatus fetchStatus[MaxThreads];
 
    SMTFetchPolicy fetchPolicy;
 
    std::list<ThreadID> priorityList;
 
    ProbePointArg<DynInstPtr> *ppFetch;
    ProbePointArg<RequestPtr> *ppFetchRequestSent;
 
  public:
    Fetch(CPU *_cpu, const O3CPUParams &params);
 
    std::string name() const;
 
 
    void regProbePoints();
 
    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
 
    void setActiveThreads(std::list<ThreadID> *at_ptr);
 
    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
 
    void startupStage();
 
    void clearStates(ThreadID tid);
 
    void recvReqRetry();
 
    void processCacheCompletion(PacketPtr pkt);
 
    void drainResume();
 
    void drainSanityCheck() const;
 
    bool isDrained() const;
 
    void takeOverFrom();
 
    void drainStall(ThreadID tid);
 
    void wakeFromQuiesce();
 
    void deactivateThread(ThreadID tid);
  private:
    void resetStage();
 
    void switchToActive();
 
    void switchToInactive();
 
    bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc);
 
    bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
    void finishTranslation(const Fault &fault, const RequestPtr &mem_req);
 
 
    bool checkInterrupt(Addr pc) { return interruptPending; }
 
    void doSquash(const TheISA::PCState &newPC,
            const DynInstPtr squashInst, ThreadID tid);
 
    void squashFromDecode(const TheISA::PCState &newPC,
                          const DynInstPtr squashInst,
                          const InstSeqNum seq_num, ThreadID tid);
 
    bool checkStall(ThreadID tid) const;
 
    FetchStatus updateFetchStatus();
 
  public:
    void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
                DynInstPtr squashInst, ThreadID tid);
 
    void tick();
 
    bool checkSignalsAndUpdate(ThreadID tid);
 
    void fetch(bool &status_change);
 
    Addr fetchBufferAlignPC(Addr addr)
    {
        return (addr & ~(fetchBufferMask));
    }
 
    TheISA::Decoder *decoder[MaxThreads];
 
    RequestPort &getInstPort() { return icachePort; }
 
  private:
    DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
            StaticInstPtr curMacroop, TheISA::PCState thisPC,
            TheISA::PCState nextPC, bool trace);
 
    ThreadID getFetchingThread();
 
    ThreadID roundRobin();
 
    ThreadID iqCount();
 
    ThreadID lsqCount();
 
    ThreadID branchCount();
 
    void pipelineIcacheAccesses(ThreadID tid);
 
    void profileStall(ThreadID tid);
 
  private:
    CPU *cpu;
 
    TimeBuffer<TimeStruct> *timeBuffer;
 
    TimeBuffer<TimeStruct>::wire fromDecode;
 
    TimeBuffer<TimeStruct>::wire fromRename;
 
    TimeBuffer<TimeStruct>::wire fromIEW;
 
    TimeBuffer<TimeStruct>::wire fromCommit;
 
    //Might be annoying how this name is different than the queue.
    TimeBuffer<FetchStruct>::wire toDecode;
 
    branch_prediction::BPredUnit *branchPred;
 
    TheISA::PCState pc[MaxThreads];
 
    Addr fetchOffset[MaxThreads];
 
    StaticInstPtr macroop[MaxThreads];
 
    bool delayedCommit[MaxThreads];
 
    RequestPtr memReq[MaxThreads];
 
    bool wroteToTimeBuffer;
 
    int numInst;
 
    struct Stalls
    {
        bool decode;
        bool drain;
    };
 
    Stalls stalls[MaxThreads];
 
    Cycles decodeToFetchDelay;
 
    Cycles renameToFetchDelay;
 
    Cycles iewToFetchDelay;
 
    Cycles commitToFetchDelay;
 
    unsigned fetchWidth;
 
    unsigned decodeWidth;
 
    bool cacheBlocked;
 
    PacketPtr retryPkt;
 
    ThreadID retryTid;
 
    unsigned int cacheBlkSize;
 
    unsigned fetchBufferSize;
 
    Addr fetchBufferMask;
 
    uint8_t *fetchBuffer[MaxThreads];
 
    Addr fetchBufferPC[MaxThreads];
 
    unsigned fetchQueueSize;
 
    std::deque<DynInstPtr> fetchQueue[MaxThreads];
 
    bool fetchBufferValid[MaxThreads];
 
    int instSize;
 
    Counter lastIcacheStall[MaxThreads];
 
    std::list<ThreadID> *activeThreads;
 
    ThreadID numThreads;
 
    ThreadID numFetchingThreads;
 
    ThreadID threadFetched;
 
    bool interruptPending;
 
    IcachePort icachePort;
 
    bool issuePipelinedIfetch[MaxThreads];
 
    FinishTranslationEvent finishTranslationEvent;
 
  protected:
    struct FetchStatGroup : public statistics::Group
    {
        FetchStatGroup(CPU *cpu, Fetch *fetch);
        // @todo: Consider making these
        // vectors and tracking on a per thread basis.
        statistics::Scalar icacheStallCycles;
        statistics::Scalar insts;
        statistics::Scalar branches;
        statistics::Scalar predictedBranches;
        statistics::Scalar cycles;
        statistics::Scalar squashCycles;
        statistics::Scalar tlbCycles;
        statistics::Scalar idleCycles;
        statistics::Scalar blockedCycles;
        statistics::Scalar miscStallCycles;
        statistics::Scalar pendingDrainCycles;
        statistics::Scalar noActiveThreadStallCycles;
        statistics::Scalar pendingTrapStallCycles;
        statistics::Scalar pendingQuiesceStallCycles;
        statistics::Scalar icacheWaitRetryStallCycles;
        statistics::Scalar cacheLines;
        statistics::Scalar icacheSquashes;
        statistics::Scalar tlbSquashes;
        statistics::Distribution nisnDist;
        statistics::Formula idleRate;
        statistics::Formula branchRate;
        statistics::Formula rate;
    } fetchStats;
};
 
} // namespace o3
} // namespace gem5
 
#endif //__CPU_O3_FETCH_HH__