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41 #ifndef __ARCH_ARM_DECODER_HH__
42 #define __ARCH_ARM_DECODER_HH__
52 #include "debug/Decode.hh"
53 #include "enums/DecoderFlavor.hh"
129 DPRINTF(Decode,
"Decode: Decoded %s instruction: %#x\n",
130 si->getName(), mach_inst);
226 #endif // __ARCH_ARM_DECODER_HH__
StaticInstPtr decodeInst(ExtMachInst mach_inst)
Decode a machine instruction without calling the cache.
void takeOverFrom(Decoder *old)
Take over the state from an old decoder when switching CPUs.
void setContext(FPSCR fpscr)
bool needMoreBytes() const
Can the decoder accept more data?
void setSveLen(uint8_t len)
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
void moreBytes(const PCState &pc, Addr fetchPC)
Feed data to the decoder.
bool instReady() const
Is an instruction ready to be decoded?
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
GenericISA::DelaySlotPCState< 4 > PCState
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
enums::DecoderFlavor decoderFlavor
void process()
Pre-decode an instruction from the current state of the decoder.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
void reset()
Reset the decoders internal state.
Decoder(ISA *isa=nullptr)
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
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