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misc.cc
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1 /*
2  * Copyright (c) 2010-2013, 2015-2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
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9  * licensed hereunder. You may use the software subject to the license
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17  * notice, this list of conditions and the following disclaimer;
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23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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36  */
37 
38 #include "arch/arm/regs/misc.hh"
39 
40 #include <tuple>
41 
42 #include "arch/arm/isa.hh"
43 #include "base/logging.hh"
44 #include "cpu/thread_context.hh"
45 #include "sim/full_system.hh"
46 
47 namespace gem5
48 {
49 
50 namespace ArmISA
51 {
52 
53 MiscRegIndex
54 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
55 {
56  switch(crn) {
57  case 0:
58  switch (opc1) {
59  case 0:
60  switch (opc2) {
61  case 0:
62  switch (crm) {
63  case 0:
64  return MISCREG_DBGDIDR;
65  case 1:
66  return MISCREG_DBGDSCRint;
67  case 7:
68  return MISCREG_DBGVCR;
69  }
70  break;
71  case 2:
72  switch (crm) {
73  case 0:
74  return MISCREG_DBGDTRRXext;
75  case 2:
76  return MISCREG_DBGDSCRext;
77  case 3:
78  return MISCREG_DBGDTRTXext;
79  case 6:
80  return MISCREG_DBGOSECCR;
81  }
82  break;
83  case 4:
84  switch (crm) {
85  case 0:
86  return MISCREG_DBGBVR0;
87  case 1:
88  return MISCREG_DBGBVR1;
89  case 2:
90  return MISCREG_DBGBVR2;
91  case 3:
92  return MISCREG_DBGBVR3;
93  case 4:
94  return MISCREG_DBGBVR4;
95  case 5:
96  return MISCREG_DBGBVR5;
97  case 6:
98  return MISCREG_DBGBVR6;
99  case 7:
100  return MISCREG_DBGBVR7;
101  case 8:
102  return MISCREG_DBGBVR8;
103  case 9:
104  return MISCREG_DBGBVR9;
105  case 10:
106  return MISCREG_DBGBVR10;
107  case 11:
108  return MISCREG_DBGBVR11;
109  case 12:
110  return MISCREG_DBGBVR12;
111  case 13:
112  return MISCREG_DBGBVR13;
113  case 14:
114  return MISCREG_DBGBVR14;
115  case 15:
116  return MISCREG_DBGBVR15;
117  }
118  break;
119  case 5:
120  switch (crm) {
121  case 0:
122  return MISCREG_DBGBCR0;
123  case 1:
124  return MISCREG_DBGBCR1;
125  case 2:
126  return MISCREG_DBGBCR2;
127  case 3:
128  return MISCREG_DBGBCR3;
129  case 4:
130  return MISCREG_DBGBCR4;
131  case 5:
132  return MISCREG_DBGBCR5;
133  case 6:
134  return MISCREG_DBGBCR6;
135  case 7:
136  return MISCREG_DBGBCR7;
137  case 8:
138  return MISCREG_DBGBCR8;
139  case 9:
140  return MISCREG_DBGBCR9;
141  case 10:
142  return MISCREG_DBGBCR10;
143  case 11:
144  return MISCREG_DBGBCR11;
145  case 12:
146  return MISCREG_DBGBCR12;
147  case 13:
148  return MISCREG_DBGBCR13;
149  case 14:
150  return MISCREG_DBGBCR14;
151  case 15:
152  return MISCREG_DBGBCR15;
153  }
154  break;
155  case 6:
156  switch (crm) {
157  case 0:
158  return MISCREG_DBGWVR0;
159  case 1:
160  return MISCREG_DBGWVR1;
161  case 2:
162  return MISCREG_DBGWVR2;
163  case 3:
164  return MISCREG_DBGWVR3;
165  case 4:
166  return MISCREG_DBGWVR4;
167  case 5:
168  return MISCREG_DBGWVR5;
169  case 6:
170  return MISCREG_DBGWVR6;
171  case 7:
172  return MISCREG_DBGWVR7;
173  case 8:
174  return MISCREG_DBGWVR8;
175  case 9:
176  return MISCREG_DBGWVR9;
177  case 10:
178  return MISCREG_DBGWVR10;
179  case 11:
180  return MISCREG_DBGWVR11;
181  case 12:
182  return MISCREG_DBGWVR12;
183  case 13:
184  return MISCREG_DBGWVR13;
185  case 14:
186  return MISCREG_DBGWVR14;
187  case 15:
188  return MISCREG_DBGWVR15;
189  break;
190  }
191  break;
192  case 7:
193  switch (crm) {
194  case 0:
195  return MISCREG_DBGWCR0;
196  case 1:
197  return MISCREG_DBGWCR1;
198  case 2:
199  return MISCREG_DBGWCR2;
200  case 3:
201  return MISCREG_DBGWCR3;
202  case 4:
203  return MISCREG_DBGWCR4;
204  case 5:
205  return MISCREG_DBGWCR5;
206  case 6:
207  return MISCREG_DBGWCR6;
208  case 7:
209  return MISCREG_DBGWCR7;
210  case 8:
211  return MISCREG_DBGWCR8;
212  case 9:
213  return MISCREG_DBGWCR9;
214  case 10:
215  return MISCREG_DBGWCR10;
216  case 11:
217  return MISCREG_DBGWCR11;
218  case 12:
219  return MISCREG_DBGWCR12;
220  case 13:
221  return MISCREG_DBGWCR13;
222  case 14:
223  return MISCREG_DBGWCR14;
224  case 15:
225  return MISCREG_DBGWCR15;
226  }
227  break;
228  }
229  break;
230  case 7:
231  switch (opc2) {
232  case 0:
233  switch (crm) {
234  case 0:
235  return MISCREG_JIDR;
236  }
237  break;
238  }
239  break;
240  }
241  break;
242  case 1:
243  switch (opc1) {
244  case 0:
245  switch(opc2) {
246  case 1:
247  switch(crm) {
248  case 0:
249  return MISCREG_DBGBXVR0;
250  case 1:
251  return MISCREG_DBGBXVR1;
252  case 2:
253  return MISCREG_DBGBXVR2;
254  case 3:
255  return MISCREG_DBGBXVR3;
256  case 4:
257  return MISCREG_DBGBXVR4;
258  case 5:
259  return MISCREG_DBGBXVR5;
260  case 6:
261  return MISCREG_DBGBXVR6;
262  case 7:
263  return MISCREG_DBGBXVR7;
264  case 8:
265  return MISCREG_DBGBXVR8;
266  case 9:
267  return MISCREG_DBGBXVR9;
268  case 10:
269  return MISCREG_DBGBXVR10;
270  case 11:
271  return MISCREG_DBGBXVR11;
272  case 12:
273  return MISCREG_DBGBXVR12;
274  case 13:
275  return MISCREG_DBGBXVR13;
276  case 14:
277  return MISCREG_DBGBXVR14;
278  case 15:
279  return MISCREG_DBGBXVR15;
280  }
281  break;
282  case 4:
283  switch (crm) {
284  case 0:
285  return MISCREG_DBGOSLAR;
286  case 1:
287  return MISCREG_DBGOSLSR;
288  case 3:
289  return MISCREG_DBGOSDLR;
290  case 4:
291  return MISCREG_DBGPRCR;
292  }
293  break;
294  }
295  break;
296  case 6:
297  switch (crm) {
298  case 0:
299  switch (opc2) {
300  case 0:
301  return MISCREG_TEEHBR;
302  }
303  break;
304  }
305  break;
306  case 7:
307  switch (crm) {
308  case 0:
309  switch (opc2) {
310  case 0:
311  return MISCREG_JOSCR;
312  }
313  break;
314  }
315  break;
316  }
317  break;
318  case 2:
319  switch (opc1) {
320  case 7:
321  switch (crm) {
322  case 0:
323  switch (opc2) {
324  case 0:
325  return MISCREG_JMCR;
326  }
327  break;
328  }
329  break;
330  }
331  break;
332  }
333  // If we get here then it must be a register that we haven't implemented
334  warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
335  crn, opc1, crm, opc2);
336  return MISCREG_CP14_UNIMPL;
337 }
338 
339 MiscRegIndex
340 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
341 {
342  switch (crn) {
343  case 0:
344  switch (opc1) {
345  case 0:
346  switch (crm) {
347  case 0:
348  switch (opc2) {
349  case 1:
350  return MISCREG_CTR;
351  case 2:
352  return MISCREG_TCMTR;
353  case 3:
354  return MISCREG_TLBTR;
355  case 5:
356  return MISCREG_MPIDR;
357  case 6:
358  return MISCREG_REVIDR;
359  default:
360  return MISCREG_MIDR;
361  }
362  break;
363  case 1:
364  switch (opc2) {
365  case 0:
366  return MISCREG_ID_PFR0;
367  case 1:
368  return MISCREG_ID_PFR1;
369  case 2:
370  return MISCREG_ID_DFR0;
371  case 3:
372  return MISCREG_ID_AFR0;
373  case 4:
374  return MISCREG_ID_MMFR0;
375  case 5:
376  return MISCREG_ID_MMFR1;
377  case 6:
378  return MISCREG_ID_MMFR2;
379  case 7:
380  return MISCREG_ID_MMFR3;
381  }
382  break;
383  case 2:
384  switch (opc2) {
385  case 0:
386  return MISCREG_ID_ISAR0;
387  case 1:
388  return MISCREG_ID_ISAR1;
389  case 2:
390  return MISCREG_ID_ISAR2;
391  case 3:
392  return MISCREG_ID_ISAR3;
393  case 4:
394  return MISCREG_ID_ISAR4;
395  case 5:
396  return MISCREG_ID_ISAR5;
397  case 6:
398  return MISCREG_ID_MMFR4;
399  case 7:
400  return MISCREG_ID_ISAR6;
401  }
402  break;
403  default:
404  return MISCREG_RAZ; // read as zero
405  }
406  break;
407  case 1:
408  if (crm == 0) {
409  switch (opc2) {
410  case 0:
411  return MISCREG_CCSIDR;
412  case 1:
413  return MISCREG_CLIDR;
414  case 7:
415  return MISCREG_AIDR;
416  }
417  }
418  break;
419  case 2:
420  if (crm == 0 && opc2 == 0) {
421  return MISCREG_CSSELR;
422  }
423  break;
424  case 4:
425  if (crm == 0) {
426  if (opc2 == 0)
427  return MISCREG_VPIDR;
428  else if (opc2 == 5)
429  return MISCREG_VMPIDR;
430  }
431  break;
432  }
433  break;
434  case 1:
435  if (opc1 == 0) {
436  if (crm == 0) {
437  switch (opc2) {
438  case 0:
439  return MISCREG_SCTLR;
440  case 1:
441  return MISCREG_ACTLR;
442  case 0x2:
443  return MISCREG_CPACR;
444  }
445  } else if (crm == 1) {
446  switch (opc2) {
447  case 0:
448  return MISCREG_SCR;
449  case 1:
450  return MISCREG_SDER;
451  case 2:
452  return MISCREG_NSACR;
453  }
454  } else if (crm == 3) {
455  if ( opc2 == 1)
456  return MISCREG_SDCR;
457  }
458  } else if (opc1 == 4) {
459  if (crm == 0) {
460  if (opc2 == 0)
461  return MISCREG_HSCTLR;
462  else if (opc2 == 1)
463  return MISCREG_HACTLR;
464  } else if (crm == 1) {
465  switch (opc2) {
466  case 0:
467  return MISCREG_HCR;
468  case 1:
469  return MISCREG_HDCR;
470  case 2:
471  return MISCREG_HCPTR;
472  case 4:
473  return MISCREG_HCR2;
474  case 3:
475  return MISCREG_HSTR;
476  case 7:
477  return MISCREG_HACR;
478  }
479  }
480  }
481  break;
482  case 2:
483  if (opc1 == 0 && crm == 0) {
484  switch (opc2) {
485  case 0:
486  return MISCREG_TTBR0;
487  case 1:
488  return MISCREG_TTBR1;
489  case 2:
490  return MISCREG_TTBCR;
491  }
492  } else if (opc1 == 4) {
493  if (crm == 0 && opc2 == 2)
494  return MISCREG_HTCR;
495  else if (crm == 1 && opc2 == 2)
496  return MISCREG_VTCR;
497  }
498  break;
499  case 3:
500  if (opc1 == 0 && crm == 0 && opc2 == 0) {
501  return MISCREG_DACR;
502  }
503  break;
504  case 4:
505  if (opc1 == 0 && crm == 6 && opc2 == 0) {
506  return MISCREG_ICC_PMR;
507  }
508  break;
509  case 5:
510  if (opc1 == 0) {
511  if (crm == 0) {
512  if (opc2 == 0) {
513  return MISCREG_DFSR;
514  } else if (opc2 == 1) {
515  return MISCREG_IFSR;
516  }
517  } else if (crm == 1) {
518  if (opc2 == 0) {
519  return MISCREG_ADFSR;
520  } else if (opc2 == 1) {
521  return MISCREG_AIFSR;
522  }
523  }
524  } else if (opc1 == 4) {
525  if (crm == 1) {
526  if (opc2 == 0)
527  return MISCREG_HADFSR;
528  else if (opc2 == 1)
529  return MISCREG_HAIFSR;
530  } else if (crm == 2 && opc2 == 0) {
531  return MISCREG_HSR;
532  }
533  }
534  break;
535  case 6:
536  if (opc1 == 0 && crm == 0) {
537  switch (opc2) {
538  case 0:
539  return MISCREG_DFAR;
540  case 2:
541  return MISCREG_IFAR;
542  }
543  } else if (opc1 == 4 && crm == 0) {
544  switch (opc2) {
545  case 0:
546  return MISCREG_HDFAR;
547  case 2:
548  return MISCREG_HIFAR;
549  case 4:
550  return MISCREG_HPFAR;
551  }
552  }
553  break;
554  case 7:
555  if (opc1 == 0) {
556  switch (crm) {
557  case 0:
558  if (opc2 == 4) {
559  return MISCREG_NOP;
560  }
561  break;
562  case 1:
563  switch (opc2) {
564  case 0:
565  return MISCREG_ICIALLUIS;
566  case 6:
567  return MISCREG_BPIALLIS;
568  }
569  break;
570  case 2:
571  switch (opc2) {
572  case 7:
573  return MISCREG_DBGDEVID0;
574  }
575  break;
576  case 4:
577  if (opc2 == 0) {
578  return MISCREG_PAR;
579  }
580  break;
581  case 5:
582  switch (opc2) {
583  case 0:
584  return MISCREG_ICIALLU;
585  case 1:
586  return MISCREG_ICIMVAU;
587  case 4:
588  return MISCREG_CP15ISB;
589  case 6:
590  return MISCREG_BPIALL;
591  case 7:
592  return MISCREG_BPIMVA;
593  }
594  break;
595  case 6:
596  if (opc2 == 1) {
597  return MISCREG_DCIMVAC;
598  } else if (opc2 == 2) {
599  return MISCREG_DCISW;
600  }
601  break;
602  case 8:
603  switch (opc2) {
604  case 0:
605  return MISCREG_ATS1CPR;
606  case 1:
607  return MISCREG_ATS1CPW;
608  case 2:
609  return MISCREG_ATS1CUR;
610  case 3:
611  return MISCREG_ATS1CUW;
612  case 4:
613  return MISCREG_ATS12NSOPR;
614  case 5:
615  return MISCREG_ATS12NSOPW;
616  case 6:
617  return MISCREG_ATS12NSOUR;
618  case 7:
619  return MISCREG_ATS12NSOUW;
620  }
621  break;
622  case 10:
623  switch (opc2) {
624  case 1:
625  return MISCREG_DCCMVAC;
626  case 2:
627  return MISCREG_DCCSW;
628  case 4:
629  return MISCREG_CP15DSB;
630  case 5:
631  return MISCREG_CP15DMB;
632  }
633  break;
634  case 11:
635  if (opc2 == 1) {
636  return MISCREG_DCCMVAU;
637  }
638  break;
639  case 13:
640  if (opc2 == 1) {
641  return MISCREG_NOP;
642  }
643  break;
644  case 14:
645  if (opc2 == 1) {
646  return MISCREG_DCCIMVAC;
647  } else if (opc2 == 2) {
648  return MISCREG_DCCISW;
649  }
650  break;
651  }
652  } else if (opc1 == 4 && crm == 8) {
653  if (opc2 == 0)
654  return MISCREG_ATS1HR;
655  else if (opc2 == 1)
656  return MISCREG_ATS1HW;
657  }
658  break;
659  case 8:
660  if (opc1 == 0) {
661  switch (crm) {
662  case 3:
663  switch (opc2) {
664  case 0:
665  return MISCREG_TLBIALLIS;
666  case 1:
667  return MISCREG_TLBIMVAIS;
668  case 2:
669  return MISCREG_TLBIASIDIS;
670  case 3:
671  return MISCREG_TLBIMVAAIS;
672  case 5:
673  return MISCREG_TLBIMVALIS;
674  case 7:
675  return MISCREG_TLBIMVAALIS;
676  }
677  break;
678  case 5:
679  switch (opc2) {
680  case 0:
681  return MISCREG_ITLBIALL;
682  case 1:
683  return MISCREG_ITLBIMVA;
684  case 2:
685  return MISCREG_ITLBIASID;
686  }
687  break;
688  case 6:
689  switch (opc2) {
690  case 0:
691  return MISCREG_DTLBIALL;
692  case 1:
693  return MISCREG_DTLBIMVA;
694  case 2:
695  return MISCREG_DTLBIASID;
696  }
697  break;
698  case 7:
699  switch (opc2) {
700  case 0:
701  return MISCREG_TLBIALL;
702  case 1:
703  return MISCREG_TLBIMVA;
704  case 2:
705  return MISCREG_TLBIASID;
706  case 3:
707  return MISCREG_TLBIMVAA;
708  case 5:
709  return MISCREG_TLBIMVAL;
710  case 7:
711  return MISCREG_TLBIMVAAL;
712  }
713  break;
714  }
715  } else if (opc1 == 4) {
716  if (crm == 0) {
717  switch (opc2) {
718  case 1:
719  return MISCREG_TLBIIPAS2IS;
720  case 5:
721  return MISCREG_TLBIIPAS2LIS;
722  }
723  } else if (crm == 3) {
724  switch (opc2) {
725  case 0:
726  return MISCREG_TLBIALLHIS;
727  case 1:
728  return MISCREG_TLBIMVAHIS;
729  case 4:
730  return MISCREG_TLBIALLNSNHIS;
731  case 5:
732  return MISCREG_TLBIMVALHIS;
733  }
734  } else if (crm == 4) {
735  switch (opc2) {
736  case 1:
737  return MISCREG_TLBIIPAS2;
738  case 5:
739  return MISCREG_TLBIIPAS2L;
740  }
741  } else if (crm == 7) {
742  switch (opc2) {
743  case 0:
744  return MISCREG_TLBIALLH;
745  case 1:
746  return MISCREG_TLBIMVAH;
747  case 4:
748  return MISCREG_TLBIALLNSNH;
749  case 5:
750  return MISCREG_TLBIMVALH;
751  }
752  }
753  }
754  break;
755  case 9:
756  // Every cop register with CRn = 9 and CRm in
757  // {0-2}, {5-8} is implementation defined regardless
758  // of opc1 and opc2.
759  switch (crm) {
760  case 0:
761  case 1:
762  case 2:
763  case 5:
764  case 6:
765  case 7:
766  case 8:
767  return MISCREG_IMPDEF_UNIMPL;
768  }
769  if (opc1 == 0) {
770  switch (crm) {
771  case 12:
772  switch (opc2) {
773  case 0:
774  return MISCREG_PMCR;
775  case 1:
776  return MISCREG_PMCNTENSET;
777  case 2:
778  return MISCREG_PMCNTENCLR;
779  case 3:
780  return MISCREG_PMOVSR;
781  case 4:
782  return MISCREG_PMSWINC;
783  case 5:
784  return MISCREG_PMSELR;
785  case 6:
786  return MISCREG_PMCEID0;
787  case 7:
788  return MISCREG_PMCEID1;
789  }
790  break;
791  case 13:
792  switch (opc2) {
793  case 0:
794  return MISCREG_PMCCNTR;
795  case 1:
796  // Selector is PMSELR.SEL
797  return MISCREG_PMXEVTYPER_PMCCFILTR;
798  case 2:
799  return MISCREG_PMXEVCNTR;
800  }
801  break;
802  case 14:
803  switch (opc2) {
804  case 0:
805  return MISCREG_PMUSERENR;
806  case 1:
807  return MISCREG_PMINTENSET;
808  case 2:
809  return MISCREG_PMINTENCLR;
810  case 3:
811  return MISCREG_PMOVSSET;
812  }
813  break;
814  }
815  } else if (opc1 == 1) {
816  switch (crm) {
817  case 0:
818  switch (opc2) {
819  case 2: // L2CTLR, L2 Control Register
820  return MISCREG_L2CTLR;
821  case 3:
822  return MISCREG_L2ECTLR;
823  }
824  break;
825  break;
826  }
827  }
828  break;
829  case 10:
830  if (opc1 == 0) {
831  // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
832  if (crm < 2) {
833  return MISCREG_IMPDEF_UNIMPL;
834  } else if (crm == 2) { // TEX Remap Registers
835  if (opc2 == 0) {
836  // Selector is TTBCR.EAE
837  return MISCREG_PRRR_MAIR0;
838  } else if (opc2 == 1) {
839  // Selector is TTBCR.EAE
840  return MISCREG_NMRR_MAIR1;
841  }
842  } else if (crm == 3) {
843  if (opc2 == 0) {
844  return MISCREG_AMAIR0;
845  } else if (opc2 == 1) {
846  return MISCREG_AMAIR1;
847  }
848  }
849  } else if (opc1 == 4) {
850  // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
851  if (crm == 2) {
852  if (opc2 == 0)
853  return MISCREG_HMAIR0;
854  else if (opc2 == 1)
855  return MISCREG_HMAIR1;
856  } else if (crm == 3) {
857  if (opc2 == 0)
858  return MISCREG_HAMAIR0;
859  else if (opc2 == 1)
860  return MISCREG_HAMAIR1;
861  }
862  }
863  break;
864  case 11:
865  if (opc1 <=7) {
866  switch (crm) {
867  case 0:
868  case 1:
869  case 2:
870  case 3:
871  case 4:
872  case 5:
873  case 6:
874  case 7:
875  case 8:
876  case 15:
877  // Reserved for DMA operations for TCM access
878  return MISCREG_IMPDEF_UNIMPL;
879  default:
880  break;
881  }
882  }
883  break;
884  case 12:
885  if (opc1 == 0) {
886  if (crm == 0) {
887  if (opc2 == 0) {
888  return MISCREG_VBAR;
889  } else if (opc2 == 1) {
890  return MISCREG_MVBAR;
891  }
892  } else if (crm == 1) {
893  if (opc2 == 0) {
894  return MISCREG_ISR;
895  }
896  } else if (crm == 8) {
897  switch (opc2) {
898  case 0:
899  return MISCREG_ICC_IAR0;
900  case 1:
901  return MISCREG_ICC_EOIR0;
902  case 2:
903  return MISCREG_ICC_HPPIR0;
904  case 3:
905  return MISCREG_ICC_BPR0;
906  case 4:
907  return MISCREG_ICC_AP0R0;
908  case 5:
909  return MISCREG_ICC_AP0R1;
910  case 6:
911  return MISCREG_ICC_AP0R2;
912  case 7:
913  return MISCREG_ICC_AP0R3;
914  }
915  } else if (crm == 9) {
916  switch (opc2) {
917  case 0:
918  return MISCREG_ICC_AP1R0;
919  case 1:
920  return MISCREG_ICC_AP1R1;
921  case 2:
922  return MISCREG_ICC_AP1R2;
923  case 3:
924  return MISCREG_ICC_AP1R3;
925  }
926  } else if (crm == 11) {
927  switch (opc2) {
928  case 1:
929  return MISCREG_ICC_DIR;
930  case 3:
931  return MISCREG_ICC_RPR;
932  }
933  } else if (crm == 12) {
934  switch (opc2) {
935  case 0:
936  return MISCREG_ICC_IAR1;
937  case 1:
938  return MISCREG_ICC_EOIR1;
939  case 2:
940  return MISCREG_ICC_HPPIR1;
941  case 3:
942  return MISCREG_ICC_BPR1;
943  case 4:
944  return MISCREG_ICC_CTLR;
945  case 5:
946  return MISCREG_ICC_SRE;
947  case 6:
948  return MISCREG_ICC_IGRPEN0;
949  case 7:
950  return MISCREG_ICC_IGRPEN1;
951  }
952  }
953  } else if (opc1 == 4) {
954  if (crm == 0 && opc2 == 0) {
955  return MISCREG_HVBAR;
956  } else if (crm == 8) {
957  switch (opc2) {
958  case 0:
959  return MISCREG_ICH_AP0R0;
960  case 1:
961  return MISCREG_ICH_AP0R1;
962  case 2:
963  return MISCREG_ICH_AP0R2;
964  case 3:
965  return MISCREG_ICH_AP0R3;
966  }
967  } else if (crm == 9) {
968  switch (opc2) {
969  case 0:
970  return MISCREG_ICH_AP1R0;
971  case 1:
972  return MISCREG_ICH_AP1R1;
973  case 2:
974  return MISCREG_ICH_AP1R2;
975  case 3:
976  return MISCREG_ICH_AP1R3;
977  case 5:
978  return MISCREG_ICC_HSRE;
979  }
980  } else if (crm == 11) {
981  switch (opc2) {
982  case 0:
983  return MISCREG_ICH_HCR;
984  case 1:
985  return MISCREG_ICH_VTR;
986  case 2:
987  return MISCREG_ICH_MISR;
988  case 3:
989  return MISCREG_ICH_EISR;
990  case 5:
991  return MISCREG_ICH_ELRSR;
992  case 7:
993  return MISCREG_ICH_VMCR;
994  }
995  } else if (crm == 12) {
996  switch (opc2) {
997  case 0:
998  return MISCREG_ICH_LR0;
999  case 1:
1000  return MISCREG_ICH_LR1;
1001  case 2:
1002  return MISCREG_ICH_LR2;
1003  case 3:
1004  return MISCREG_ICH_LR3;
1005  case 4:
1006  return MISCREG_ICH_LR4;
1007  case 5:
1008  return MISCREG_ICH_LR5;
1009  case 6:
1010  return MISCREG_ICH_LR6;
1011  case 7:
1012  return MISCREG_ICH_LR7;
1013  }
1014  } else if (crm == 13) {
1015  switch (opc2) {
1016  case 0:
1017  return MISCREG_ICH_LR8;
1018  case 1:
1019  return MISCREG_ICH_LR9;
1020  case 2:
1021  return MISCREG_ICH_LR10;
1022  case 3:
1023  return MISCREG_ICH_LR11;
1024  case 4:
1025  return MISCREG_ICH_LR12;
1026  case 5:
1027  return MISCREG_ICH_LR13;
1028  case 6:
1029  return MISCREG_ICH_LR14;
1030  case 7:
1031  return MISCREG_ICH_LR15;
1032  }
1033  } else if (crm == 14) {
1034  switch (opc2) {
1035  case 0:
1036  return MISCREG_ICH_LRC0;
1037  case 1:
1038  return MISCREG_ICH_LRC1;
1039  case 2:
1040  return MISCREG_ICH_LRC2;
1041  case 3:
1042  return MISCREG_ICH_LRC3;
1043  case 4:
1044  return MISCREG_ICH_LRC4;
1045  case 5:
1046  return MISCREG_ICH_LRC5;
1047  case 6:
1048  return MISCREG_ICH_LRC6;
1049  case 7:
1050  return MISCREG_ICH_LRC7;
1051  }
1052  } else if (crm == 15) {
1053  switch (opc2) {
1054  case 0:
1055  return MISCREG_ICH_LRC8;
1056  case 1:
1057  return MISCREG_ICH_LRC9;
1058  case 2:
1059  return MISCREG_ICH_LRC10;
1060  case 3:
1061  return MISCREG_ICH_LRC11;
1062  case 4:
1063  return MISCREG_ICH_LRC12;
1064  case 5:
1065  return MISCREG_ICH_LRC13;
1066  case 6:
1067  return MISCREG_ICH_LRC14;
1068  case 7:
1069  return MISCREG_ICH_LRC15;
1070  }
1071  }
1072  } else if (opc1 == 6) {
1073  if (crm == 12) {
1074  switch (opc2) {
1075  case 4:
1076  return MISCREG_ICC_MCTLR;
1077  case 5:
1078  return MISCREG_ICC_MSRE;
1079  case 7:
1080  return MISCREG_ICC_MGRPEN1;
1081  }
1082  }
1083  }
1084  break;
1085  case 13:
1086  if (opc1 == 0) {
1087  if (crm == 0) {
1088  switch (opc2) {
1089  case 0:
1090  return MISCREG_FCSEIDR;
1091  case 1:
1092  return MISCREG_CONTEXTIDR;
1093  case 2:
1094  return MISCREG_TPIDRURW;
1095  case 3:
1096  return MISCREG_TPIDRURO;
1097  case 4:
1098  return MISCREG_TPIDRPRW;
1099  }
1100  }
1101  } else if (opc1 == 4) {
1102  if (crm == 0 && opc2 == 2)
1103  return MISCREG_HTPIDR;
1104  }
1105  break;
1106  case 14:
1107  if (opc1 == 0) {
1108  switch (crm) {
1109  case 0:
1110  if (opc2 == 0)
1111  return MISCREG_CNTFRQ;
1112  break;
1113  case 1:
1114  if (opc2 == 0)
1115  return MISCREG_CNTKCTL;
1116  break;
1117  case 2:
1118  if (opc2 == 0)
1119  return MISCREG_CNTP_TVAL;
1120  else if (opc2 == 1)
1121  return MISCREG_CNTP_CTL;
1122  break;
1123  case 3:
1124  if (opc2 == 0)
1125  return MISCREG_CNTV_TVAL;
1126  else if (opc2 == 1)
1127  return MISCREG_CNTV_CTL;
1128  break;
1129  }
1130  } else if (opc1 == 4) {
1131  if (crm == 1 && opc2 == 0) {
1132  return MISCREG_CNTHCTL;
1133  } else if (crm == 2) {
1134  if (opc2 == 0)
1135  return MISCREG_CNTHP_TVAL;
1136  else if (opc2 == 1)
1137  return MISCREG_CNTHP_CTL;
1138  }
1139  }
1140  break;
1141  case 15:
1142  // Implementation defined
1143  return MISCREG_IMPDEF_UNIMPL;
1144  }
1145  // Unrecognized register
1146  return MISCREG_CP15_UNIMPL;
1147 }
1148 
1149 MiscRegIndex
1150 decodeCP15Reg64(unsigned crm, unsigned opc1)
1151 {
1152  switch (crm) {
1153  case 2:
1154  switch (opc1) {
1155  case 0:
1156  return MISCREG_TTBR0;
1157  case 1:
1158  return MISCREG_TTBR1;
1159  case 4:
1160  return MISCREG_HTTBR;
1161  case 6:
1162  return MISCREG_VTTBR;
1163  }
1164  break;
1165  case 7:
1166  if (opc1 == 0)
1167  return MISCREG_PAR;
1168  break;
1169  case 14:
1170  switch (opc1) {
1171  case 0:
1172  return MISCREG_CNTPCT;
1173  case 1:
1174  return MISCREG_CNTVCT;
1175  case 2:
1176  return MISCREG_CNTP_CVAL;
1177  case 3:
1178  return MISCREG_CNTV_CVAL;
1179  case 4:
1180  return MISCREG_CNTVOFF;
1181  case 6:
1182  return MISCREG_CNTHP_CVAL;
1183  }
1184  break;
1185  case 12:
1186  switch (opc1) {
1187  case 0:
1188  return MISCREG_ICC_SGI1R;
1189  case 1:
1190  return MISCREG_ICC_ASGI1R;
1191  case 2:
1192  return MISCREG_ICC_SGI0R;
1193  default:
1194  break;
1195  }
1196  break;
1197  case 15:
1198  if (opc1 == 0)
1199  return MISCREG_CPUMERRSR;
1200  else if (opc1 == 1)
1201  return MISCREG_L2MERRSR;
1202  break;
1203  }
1204  // Unrecognized register
1205  return MISCREG_CP15_UNIMPL;
1206 }
1207 
1208 std::tuple<bool, bool>
1209 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1210 {
1211  bool secure = !scr.ns;
1212  bool canRead = false;
1213  bool undefined = false;
1214 
1215  switch (cpsr.mode) {
1216  case MODE_USER:
1217  canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1218  miscRegInfo[reg][MISCREG_USR_NS_RD];
1219  break;
1220  case MODE_FIQ:
1221  case MODE_IRQ:
1222  case MODE_SVC:
1223  case MODE_ABORT:
1224  case MODE_UNDEFINED:
1225  case MODE_SYSTEM:
1226  canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1227  miscRegInfo[reg][MISCREG_PRI_NS_RD];
1228  break;
1229  case MODE_MON:
1230  canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1231  miscRegInfo[reg][MISCREG_MON_NS1_RD];
1232  break;
1233  case MODE_HYP:
1234  canRead = miscRegInfo[reg][MISCREG_HYP_NS_RD];
1235  break;
1236  default:
1237  undefined = true;
1238  }
1239 
1240  switch (reg) {
1241  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
1242  if (!undefined)
1243  undefined = AArch32isUndefinedGenericTimer(reg, tc);
1244  break;
1245  default:
1246  break;
1247  }
1248 
1249  // can't do permissions checkes on the root of a banked pair of regs
1250  assert(!miscRegInfo[reg][MISCREG_BANKED]);
1251  return std::make_tuple(canRead, undefined);
1252 }
1253 
1254 std::tuple<bool, bool>
1255 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1256 {
1257  bool secure = !scr.ns;
1258  bool canWrite = false;
1259  bool undefined = false;
1260 
1261  switch (cpsr.mode) {
1262  case MODE_USER:
1263  canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1264  miscRegInfo[reg][MISCREG_USR_NS_WR];
1265  break;
1266  case MODE_FIQ:
1267  case MODE_IRQ:
1268  case MODE_SVC:
1269  case MODE_ABORT:
1270  case MODE_UNDEFINED:
1271  case MODE_SYSTEM:
1272  canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1273  miscRegInfo[reg][MISCREG_PRI_NS_WR];
1274  break;
1275  case MODE_MON:
1276  canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1277  miscRegInfo[reg][MISCREG_MON_NS1_WR];
1278  break;
1279  case MODE_HYP:
1280  canWrite = miscRegInfo[reg][MISCREG_HYP_NS_WR];
1281  break;
1282  default:
1283  undefined = true;
1284  }
1285 
1286  switch (reg) {
1287  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
1288  if (!undefined)
1289  undefined = AArch32isUndefinedGenericTimer(reg, tc);
1290  break;
1291  default:
1292  break;
1293  }
1294 
1295  // can't do permissions checkes on the root of a banked pair of regs
1296  assert(!miscRegInfo[reg][MISCREG_BANKED]);
1297  return std::make_tuple(canWrite, undefined);
1298 }
1299 
1300 bool
1301 AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
1302 {
1303  if (currEL(tc) == EL0 && ELIs32(tc, EL1)) {
1304  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1305  bool trap_cond = condGenericTimerSystemAccessTrapEL1(reg, tc);
1306  if (trap_cond && (!EL2Enabled(tc) || !hcr.tge))
1307  return true;
1308  }
1309  return false;
1310 }
1311 
1312 int
1313 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1314 {
1315  SCR scr = tc->readMiscReg(MISCREG_SCR);
1316  return snsBankedIndex(reg, tc, scr.ns);
1317 }
1318 
1319 int
1320 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1321 {
1322  int reg_as_int = static_cast<int>(reg);
1323  if (miscRegInfo[reg][MISCREG_BANKED]) {
1324  reg_as_int += (ArmSystem::haveSecurity(tc) &&
1325  !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1326  }
1327  return reg_as_int;
1328 }
1329 
1330 int
1331 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1332 {
1333  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
1334  SCR scr = tc->readMiscReg(MISCREG_SCR);
1335  return isa->snsBankedIndex64(reg, scr.ns);
1336 }
1337 
1346 int unflattenResultMiscReg[NUM_MISCREGS];
1347 
1348 void
1349 preUnflattenMiscReg()
1350 {
1351  int reg = -1;
1352  for (int i = 0 ; i < NUM_MISCREGS; i++){
1353  if (miscRegInfo[i][MISCREG_BANKED])
1354  reg = i;
1355  if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1356  unflattenResultMiscReg[i] = reg;
1357  else
1358  unflattenResultMiscReg[i] = i;
1359  // if this assert fails, no parent was found, and something is broken
1360  assert(unflattenResultMiscReg[i] > -1);
1361  }
1362 }
1363 
1364 int
1365 unflattenMiscReg(int reg)
1366 {
1367  return unflattenResultMiscReg[reg];
1368 }
1369 
1370 bool
1371 canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1372  ThreadContext *tc)
1373 {
1374  // Check for SP_EL0 access while SPSEL == 0
1375  if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1376  return false;
1377 
1378  // Check for RVBAR access
1379  if (reg == MISCREG_RVBAR_EL1) {
1380  ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1381  if (highest_el == EL2 || highest_el == EL3)
1382  return false;
1383  }
1384  if (reg == MISCREG_RVBAR_EL2) {
1385  ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1386  if (highest_el == EL3)
1387  return false;
1388  }
1389 
1390  bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1391  bool el2_host = EL2Enabled(tc) && hcr.e2h;
1392 
1393  switch (currEL(cpsr)) {
1394  case EL0:
1395  return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1396  miscRegInfo[reg][MISCREG_USR_NS_RD];
1397  case EL1:
1398  return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1399  miscRegInfo[reg][MISCREG_PRI_NS_RD];
1400  case EL2:
1401  if (el2_host) {
1402  return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_RD] :
1403  miscRegInfo[reg][MISCREG_HYP_E2H_NS_RD];
1404  } else {
1405  return secure ? miscRegInfo[reg][MISCREG_HYP_S_RD] :
1406  miscRegInfo[reg][MISCREG_HYP_NS_RD];
1407  }
1408  case EL3:
1409  return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
1410  secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1411  miscRegInfo[reg][MISCREG_MON_NS1_RD];
1412  default:
1413  panic("Invalid exception level");
1414  }
1415 }
1416 
1417 bool
1418 canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1419  ThreadContext *tc)
1420 {
1421  // Check for SP_EL0 access while SPSEL == 0
1422  if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1423  return false;
1424  ExceptionLevel el = currEL(cpsr);
1425 
1426  bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1427  bool el2_host = EL2Enabled(tc) && hcr.e2h;
1428 
1429  switch (el) {
1430  case EL0:
1431  return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1432  miscRegInfo[reg][MISCREG_USR_NS_WR];
1433  case EL1:
1434  return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1435  miscRegInfo[reg][MISCREG_PRI_NS_WR];
1436  case EL2:
1437  if (el2_host) {
1438  return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_WR] :
1439  miscRegInfo[reg][MISCREG_HYP_E2H_NS_WR];
1440  } else {
1441  return secure ? miscRegInfo[reg][MISCREG_HYP_S_WR] :
1442  miscRegInfo[reg][MISCREG_HYP_NS_WR];
1443  }
1444  case EL3:
1445  return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
1446  secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1447  miscRegInfo[reg][MISCREG_MON_NS1_WR];
1448  default:
1449  panic("Invalid exception level");
1450  }
1451 }
1452 
1453 MiscRegIndex
1454 decodeAArch64SysReg(unsigned op0, unsigned op1,
1455  unsigned crn, unsigned crm,
1456  unsigned op2)
1457 {
1458  switch (op0) {
1459  case 1:
1460  switch (crn) {
1461  case 7:
1462  switch (op1) {
1463  case 0:
1464  switch (crm) {
1465  case 1:
1466  switch (op2) {
1467  case 0:
1468  return MISCREG_IC_IALLUIS;
1469  }
1470  break;
1471  case 5:
1472  switch (op2) {
1473  case 0:
1474  return MISCREG_IC_IALLU;
1475  }
1476  break;
1477  case 6:
1478  switch (op2) {
1479  case 1:
1480  return MISCREG_DC_IVAC_Xt;
1481  case 2:
1482  return MISCREG_DC_ISW_Xt;
1483  }
1484  break;
1485  case 8:
1486  switch (op2) {
1487  case 0:
1488  return MISCREG_AT_S1E1R_Xt;
1489  case 1:
1490  return MISCREG_AT_S1E1W_Xt;
1491  case 2:
1492  return MISCREG_AT_S1E0R_Xt;
1493  case 3:
1494  return MISCREG_AT_S1E0W_Xt;
1495  }
1496  break;
1497  case 10:
1498  switch (op2) {
1499  case 2:
1500  return MISCREG_DC_CSW_Xt;
1501  }
1502  break;
1503  case 14:
1504  switch (op2) {
1505  case 2:
1506  return MISCREG_DC_CISW_Xt;
1507  }
1508  break;
1509  }
1510  break;
1511  case 3:
1512  switch (crm) {
1513  case 4:
1514  switch (op2) {
1515  case 1:
1516  return MISCREG_DC_ZVA_Xt;
1517  }
1518  break;
1519  case 5:
1520  switch (op2) {
1521  case 1:
1522  return MISCREG_IC_IVAU_Xt;
1523  }
1524  break;
1525  case 10:
1526  switch (op2) {
1527  case 1:
1528  return MISCREG_DC_CVAC_Xt;
1529  }
1530  break;
1531  case 11:
1532  switch (op2) {
1533  case 1:
1534  return MISCREG_DC_CVAU_Xt;
1535  }
1536  break;
1537  case 14:
1538  switch (op2) {
1539  case 1:
1540  return MISCREG_DC_CIVAC_Xt;
1541  }
1542  break;
1543  }
1544  break;
1545  case 4:
1546  switch (crm) {
1547  case 8:
1548  switch (op2) {
1549  case 0:
1550  return MISCREG_AT_S1E2R_Xt;
1551  case 1:
1552  return MISCREG_AT_S1E2W_Xt;
1553  case 4:
1554  return MISCREG_AT_S12E1R_Xt;
1555  case 5:
1556  return MISCREG_AT_S12E1W_Xt;
1557  case 6:
1558  return MISCREG_AT_S12E0R_Xt;
1559  case 7:
1560  return MISCREG_AT_S12E0W_Xt;
1561  }
1562  break;
1563  }
1564  break;
1565  case 6:
1566  switch (crm) {
1567  case 8:
1568  switch (op2) {
1569  case 0:
1570  return MISCREG_AT_S1E3R_Xt;
1571  case 1:
1572  return MISCREG_AT_S1E3W_Xt;
1573  }
1574  break;
1575  }
1576  break;
1577  }
1578  break;
1579  case 8:
1580  switch (op1) {
1581  case 0:
1582  switch (crm) {
1583  case 3:
1584  switch (op2) {
1585  case 0:
1586  return MISCREG_TLBI_VMALLE1IS;
1587  case 1:
1588  return MISCREG_TLBI_VAE1IS_Xt;
1589  case 2:
1590  return MISCREG_TLBI_ASIDE1IS_Xt;
1591  case 3:
1592  return MISCREG_TLBI_VAAE1IS_Xt;
1593  case 5:
1594  return MISCREG_TLBI_VALE1IS_Xt;
1595  case 7:
1596  return MISCREG_TLBI_VAALE1IS_Xt;
1597  }
1598  break;
1599  case 7:
1600  switch (op2) {
1601  case 0:
1602  return MISCREG_TLBI_VMALLE1;
1603  case 1:
1604  return MISCREG_TLBI_VAE1_Xt;
1605  case 2:
1606  return MISCREG_TLBI_ASIDE1_Xt;
1607  case 3:
1608  return MISCREG_TLBI_VAAE1_Xt;
1609  case 5:
1610  return MISCREG_TLBI_VALE1_Xt;
1611  case 7:
1612  return MISCREG_TLBI_VAALE1_Xt;
1613  }
1614  break;
1615  }
1616  break;
1617  case 4:
1618  switch (crm) {
1619  case 0:
1620  switch (op2) {
1621  case 1:
1622  return MISCREG_TLBI_IPAS2E1IS_Xt;
1623  case 5:
1624  return MISCREG_TLBI_IPAS2LE1IS_Xt;
1625  }
1626  break;
1627  case 3:
1628  switch (op2) {
1629  case 0:
1630  return MISCREG_TLBI_ALLE2IS;
1631  case 1:
1632  return MISCREG_TLBI_VAE2IS_Xt;
1633  case 4:
1634  return MISCREG_TLBI_ALLE1IS;
1635  case 5:
1636  return MISCREG_TLBI_VALE2IS_Xt;
1637  case 6:
1638  return MISCREG_TLBI_VMALLS12E1IS;
1639  }
1640  break;
1641  case 4:
1642  switch (op2) {
1643  case 1:
1644  return MISCREG_TLBI_IPAS2E1_Xt;
1645  case 5:
1646  return MISCREG_TLBI_IPAS2LE1_Xt;
1647  }
1648  break;
1649  case 7:
1650  switch (op2) {
1651  case 0:
1652  return MISCREG_TLBI_ALLE2;
1653  case 1:
1654  return MISCREG_TLBI_VAE2_Xt;
1655  case 4:
1656  return MISCREG_TLBI_ALLE1;
1657  case 5:
1658  return MISCREG_TLBI_VALE2_Xt;
1659  case 6:
1660  return MISCREG_TLBI_VMALLS12E1;
1661  }
1662  break;
1663  }
1664  break;
1665  case 6:
1666  switch (crm) {
1667  case 3:
1668  switch (op2) {
1669  case 0:
1670  return MISCREG_TLBI_ALLE3IS;
1671  case 1:
1672  return MISCREG_TLBI_VAE3IS_Xt;
1673  case 5:
1674  return MISCREG_TLBI_VALE3IS_Xt;
1675  }
1676  break;
1677  case 7:
1678  switch (op2) {
1679  case 0:
1680  return MISCREG_TLBI_ALLE3;
1681  case 1:
1682  return MISCREG_TLBI_VAE3_Xt;
1683  case 5:
1684  return MISCREG_TLBI_VALE3_Xt;
1685  }
1686  break;
1687  }
1688  break;
1689  }
1690  break;
1691  case 11:
1692  case 15:
1693  // SYS Instruction with CRn = { 11, 15 }
1694  // (Trappable by HCR_EL2.TIDCP)
1695  return MISCREG_IMPDEF_UNIMPL;
1696  }
1697  break;
1698  case 2:
1699  switch (crn) {
1700  case 0:
1701  switch (op1) {
1702  case 0:
1703  switch (crm) {
1704  case 0:
1705  switch (op2) {
1706  case 2:
1707  return MISCREG_OSDTRRX_EL1;
1708  case 4:
1709  return MISCREG_DBGBVR0_EL1;
1710  case 5:
1711  return MISCREG_DBGBCR0_EL1;
1712  case 6:
1713  return MISCREG_DBGWVR0_EL1;
1714  case 7:
1715  return MISCREG_DBGWCR0_EL1;
1716  }
1717  break;
1718  case 1:
1719  switch (op2) {
1720  case 4:
1721  return MISCREG_DBGBVR1_EL1;
1722  case 5:
1723  return MISCREG_DBGBCR1_EL1;
1724  case 6:
1725  return MISCREG_DBGWVR1_EL1;
1726  case 7:
1727  return MISCREG_DBGWCR1_EL1;
1728  }
1729  break;
1730  case 2:
1731  switch (op2) {
1732  case 0:
1733  return MISCREG_MDCCINT_EL1;
1734  case 2:
1735  return MISCREG_MDSCR_EL1;
1736  case 4:
1737  return MISCREG_DBGBVR2_EL1;
1738  case 5:
1739  return MISCREG_DBGBCR2_EL1;
1740  case 6:
1741  return MISCREG_DBGWVR2_EL1;
1742  case 7:
1743  return MISCREG_DBGWCR2_EL1;
1744  }
1745  break;
1746  case 3:
1747  switch (op2) {
1748  case 2:
1749  return MISCREG_OSDTRTX_EL1;
1750  case 4:
1751  return MISCREG_DBGBVR3_EL1;
1752  case 5:
1753  return MISCREG_DBGBCR3_EL1;
1754  case 6:
1755  return MISCREG_DBGWVR3_EL1;
1756  case 7:
1757  return MISCREG_DBGWCR3_EL1;
1758  }
1759  break;
1760  case 4:
1761  switch (op2) {
1762  case 4:
1763  return MISCREG_DBGBVR4_EL1;
1764  case 5:
1765  return MISCREG_DBGBCR4_EL1;
1766  case 6:
1767  return MISCREG_DBGWVR4_EL1;
1768  case 7:
1769  return MISCREG_DBGWCR4_EL1;
1770  }
1771  break;
1772  case 5:
1773  switch (op2) {
1774  case 4:
1775  return MISCREG_DBGBVR5_EL1;
1776  case 5:
1777  return MISCREG_DBGBCR5_EL1;
1778  case 6:
1779  return MISCREG_DBGWVR5_EL1;
1780  case 7:
1781  return MISCREG_DBGWCR5_EL1;
1782  }
1783  break;
1784  case 6:
1785  switch (op2) {
1786  case 2:
1787  return MISCREG_OSECCR_EL1;
1788  case 4:
1789  return MISCREG_DBGBVR6_EL1;
1790  case 5:
1791  return MISCREG_DBGBCR6_EL1;
1792  case 6:
1793  return MISCREG_DBGWVR6_EL1;
1794  case 7:
1795  return MISCREG_DBGWCR6_EL1;
1796  }
1797  break;
1798  case 7:
1799  switch (op2) {
1800  case 4:
1801  return MISCREG_DBGBVR7_EL1;
1802  case 5:
1803  return MISCREG_DBGBCR7_EL1;
1804  case 6:
1805  return MISCREG_DBGWVR7_EL1;
1806  case 7:
1807  return MISCREG_DBGWCR7_EL1;
1808  }
1809  break;
1810  case 8:
1811  switch (op2) {
1812  case 4:
1813  return MISCREG_DBGBVR8_EL1;
1814  case 5:
1815  return MISCREG_DBGBCR8_EL1;
1816  case 6:
1817  return MISCREG_DBGWVR8_EL1;
1818  case 7:
1819  return MISCREG_DBGWCR8_EL1;
1820  }
1821  break;
1822  case 9:
1823  switch (op2) {
1824  case 4:
1825  return MISCREG_DBGBVR9_EL1;
1826  case 5:
1827  return MISCREG_DBGBCR9_EL1;
1828  case 6:
1829  return MISCREG_DBGWVR9_EL1;
1830  case 7:
1831  return MISCREG_DBGWCR9_EL1;
1832  }
1833  break;
1834  case 10:
1835  switch (op2) {
1836  case 4:
1837  return MISCREG_DBGBVR10_EL1;
1838  case 5:
1839  return MISCREG_DBGBCR10_EL1;
1840  case 6:
1841  return MISCREG_DBGWVR10_EL1;
1842  case 7:
1843  return MISCREG_DBGWCR10_EL1;
1844  }
1845  break;
1846  case 11:
1847  switch (op2) {
1848  case 4:
1849  return MISCREG_DBGBVR11_EL1;
1850  case 5:
1851  return MISCREG_DBGBCR11_EL1;
1852  case 6:
1853  return MISCREG_DBGWVR11_EL1;
1854  case 7:
1855  return MISCREG_DBGWCR11_EL1;
1856  }
1857  break;
1858  case 12:
1859  switch (op2) {
1860  case 4:
1861  return MISCREG_DBGBVR12_EL1;
1862  case 5:
1863  return MISCREG_DBGBCR12_EL1;
1864  case 6:
1865  return MISCREG_DBGWVR12_EL1;
1866  case 7:
1867  return MISCREG_DBGWCR12_EL1;
1868  }
1869  break;
1870  case 13:
1871  switch (op2) {
1872  case 4:
1873  return MISCREG_DBGBVR13_EL1;
1874  case 5:
1875  return MISCREG_DBGBCR13_EL1;
1876  case 6:
1877  return MISCREG_DBGWVR13_EL1;
1878  case 7:
1879  return MISCREG_DBGWCR13_EL1;
1880  }
1881  break;
1882  case 14:
1883  switch (op2) {
1884  case 4:
1885  return MISCREG_DBGBVR14_EL1;
1886  case 5:
1887  return MISCREG_DBGBCR14_EL1;
1888  case 6:
1889  return MISCREG_DBGWVR14_EL1;
1890  case 7:
1891  return MISCREG_DBGWCR14_EL1;
1892  }
1893  break;
1894  case 15:
1895  switch (op2) {
1896  case 4:
1897  return MISCREG_DBGBVR15_EL1;
1898  case 5:
1899  return MISCREG_DBGBCR15_EL1;
1900  case 6:
1901  return MISCREG_DBGWVR15_EL1;
1902  case 7:
1903  return MISCREG_DBGWCR15_EL1;
1904  }
1905  break;
1906  }
1907  break;
1908  case 2:
1909  switch (crm) {
1910  case 0:
1911  switch (op2) {
1912  case 0:
1913  return MISCREG_TEECR32_EL1;
1914  }
1915  break;
1916  }
1917  break;
1918  case 3:
1919  switch (crm) {
1920  case 1:
1921  switch (op2) {
1922  case 0:
1923  return MISCREG_MDCCSR_EL0;
1924  }
1925  break;
1926  case 4:
1927  switch (op2) {
1928  case 0:
1929  return MISCREG_MDDTR_EL0;
1930  }
1931  break;
1932  case 5:
1933  switch (op2) {
1934  case 0:
1935  return MISCREG_MDDTRRX_EL0;
1936  }
1937  break;
1938  }
1939  break;
1940  case 4:
1941  switch (crm) {
1942  case 7:
1943  switch (op2) {
1944  case 0:
1945  return MISCREG_DBGVCR32_EL2;
1946  }
1947  break;
1948  }
1949  break;
1950  }
1951  break;
1952  case 1:
1953  switch (op1) {
1954  case 0:
1955  switch (crm) {
1956  case 0:
1957  switch (op2) {
1958  case 0:
1959  return MISCREG_MDRAR_EL1;
1960  case 4:
1961  return MISCREG_OSLAR_EL1;
1962  }
1963  break;
1964  case 1:
1965  switch (op2) {
1966  case 4:
1967  return MISCREG_OSLSR_EL1;
1968  }
1969  break;
1970  case 3:
1971  switch (op2) {
1972  case 4:
1973  return MISCREG_OSDLR_EL1;
1974  }
1975  break;
1976  case 4:
1977  switch (op2) {
1978  case 4:
1979  return MISCREG_DBGPRCR_EL1;
1980  }
1981  break;
1982  }
1983  break;
1984  case 2:
1985  switch (crm) {
1986  case 0:
1987  switch (op2) {
1988  case 0:
1989  return MISCREG_TEEHBR32_EL1;
1990  }
1991  break;
1992  }
1993  break;
1994  }
1995  break;
1996  case 7:
1997  switch (op1) {
1998  case 0:
1999  switch (crm) {
2000  case 8:
2001  switch (op2) {
2002  case 6:
2003  return MISCREG_DBGCLAIMSET_EL1;
2004  }
2005  break;
2006  case 9:
2007  switch (op2) {
2008  case 6:
2009  return MISCREG_DBGCLAIMCLR_EL1;
2010  }
2011  break;
2012  case 14:
2013  switch (op2) {
2014  case 6:
2015  return MISCREG_DBGAUTHSTATUS_EL1;
2016  }
2017  break;
2018  }
2019  break;
2020  }
2021  break;
2022  }
2023  break;
2024  case 3:
2025  switch (crn) {
2026  case 0:
2027  switch (op1) {
2028  case 0:
2029  switch (crm) {
2030  case 0:
2031  switch (op2) {
2032  case 0:
2033  return MISCREG_MIDR_EL1;
2034  case 5:
2035  return MISCREG_MPIDR_EL1;
2036  case 6:
2037  return MISCREG_REVIDR_EL1;
2038  }
2039  break;
2040  case 1:
2041  switch (op2) {
2042  case 0:
2043  return MISCREG_ID_PFR0_EL1;
2044  case 1:
2045  return MISCREG_ID_PFR1_EL1;
2046  case 2:
2047  return MISCREG_ID_DFR0_EL1;
2048  case 3:
2049  return MISCREG_ID_AFR0_EL1;
2050  case 4:
2051  return MISCREG_ID_MMFR0_EL1;
2052  case 5:
2053  return MISCREG_ID_MMFR1_EL1;
2054  case 6:
2055  return MISCREG_ID_MMFR2_EL1;
2056  case 7:
2057  return MISCREG_ID_MMFR3_EL1;
2058  }
2059  break;
2060  case 2:
2061  switch (op2) {
2062  case 0:
2063  return MISCREG_ID_ISAR0_EL1;
2064  case 1:
2065  return MISCREG_ID_ISAR1_EL1;
2066  case 2:
2067  return MISCREG_ID_ISAR2_EL1;
2068  case 3:
2069  return MISCREG_ID_ISAR3_EL1;
2070  case 4:
2071  return MISCREG_ID_ISAR4_EL1;
2072  case 5:
2073  return MISCREG_ID_ISAR5_EL1;
2074  case 6:
2075  return MISCREG_ID_MMFR4_EL1;
2076  case 7:
2077  return MISCREG_ID_ISAR6_EL1;
2078  }
2079  break;
2080  case 3:
2081  switch (op2) {
2082  case 0:
2083  return MISCREG_MVFR0_EL1;
2084  case 1:
2085  return MISCREG_MVFR1_EL1;
2086  case 2:
2087  return MISCREG_MVFR2_EL1;
2088  case 3 ... 7:
2089  return MISCREG_RAZ;
2090  }
2091  break;
2092  case 4:
2093  switch (op2) {
2094  case 0:
2095  return MISCREG_ID_AA64PFR0_EL1;
2096  case 1:
2097  return MISCREG_ID_AA64PFR1_EL1;
2098  case 2 ... 3:
2099  return MISCREG_RAZ;
2100  case 4:
2101  return MISCREG_ID_AA64ZFR0_EL1;
2102  case 5 ... 7:
2103  return MISCREG_RAZ;
2104  }
2105  break;
2106  case 5:
2107  switch (op2) {
2108  case 0:
2109  return MISCREG_ID_AA64DFR0_EL1;
2110  case 1:
2111  return MISCREG_ID_AA64DFR1_EL1;
2112  case 4:
2113  return MISCREG_ID_AA64AFR0_EL1;
2114  case 5:
2115  return MISCREG_ID_AA64AFR1_EL1;
2116  case 2:
2117  case 3:
2118  case 6:
2119  case 7:
2120  return MISCREG_RAZ;
2121  }
2122  break;
2123  case 6:
2124  switch (op2) {
2125  case 0:
2126  return MISCREG_ID_AA64ISAR0_EL1;
2127  case 1:
2128  return MISCREG_ID_AA64ISAR1_EL1;
2129  case 2 ... 7:
2130  return MISCREG_RAZ;
2131  }
2132  break;
2133  case 7:
2134  switch (op2) {
2135  case 0:
2136  return MISCREG_ID_AA64MMFR0_EL1;
2137  case 1:
2138  return MISCREG_ID_AA64MMFR1_EL1;
2139  case 2:
2140  return MISCREG_ID_AA64MMFR2_EL1;
2141  case 3 ... 7:
2142  return MISCREG_RAZ;
2143  }
2144  break;
2145  }
2146  break;
2147  case 1:
2148  switch (crm) {
2149  case 0:
2150  switch (op2) {
2151  case 0:
2152  return MISCREG_CCSIDR_EL1;
2153  case 1:
2154  return MISCREG_CLIDR_EL1;
2155  case 7:
2156  return MISCREG_AIDR_EL1;
2157  }
2158  break;
2159  }
2160  break;
2161  case 2:
2162  switch (crm) {
2163  case 0:
2164  switch (op2) {
2165  case 0:
2166  return MISCREG_CSSELR_EL1;
2167  }
2168  break;
2169  }
2170  break;
2171  case 3:
2172  switch (crm) {
2173  case 0:
2174  switch (op2) {
2175  case 1:
2176  return MISCREG_CTR_EL0;
2177  case 7:
2178  return MISCREG_DCZID_EL0;
2179  }
2180  break;
2181  }
2182  break;
2183  case 4:
2184  switch (crm) {
2185  case 0:
2186  switch (op2) {
2187  case 0:
2188  return MISCREG_VPIDR_EL2;
2189  case 5:
2190  return MISCREG_VMPIDR_EL2;
2191  }
2192  break;
2193  }
2194  break;
2195  }
2196  break;
2197  case 1:
2198  switch (op1) {
2199  case 0:
2200  switch (crm) {
2201  case 0:
2202  switch (op2) {
2203  case 0:
2204  return MISCREG_SCTLR_EL1;
2205  case 1:
2206  return MISCREG_ACTLR_EL1;
2207  case 2:
2208  return MISCREG_CPACR_EL1;
2209  }
2210  break;
2211  case 2:
2212  switch (op2) {
2213  case 0:
2214  return MISCREG_ZCR_EL1;
2215  }
2216  break;
2217  }
2218  break;
2219  case 4:
2220  switch (crm) {
2221  case 0:
2222  switch (op2) {
2223  case 0:
2224  return MISCREG_SCTLR_EL2;
2225  case 1:
2226  return MISCREG_ACTLR_EL2;
2227  }
2228  break;
2229  case 1:
2230  switch (op2) {
2231  case 0:
2232  return MISCREG_HCR_EL2;
2233  case 1:
2234  return MISCREG_MDCR_EL2;
2235  case 2:
2236  return MISCREG_CPTR_EL2;
2237  case 3:
2238  return MISCREG_HSTR_EL2;
2239  case 7:
2240  return MISCREG_HACR_EL2;
2241  }
2242  break;
2243  case 2:
2244  switch (op2) {
2245  case 0:
2246  return MISCREG_ZCR_EL2;
2247  }
2248  break;
2249  }
2250  break;
2251  case 5:
2252  /* op0: 3 Crn:1 op1:5 */
2253  switch (crm) {
2254  case 0:
2255  switch (op2) {
2256  case 0:
2257  return MISCREG_SCTLR_EL12;
2258  case 2:
2259  return MISCREG_CPACR_EL12;
2260  }
2261  break;
2262  case 2:
2263  switch (op2) {
2264  case 0:
2265  return MISCREG_ZCR_EL12;
2266  }
2267  break;
2268  }
2269  break;
2270  case 6:
2271  switch (crm) {
2272  case 0:
2273  switch (op2) {
2274  case 0:
2275  return MISCREG_SCTLR_EL3;
2276  case 1:
2277  return MISCREG_ACTLR_EL3;
2278  }
2279  break;
2280  case 1:
2281  switch (op2) {
2282  case 0:
2283  return MISCREG_SCR_EL3;
2284  case 1:
2285  return MISCREG_SDER32_EL3;
2286  case 2:
2287  return MISCREG_CPTR_EL3;
2288  }
2289  break;
2290  case 2:
2291  switch (op2) {
2292  case 0:
2293  return MISCREG_ZCR_EL3;
2294  }
2295  break;
2296  case 3:
2297  switch (op2) {
2298  case 1:
2299  return MISCREG_MDCR_EL3;
2300  }
2301  break;
2302  }
2303  break;
2304  }
2305  break;
2306  case 2:
2307  switch (op1) {
2308  case 0:
2309  switch (crm) {
2310  case 0:
2311  switch (op2) {
2312  case 0:
2313  return MISCREG_TTBR0_EL1;
2314  case 1:
2315  return MISCREG_TTBR1_EL1;
2316  case 2:
2317  return MISCREG_TCR_EL1;
2318  }
2319  break;
2320  case 0x1:
2321  switch (op2) {
2322  case 0x0:
2323  return MISCREG_APIAKeyLo_EL1;
2324  case 0x1:
2325  return MISCREG_APIAKeyHi_EL1;
2326  case 0x2:
2327  return MISCREG_APIBKeyLo_EL1;
2328  case 0x3:
2329  return MISCREG_APIBKeyHi_EL1;
2330  }
2331  break;
2332  case 0x2:
2333  switch (op2) {
2334  case 0x0:
2335  return MISCREG_APDAKeyLo_EL1;
2336  case 0x1:
2337  return MISCREG_APDAKeyHi_EL1;
2338  case 0x2:
2339  return MISCREG_APDBKeyLo_EL1;
2340  case 0x3:
2341  return MISCREG_APDBKeyHi_EL1;
2342  }
2343  break;
2344 
2345  case 0x3:
2346  switch (op2) {
2347  case 0x0:
2348  return MISCREG_APGAKeyLo_EL1;
2349  case 0x1:
2350  return MISCREG_APGAKeyHi_EL1;
2351  }
2352  break;
2353  }
2354  break;
2355  case 4:
2356  switch (crm) {
2357  case 0:
2358  switch (op2) {
2359  case 0:
2360  return MISCREG_TTBR0_EL2;
2361  case 1:
2362  return MISCREG_TTBR1_EL2;
2363  case 2:
2364  return MISCREG_TCR_EL2;
2365  }
2366  break;
2367  case 1:
2368  switch (op2) {
2369  case 0:
2370  return MISCREG_VTTBR_EL2;
2371  case 2:
2372  return MISCREG_VTCR_EL2;
2373  }
2374  break;
2375  case 6:
2376  switch (op2) {
2377  case 0:
2378  return MISCREG_VSTTBR_EL2;
2379  case 2:
2380  return MISCREG_VSTCR_EL2;
2381  }
2382  break;
2383  }
2384  break;
2385  case 5:
2386  /* op0: 3 Crn:2 op1:5 */
2387  switch (crm) {
2388  case 0:
2389  switch (op2) {
2390  case 0:
2391  return MISCREG_TTBR0_EL12;
2392  case 1:
2393  return MISCREG_TTBR1_EL12;
2394  case 2:
2395  return MISCREG_TCR_EL12;
2396  }
2397  break;
2398  }
2399  break;
2400  case 6:
2401  switch (crm) {
2402  case 0:
2403  switch (op2) {
2404  case 0:
2405  return MISCREG_TTBR0_EL3;
2406  case 2:
2407  return MISCREG_TCR_EL3;
2408  }
2409  break;
2410  }
2411  break;
2412  }
2413  break;
2414  case 3:
2415  switch (op1) {
2416  case 4:
2417  switch (crm) {
2418  case 0:
2419  switch (op2) {
2420  case 0:
2421  return MISCREG_DACR32_EL2;
2422  }
2423  break;
2424  }
2425  break;
2426  }
2427  break;
2428  case 4:
2429  switch (op1) {
2430  case 0:
2431  switch (crm) {
2432  case 0:
2433  switch (op2) {
2434  case 0:
2435  return MISCREG_SPSR_EL1;
2436  case 1:
2437  return MISCREG_ELR_EL1;
2438  }
2439  break;
2440  case 1:
2441  switch (op2) {
2442  case 0:
2443  return MISCREG_SP_EL0;
2444  }
2445  break;
2446  case 2:
2447  switch (op2) {
2448  case 0:
2449  return MISCREG_SPSEL;
2450  case 2:
2451  return MISCREG_CURRENTEL;
2452  case 3:
2453  return MISCREG_PAN;
2454  }
2455  break;
2456  case 6:
2457  switch (op2) {
2458  case 0:
2459  return MISCREG_ICC_PMR_EL1;
2460  }
2461  break;
2462  }
2463  break;
2464  case 3:
2465  switch (crm) {
2466  case 2:
2467  switch (op2) {
2468  case 0:
2469  return MISCREG_NZCV;
2470  case 1:
2471  return MISCREG_DAIF;
2472  }
2473  break;
2474  case 4:
2475  switch (op2) {
2476  case 0:
2477  return MISCREG_FPCR;
2478  case 1:
2479  return MISCREG_FPSR;
2480  }
2481  break;
2482  case 5:
2483  switch (op2) {
2484  case 0:
2485  return MISCREG_DSPSR_EL0;
2486  case 1:
2487  return MISCREG_DLR_EL0;
2488  }
2489  break;
2490  }
2491  break;
2492  case 4:
2493  switch (crm) {
2494  case 0:
2495  switch (op2) {
2496  case 0:
2497  return MISCREG_SPSR_EL2;
2498  case 1:
2499  return MISCREG_ELR_EL2;
2500  }
2501  break;
2502  case 1:
2503  switch (op2) {
2504  case 0:
2505  return MISCREG_SP_EL1;
2506  }
2507  break;
2508  case 3:
2509  switch (op2) {
2510  case 0:
2511  return MISCREG_SPSR_IRQ_AA64;
2512  case 1:
2513  return MISCREG_SPSR_ABT_AA64;
2514  case 2:
2515  return MISCREG_SPSR_UND_AA64;
2516  case 3:
2517  return MISCREG_SPSR_FIQ_AA64;
2518  }
2519  break;
2520  }
2521  break;
2522  case 5:
2523  switch (crm) {
2524  case 0:
2525  switch (op2) {
2526  case 0:
2527  return MISCREG_SPSR_EL12;
2528  case 1:
2529  return MISCREG_ELR_EL12;
2530  }
2531  break;
2532  }
2533  break;
2534  case 6:
2535  switch (crm) {
2536  case 0:
2537  switch (op2) {
2538  case 0:
2539  return MISCREG_SPSR_EL3;
2540  case 1:
2541  return MISCREG_ELR_EL3;
2542  }
2543  break;
2544  case 1:
2545  switch (op2) {
2546  case 0:
2547  return MISCREG_SP_EL2;
2548  }
2549  break;
2550  }
2551  break;
2552  }
2553  break;
2554  case 5:
2555  switch (op1) {
2556  case 0:
2557  switch (crm) {
2558  case 1:
2559  switch (op2) {
2560  case 0:
2561  return MISCREG_AFSR0_EL1;
2562  case 1:
2563  return MISCREG_AFSR1_EL1;
2564  }
2565  break;
2566  case 2:
2567  switch (op2) {
2568  case 0:
2569  return MISCREG_ESR_EL1;
2570  }
2571  break;
2572  case 3:
2573  switch (op2) {
2574  case 0:
2575  return MISCREG_ERRIDR_EL1;
2576  case 1:
2577  return MISCREG_ERRSELR_EL1;
2578  }
2579  break;
2580  case 4:
2581  switch (op2) {
2582  case 0:
2583  return MISCREG_ERXFR_EL1;
2584  case 1:
2585  return MISCREG_ERXCTLR_EL1;
2586  case 2:
2587  return MISCREG_ERXSTATUS_EL1;
2588  case 3:
2589  return MISCREG_ERXADDR_EL1;
2590  }
2591  break;
2592  case 5:
2593  switch (op2) {
2594  case 0:
2595  return MISCREG_ERXMISC0_EL1;
2596  case 1:
2597  return MISCREG_ERXMISC1_EL1;
2598  }
2599  break;
2600  }
2601  break;
2602  case 4:
2603  switch (crm) {
2604  case 0:
2605  switch (op2) {
2606  case 1:
2607  return MISCREG_IFSR32_EL2;
2608  }
2609  break;
2610  case 1:
2611  switch (op2) {
2612  case 0:
2613  return MISCREG_AFSR0_EL2;
2614  case 1:
2615  return MISCREG_AFSR1_EL2;
2616  }
2617  break;
2618  case 2:
2619  switch (op2) {
2620  case 0:
2621  return MISCREG_ESR_EL2;
2622  case 3:
2623  return MISCREG_VSESR_EL2;
2624  }
2625  break;
2626  case 3:
2627  switch (op2) {
2628  case 0:
2629  return MISCREG_FPEXC32_EL2;
2630  }
2631  break;
2632  }
2633  break;
2634  case 5:
2635  switch (crm) {
2636  case 1:
2637  switch (op2) {
2638  case 0:
2639  return MISCREG_AFSR0_EL12;
2640  case 1:
2641  return MISCREG_AFSR1_EL12;
2642  }
2643  break;
2644  case 2:
2645  switch (op2) {
2646  case 0:
2647  return MISCREG_ESR_EL12;
2648  }
2649  break;
2650  }
2651  break;
2652  case 6:
2653  switch (crm) {
2654  case 1:
2655  switch (op2) {
2656  case 0:
2657  return MISCREG_AFSR0_EL3;
2658  case 1:
2659  return MISCREG_AFSR1_EL3;
2660  }
2661  break;
2662  case 2:
2663  switch (op2) {
2664  case 0:
2665  return MISCREG_ESR_EL3;
2666  }
2667  break;
2668  }
2669  break;
2670  }
2671  break;
2672  case 6:
2673  switch (op1) {
2674  case 0:
2675  switch (crm) {
2676  case 0:
2677  switch (op2) {
2678  case 0:
2679  return MISCREG_FAR_EL1;
2680  }
2681  break;
2682  }
2683  break;
2684  case 4:
2685  switch (crm) {
2686  case 0:
2687  switch (op2) {
2688  case 0:
2689  return MISCREG_FAR_EL2;
2690  case 4:
2691  return MISCREG_HPFAR_EL2;
2692  }
2693  break;
2694  }
2695  break;
2696  case 5:
2697  switch (crm) {
2698  case 0:
2699  switch (op2) {
2700  case 0:
2701  return MISCREG_FAR_EL12;
2702  }
2703  break;
2704  }
2705  break;
2706  case 6:
2707  switch (crm) {
2708  case 0:
2709  switch (op2) {
2710  case 0:
2711  return MISCREG_FAR_EL3;
2712  }
2713  break;
2714  }
2715  break;
2716  }
2717  break;
2718  case 7:
2719  switch (op1) {
2720  case 0:
2721  switch (crm) {
2722  case 4:
2723  switch (op2) {
2724  case 0:
2725  return MISCREG_PAR_EL1;
2726  }
2727  break;
2728  }
2729  break;
2730  }
2731  break;
2732  case 9:
2733  switch (op1) {
2734  case 0:
2735  switch (crm) {
2736  case 14:
2737  switch (op2) {
2738  case 1:
2739  return MISCREG_PMINTENSET_EL1;
2740  case 2:
2741  return MISCREG_PMINTENCLR_EL1;
2742  }
2743  break;
2744  }
2745  break;
2746  case 3:
2747  switch (crm) {
2748  case 12:
2749  switch (op2) {
2750  case 0:
2751  return MISCREG_PMCR_EL0;
2752  case 1:
2753  return MISCREG_PMCNTENSET_EL0;
2754  case 2:
2755  return MISCREG_PMCNTENCLR_EL0;
2756  case 3:
2757  return MISCREG_PMOVSCLR_EL0;
2758  case 4:
2759  return MISCREG_PMSWINC_EL0;
2760  case 5:
2761  return MISCREG_PMSELR_EL0;
2762  case 6:
2763  return MISCREG_PMCEID0_EL0;
2764  case 7:
2765  return MISCREG_PMCEID1_EL0;
2766  }
2767  break;
2768  case 13:
2769  switch (op2) {
2770  case 0:
2771  return MISCREG_PMCCNTR_EL0;
2772  case 1:
2773  return MISCREG_PMXEVTYPER_EL0;
2774  case 2:
2775  return MISCREG_PMXEVCNTR_EL0;
2776  }
2777  break;
2778  case 14:
2779  switch (op2) {
2780  case 0:
2781  return MISCREG_PMUSERENR_EL0;
2782  case 3:
2783  return MISCREG_PMOVSSET_EL0;
2784  }
2785  break;
2786  }
2787  break;
2788  }
2789  break;
2790  case 10:
2791  switch (op1) {
2792  case 0:
2793  switch (crm) {
2794  case 2:
2795  switch (op2) {
2796  case 0:
2797  return MISCREG_MAIR_EL1;
2798  }
2799  break;
2800  case 3:
2801  switch (op2) {
2802  case 0:
2803  return MISCREG_AMAIR_EL1;
2804  }
2805  break;
2806  }
2807  break;
2808  case 4:
2809  switch (crm) {
2810  case 2:
2811  switch (op2) {
2812  case 0:
2813  return MISCREG_MAIR_EL2;
2814  }
2815  break;
2816  case 3:
2817  switch (op2) {
2818  case 0:
2819  return MISCREG_AMAIR_EL2;
2820  }
2821  break;
2822  }
2823  break;
2824  case 5:
2825  switch (crm) {
2826  case 2:
2827  switch (op2) {
2828  case 0:
2829  return MISCREG_MAIR_EL12;
2830  }
2831  break;
2832  case 3:
2833  switch (op2) {
2834  case 0:
2835  return MISCREG_AMAIR_EL12;
2836  }
2837  break;
2838  }
2839  break;
2840  case 6:
2841  switch (crm) {
2842  case 2:
2843  switch (op2) {
2844  case 0:
2845  return MISCREG_MAIR_EL3;
2846  }
2847  break;
2848  case 3:
2849  switch (op2) {
2850  case 0:
2851  return MISCREG_AMAIR_EL3;
2852  }
2853  break;
2854  }
2855  break;
2856  }
2857  break;
2858  case 11:
2859  switch (op1) {
2860  case 1:
2861  switch (crm) {
2862  case 0:
2863  switch (op2) {
2864  case 2:
2865  return MISCREG_L2CTLR_EL1;
2866  case 3:
2867  return MISCREG_L2ECTLR_EL1;
2868  }
2869  break;
2870  }
2871  GEM5_FALLTHROUGH;
2872  default:
2873  // S3_<op1>_11_<Cm>_<op2>
2874  return MISCREG_IMPDEF_UNIMPL;
2875  }
2876  GEM5_UNREACHABLE;
2877  case 12:
2878  switch (op1) {
2879  case 0:
2880  switch (crm) {
2881  case 0:
2882  switch (op2) {
2883  case 0:
2884  return MISCREG_VBAR_EL1;
2885  case 1:
2886  return MISCREG_RVBAR_EL1;
2887  }
2888  break;
2889  case 1:
2890  switch (op2) {
2891  case 0:
2892  return MISCREG_ISR_EL1;
2893  case 1:
2894  return MISCREG_DISR_EL1;
2895  }
2896  break;
2897  case 8:
2898  switch (op2) {
2899  case 0:
2900  return MISCREG_ICC_IAR0_EL1;
2901  case 1:
2902  return MISCREG_ICC_EOIR0_EL1;
2903  case 2:
2904  return MISCREG_ICC_HPPIR0_EL1;
2905  case 3:
2906  return MISCREG_ICC_BPR0_EL1;
2907  case 4:
2908  return MISCREG_ICC_AP0R0_EL1;
2909  case 5:
2910  return MISCREG_ICC_AP0R1_EL1;
2911  case 6:
2912  return MISCREG_ICC_AP0R2_EL1;
2913  case 7:
2914  return MISCREG_ICC_AP0R3_EL1;
2915  }
2916  break;
2917  case 9:
2918  switch (op2) {
2919  case 0:
2920  return MISCREG_ICC_AP1R0_EL1;
2921  case 1:
2922  return MISCREG_ICC_AP1R1_EL1;
2923  case 2:
2924  return MISCREG_ICC_AP1R2_EL1;
2925  case 3:
2926  return MISCREG_ICC_AP1R3_EL1;
2927  }
2928  break;
2929  case 11:
2930  switch (op2) {
2931  case 1:
2932  return MISCREG_ICC_DIR_EL1;
2933  case 3:
2934  return MISCREG_ICC_RPR_EL1;
2935  case 5:
2936  return MISCREG_ICC_SGI1R_EL1;
2937  case 6:
2938  return MISCREG_ICC_ASGI1R_EL1;
2939  case 7:
2940  return MISCREG_ICC_SGI0R_EL1;
2941  }
2942  break;
2943  case 12:
2944  switch (op2) {
2945  case 0:
2946  return MISCREG_ICC_IAR1_EL1;
2947  case 1:
2948  return MISCREG_ICC_EOIR1_EL1;
2949  case 2:
2950  return MISCREG_ICC_HPPIR1_EL1;
2951  case 3:
2952  return MISCREG_ICC_BPR1_EL1;
2953  case 4:
2954  return MISCREG_ICC_CTLR_EL1;
2955  case 5:
2956  return MISCREG_ICC_SRE_EL1;
2957  case 6:
2958  return MISCREG_ICC_IGRPEN0_EL1;
2959  case 7:
2960  return MISCREG_ICC_IGRPEN1_EL1;
2961  }
2962  break;
2963  }
2964  break;
2965  case 4:
2966  switch (crm) {
2967  case 0:
2968  switch (op2) {
2969  case 0:
2970  return MISCREG_VBAR_EL2;
2971  case 1:
2972  return MISCREG_RVBAR_EL2;
2973  }
2974  break;
2975  case 1:
2976  switch (op2) {
2977  case 1:
2978  return MISCREG_VDISR_EL2;
2979  }
2980  break;
2981  case 8:
2982  switch (op2) {
2983  case 0:
2984  return MISCREG_ICH_AP0R0_EL2;
2985  case 1:
2986  return MISCREG_ICH_AP0R1_EL2;
2987  case 2:
2988  return MISCREG_ICH_AP0R2_EL2;
2989  case 3:
2990  return MISCREG_ICH_AP0R3_EL2;
2991  }
2992  break;
2993  case 9:
2994  switch (op2) {
2995  case 0:
2996  return MISCREG_ICH_AP1R0_EL2;
2997  case 1:
2998  return MISCREG_ICH_AP1R1_EL2;
2999  case 2:
3000  return MISCREG_ICH_AP1R2_EL2;
3001  case 3:
3002  return MISCREG_ICH_AP1R3_EL2;
3003  case 5:
3004  return MISCREG_ICC_SRE_EL2;
3005  }
3006  break;
3007  case 11:
3008  switch (op2) {
3009  case 0:
3010  return MISCREG_ICH_HCR_EL2;
3011  case 1:
3012  return MISCREG_ICH_VTR_EL2;
3013  case 2:
3014  return MISCREG_ICH_MISR_EL2;
3015  case 3:
3016  return MISCREG_ICH_EISR_EL2;
3017  case 5:
3018  return MISCREG_ICH_ELRSR_EL2;
3019  case 7:
3020  return MISCREG_ICH_VMCR_EL2;
3021  }
3022  break;
3023  case 12:
3024  switch (op2) {
3025  case 0:
3026  return MISCREG_ICH_LR0_EL2;
3027  case 1:
3028  return MISCREG_ICH_LR1_EL2;
3029  case 2:
3030  return MISCREG_ICH_LR2_EL2;
3031  case 3:
3032  return MISCREG_ICH_LR3_EL2;
3033  case 4:
3034  return MISCREG_ICH_LR4_EL2;
3035  case 5:
3036  return MISCREG_ICH_LR5_EL2;
3037  case 6:
3038  return MISCREG_ICH_LR6_EL2;
3039  case 7:
3040  return MISCREG_ICH_LR7_EL2;
3041  }
3042  break;
3043  case 13:
3044  switch (op2) {
3045  case 0:
3046  return MISCREG_ICH_LR8_EL2;
3047  case 1:
3048  return MISCREG_ICH_LR9_EL2;
3049  case 2:
3050  return MISCREG_ICH_LR10_EL2;
3051  case 3:
3052  return MISCREG_ICH_LR11_EL2;
3053  case 4:
3054  return MISCREG_ICH_LR12_EL2;
3055  case 5:
3056  return MISCREG_ICH_LR13_EL2;
3057  case 6:
3058  return MISCREG_ICH_LR14_EL2;
3059  case 7:
3060  return MISCREG_ICH_LR15_EL2;
3061  }
3062  break;
3063  }
3064  break;
3065  case 5:
3066  switch (crm) {
3067  case 0:
3068  switch (op2) {
3069  case 0:
3070  return MISCREG_VBAR_EL12;
3071  }
3072  break;
3073  }
3074  break;
3075  case 6:
3076  switch (crm) {
3077  case 0:
3078  switch (op2) {
3079  case 0:
3080  return MISCREG_VBAR_EL3;
3081  case 1:
3082  return MISCREG_RVBAR_EL3;
3083  case 2:
3084  return MISCREG_RMR_EL3;
3085  }
3086  break;
3087  case 12:
3088  switch (op2) {
3089  case 4:
3090  return MISCREG_ICC_CTLR_EL3;
3091  case 5:
3092  return MISCREG_ICC_SRE_EL3;
3093  case 7:
3094  return MISCREG_ICC_IGRPEN1_EL3;
3095  }
3096  break;
3097  }
3098  break;
3099  }
3100  break;
3101  case 13:
3102  switch (op1) {
3103  case 0:
3104  switch (crm) {
3105  case 0:
3106  switch (op2) {
3107  case 1:
3108  return MISCREG_CONTEXTIDR_EL1;
3109  case 4:
3110  return MISCREG_TPIDR_EL1;
3111  }
3112  break;
3113  }
3114  break;
3115  case 3:
3116  switch (crm) {
3117  case 0:
3118  switch (op2) {
3119  case 2:
3120  return MISCREG_TPIDR_EL0;
3121  case 3:
3122  return MISCREG_TPIDRRO_EL0;
3123  }
3124  break;
3125  }
3126  break;
3127  case 4:
3128  switch (crm) {
3129  case 0:
3130  switch (op2) {
3131  case 1:
3132  return MISCREG_CONTEXTIDR_EL2;
3133  case 2:
3134  return MISCREG_TPIDR_EL2;
3135  }
3136  break;
3137  }
3138  break;
3139  case 5:
3140  switch (crm) {
3141  case 0:
3142  switch (op2) {
3143  case 1:
3144  return MISCREG_CONTEXTIDR_EL12;
3145  }
3146  break;
3147  }
3148  break;
3149  case 6:
3150  switch (crm) {
3151  case 0:
3152  switch (op2) {
3153  case 2:
3154  return MISCREG_TPIDR_EL3;
3155  }
3156  break;
3157  }
3158  break;
3159  }
3160  break;
3161  case 14:
3162  switch (op1) {
3163  case 0:
3164  switch (crm) {
3165  case 1:
3166  switch (op2) {
3167  case 0:
3168  return MISCREG_CNTKCTL_EL1;
3169  }
3170  break;
3171  }
3172  break;
3173  case 3:
3174  switch (crm) {
3175  case 0:
3176  switch (op2) {
3177  case 0:
3178  return MISCREG_CNTFRQ_EL0;
3179  case 1:
3180  return MISCREG_CNTPCT_EL0;
3181  case 2:
3182  return MISCREG_CNTVCT_EL0;
3183  }
3184  break;
3185  case 2:
3186  switch (op2) {
3187  case 0:
3188  return MISCREG_CNTP_TVAL_EL0;
3189  case 1:
3190  return MISCREG_CNTP_CTL_EL0;
3191  case 2:
3192  return MISCREG_CNTP_CVAL_EL0;
3193  }
3194  break;
3195  case 3:
3196  switch (op2) {
3197  case 0:
3198  return MISCREG_CNTV_TVAL_EL0;
3199  case 1:
3200  return MISCREG_CNTV_CTL_EL0;
3201  case 2:
3202  return MISCREG_CNTV_CVAL_EL0;
3203  }
3204  break;
3205  case 8:
3206  switch (op2) {
3207  case 0:
3208  return MISCREG_PMEVCNTR0_EL0;
3209  case 1:
3210  return MISCREG_PMEVCNTR1_EL0;
3211  case 2:
3212  return MISCREG_PMEVCNTR2_EL0;
3213  case 3:
3214  return MISCREG_PMEVCNTR3_EL0;
3215  case 4:
3216  return MISCREG_PMEVCNTR4_EL0;
3217  case 5:
3218  return MISCREG_PMEVCNTR5_EL0;
3219  }
3220  break;
3221  case 12:
3222  switch (op2) {
3223  case 0:
3224  return MISCREG_PMEVTYPER0_EL0;
3225  case 1:
3226  return MISCREG_PMEVTYPER1_EL0;
3227  case 2:
3228  return MISCREG_PMEVTYPER2_EL0;
3229  case 3:
3230  return MISCREG_PMEVTYPER3_EL0;
3231  case 4:
3232  return MISCREG_PMEVTYPER4_EL0;
3233  case 5:
3234  return MISCREG_PMEVTYPER5_EL0;
3235  }
3236  break;
3237  case 15:
3238  switch (op2) {
3239  case 7:
3240  return MISCREG_PMCCFILTR_EL0;
3241  }
3242  }
3243  break;
3244  case 4:
3245  switch (crm) {
3246  case 0:
3247  switch (op2) {
3248  case 3:
3249  return MISCREG_CNTVOFF_EL2;
3250  }
3251  break;
3252  case 1:
3253  switch (op2) {
3254  case 0:
3255  return MISCREG_CNTHCTL_EL2;
3256  }
3257  break;
3258  case 2:
3259  switch (op2) {
3260  case 0:
3261  return MISCREG_CNTHP_TVAL_EL2;
3262  case 1:
3263  return MISCREG_CNTHP_CTL_EL2;
3264  case 2:
3265  return MISCREG_CNTHP_CVAL_EL2;
3266  }
3267  break;
3268  case 3:
3269  switch (op2) {
3270  case 0:
3271  return MISCREG_CNTHV_TVAL_EL2;
3272  case 1:
3273  return MISCREG_CNTHV_CTL_EL2;
3274  case 2:
3275  return MISCREG_CNTHV_CVAL_EL2;
3276  }
3277  break;
3278  }
3279  break;
3280  case 5:
3281  switch (crm) {
3282  case 1:
3283  switch (op2) {
3284  case 0:
3285  return MISCREG_CNTKCTL_EL12;
3286  }
3287  break;
3288  case 2:
3289  switch (op2) {
3290  case 0:
3291  return MISCREG_CNTP_TVAL_EL02;
3292  case 1:
3293  return MISCREG_CNTP_CTL_EL02;
3294  case 2:
3295  return MISCREG_CNTP_CVAL_EL02;
3296  }
3297  break;
3298  case 3:
3299  switch (op2) {
3300  case 0:
3301  return MISCREG_CNTV_TVAL_EL02;
3302  case 1:
3303  return MISCREG_CNTV_CTL_EL02;
3304  case 2:
3305  return MISCREG_CNTV_CVAL_EL02;
3306  }
3307  break;
3308  }
3309  break;
3310  case 7:
3311  switch (crm) {
3312  case 2:
3313  switch (op2) {
3314  case 0:
3315  return MISCREG_CNTPS_TVAL_EL1;
3316  case 1:
3317  return MISCREG_CNTPS_CTL_EL1;
3318  case 2:
3319  return MISCREG_CNTPS_CVAL_EL1;
3320  }
3321  break;
3322  }
3323  break;
3324  }
3325  break;
3326  case 15:
3327  switch (op1) {
3328  case 0:
3329  switch (crm) {
3330  case 0:
3331  switch (op2) {
3332  case 0:
3333  return MISCREG_IL1DATA0_EL1;
3334  case 1:
3335  return MISCREG_IL1DATA1_EL1;
3336  case 2:
3337  return MISCREG_IL1DATA2_EL1;
3338  case 3:
3339  return MISCREG_IL1DATA3_EL1;
3340  }
3341  break;
3342  case 1:
3343  switch (op2) {
3344  case 0:
3345  return MISCREG_DL1DATA0_EL1;
3346  case 1:
3347  return MISCREG_DL1DATA1_EL1;
3348  case 2:
3349  return MISCREG_DL1DATA2_EL1;
3350  case 3:
3351  return MISCREG_DL1DATA3_EL1;
3352  case 4:
3353  return MISCREG_DL1DATA4_EL1;
3354  }
3355  break;
3356  }
3357  break;
3358  case 1:
3359  switch (crm) {
3360  case 0:
3361  switch (op2) {
3362  case 0:
3363  return MISCREG_L2ACTLR_EL1;
3364  }
3365  break;
3366  case 2:
3367  switch (op2) {
3368  case 0:
3369  return MISCREG_CPUACTLR_EL1;
3370  case 1:
3371  return MISCREG_CPUECTLR_EL1;
3372  case 2:
3373  return MISCREG_CPUMERRSR_EL1;
3374  case 3:
3375  return MISCREG_L2MERRSR_EL1;
3376  }
3377  break;
3378  case 3:
3379  switch (op2) {
3380  case 0:
3381  return MISCREG_CBAR_EL1;
3382 
3383  }
3384  break;
3385  }
3386  break;
3387  }
3388  // S3_<op1>_15_<Cm>_<op2>
3389  return MISCREG_IMPDEF_UNIMPL;
3390  }
3391  break;
3392  }
3393 
3394  return MISCREG_UNKNOWN;
3395 }
3396 
3397 std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
3398 
3399 void
3400 ISA::initializeMiscRegMetadata()
3401 {
3402  // the MiscReg metadata tables are shared across all instances of the
3403  // ISA object, so there's no need to initialize them multiple times.
3404  static bool completed = false;
3405  if (completed)
3406  return;
3407 
3408  // This boolean variable specifies if the system is running in aarch32 at
3409  // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
3410  // is running in aarch64 (aarch32EL3 = false)
3411  bool aarch32EL3 = haveSecurity && !highestELIs64;
3412 
3413  // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
3414  // unsupported
3415  bool SPAN = false;
3416 
3417  // Implicit error synchronization event enable (Arm 8.2+), unsupported
3418  bool IESB = false;
3419 
3420  // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
3421  // unsupported
3422  bool LSMAOE = false;
3423 
3424  // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
3425  bool nTLSMD = false;
3426 
3427  // Pointer authentication (Arm 8.3+), unsupported
3428  bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
3429  bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
3430  bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
3431  bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
3432 
3446  InitReg(MISCREG_CPSR)
3447  .allPrivileges();
3448  InitReg(MISCREG_SPSR)
3449  .allPrivileges();
3450  InitReg(MISCREG_SPSR_FIQ)
3451  .allPrivileges();
3452  InitReg(MISCREG_SPSR_IRQ)
3453  .allPrivileges();
3454  InitReg(MISCREG_SPSR_SVC)
3455  .allPrivileges();
3456  InitReg(MISCREG_SPSR_MON)
3457  .allPrivileges();
3458  InitReg(MISCREG_SPSR_ABT)
3459  .allPrivileges();
3460  InitReg(MISCREG_SPSR_HYP)
3461  .allPrivileges();
3462  InitReg(MISCREG_SPSR_UND)
3463  .allPrivileges();
3464  InitReg(MISCREG_ELR_HYP)
3465  .allPrivileges();
3466  InitReg(MISCREG_FPSID)
3467  .allPrivileges();
3468  InitReg(MISCREG_FPSCR)
3469  .allPrivileges();
3470  InitReg(MISCREG_MVFR1)
3471  .allPrivileges();
3472  InitReg(MISCREG_MVFR0)
3473  .allPrivileges();
3474  InitReg(MISCREG_FPEXC)
3475  .allPrivileges();
3476 
3477  // Helper registers
3478  InitReg(MISCREG_CPSR_MODE)
3479  .allPrivileges();
3480  InitReg(MISCREG_CPSR_Q)
3481  .allPrivileges();
3482  InitReg(MISCREG_FPSCR_EXC)
3483  .allPrivileges();
3484  InitReg(MISCREG_FPSCR_QC)
3485  .allPrivileges();
3486  InitReg(MISCREG_LOCKADDR)
3487  .allPrivileges();
3488  InitReg(MISCREG_LOCKFLAG)
3489  .allPrivileges();
3490  InitReg(MISCREG_PRRR_MAIR0)
3491  .mutex()
3492  .banked();
3493  InitReg(MISCREG_PRRR_MAIR0_NS)
3494  .mutex()
3495  .privSecure(!aarch32EL3)
3496  .bankedChild();
3497  InitReg(MISCREG_PRRR_MAIR0_S)
3498  .mutex()
3499  .bankedChild();
3500  InitReg(MISCREG_NMRR_MAIR1)
3501  .mutex()
3502  .banked();
3503  InitReg(MISCREG_NMRR_MAIR1_NS)
3504  .mutex()
3505  .privSecure(!aarch32EL3)
3506  .bankedChild();
3507  InitReg(MISCREG_NMRR_MAIR1_S)
3508  .mutex()
3509  .bankedChild();
3510  InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
3511  .mutex();
3512  InitReg(MISCREG_SCTLR_RST)
3513  .allPrivileges();
3514  InitReg(MISCREG_SEV_MAILBOX)
3515  .allPrivileges();
3516 
3517  // AArch32 CP14 registers
3518  InitReg(MISCREG_DBGDIDR)
3519  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3520  InitReg(MISCREG_DBGDSCRint)
3521  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3522  InitReg(MISCREG_DBGDCCINT)
3523  .unimplemented()
3524  .allPrivileges();
3525  InitReg(MISCREG_DBGDTRTXint)
3526  .unimplemented()
3527  .allPrivileges();
3528  InitReg(MISCREG_DBGDTRRXint)
3529  .unimplemented()
3530  .allPrivileges();
3531  InitReg(MISCREG_DBGWFAR)
3532  .unimplemented()
3533  .allPrivileges();
3534  InitReg(MISCREG_DBGVCR)
3535  .allPrivileges().exceptUserMode();
3536  InitReg(MISCREG_DBGDTRRXext)
3537  .unimplemented()
3538  .allPrivileges();
3539  InitReg(MISCREG_DBGDSCRext)
3540  .allPrivileges();
3541  InitReg(MISCREG_DBGDTRTXext)
3542  .unimplemented()
3543  .allPrivileges();
3544  InitReg(MISCREG_DBGOSECCR)
3545  .unimplemented()
3546  .allPrivileges();
3547  InitReg(MISCREG_DBGBVR0)
3548  .allPrivileges().exceptUserMode();
3549  InitReg(MISCREG_DBGBVR1)
3550  .allPrivileges().exceptUserMode();
3551  InitReg(MISCREG_DBGBVR2)
3552  .allPrivileges().exceptUserMode();
3553  InitReg(MISCREG_DBGBVR3)
3554  .allPrivileges().exceptUserMode();
3555  InitReg(MISCREG_DBGBVR4)
3556  .allPrivileges().exceptUserMode();
3557  InitReg(MISCREG_DBGBVR5)
3558  .allPrivileges().exceptUserMode();
3559  InitReg(MISCREG_DBGBVR6)
3560  .allPrivileges().exceptUserMode();
3561  InitReg(MISCREG_DBGBVR7)
3562  .allPrivileges().exceptUserMode();
3563  InitReg(MISCREG_DBGBVR8)
3564  .allPrivileges().exceptUserMode();
3565  InitReg(MISCREG_DBGBVR9)
3566  .allPrivileges().exceptUserMode();
3567  InitReg(MISCREG_DBGBVR10)
3568  .allPrivileges().exceptUserMode();
3569  InitReg(MISCREG_DBGBVR11)
3570  .allPrivileges().exceptUserMode();
3571  InitReg(MISCREG_DBGBVR12)
3572  .allPrivileges().exceptUserMode();
3573  InitReg(MISCREG_DBGBVR13)
3574  .allPrivileges().exceptUserMode();
3575  InitReg(MISCREG_DBGBVR14)
3576  .allPrivileges().exceptUserMode();
3577  InitReg(MISCREG_DBGBVR15)
3578  .allPrivileges().exceptUserMode();
3579  InitReg(MISCREG_DBGBCR0)
3580  .allPrivileges().exceptUserMode();
3581  InitReg(MISCREG_DBGBCR1)
3582  .allPrivileges().exceptUserMode();
3583  InitReg(MISCREG_DBGBCR2)
3584  .allPrivileges().exceptUserMode();
3585  InitReg(MISCREG_DBGBCR3)
3586  .allPrivileges().exceptUserMode();
3587  InitReg(MISCREG_DBGBCR4)
3588  .allPrivileges().exceptUserMode();
3589  InitReg(MISCREG_DBGBCR5)
3590  .allPrivileges().exceptUserMode();
3591  InitReg(MISCREG_DBGBCR6)
3592  .allPrivileges().exceptUserMode();
3593  InitReg(MISCREG_DBGBCR7)
3594  .allPrivileges().exceptUserMode();
3595  InitReg(MISCREG_DBGBCR8)
3596  .allPrivileges().exceptUserMode();
3597  InitReg(MISCREG_DBGBCR9)
3598  .allPrivileges().exceptUserMode();
3599  InitReg(MISCREG_DBGBCR10)
3600  .allPrivileges().exceptUserMode();
3601  InitReg(MISCREG_DBGBCR11)
3602  .allPrivileges().exceptUserMode();
3603  InitReg(MISCREG_DBGBCR12)
3604  .allPrivileges().exceptUserMode();
3605  InitReg(MISCREG_DBGBCR13)
3606  .allPrivileges().exceptUserMode();
3607  InitReg(MISCREG_DBGBCR14)
3608  .allPrivileges().exceptUserMode();
3609  InitReg(MISCREG_DBGBCR15)
3610  .allPrivileges().exceptUserMode();
3611  InitReg(MISCREG_DBGWVR0)
3612  .allPrivileges().exceptUserMode();
3613  InitReg(MISCREG_DBGWVR1)
3614  .allPrivileges().exceptUserMode();
3615  InitReg(MISCREG_DBGWVR2)
3616  .allPrivileges().exceptUserMode();
3617  InitReg(MISCREG_DBGWVR3)
3618  .allPrivileges().exceptUserMode();
3619  InitReg(MISCREG_DBGWVR4)
3620  .allPrivileges().exceptUserMode();
3621  InitReg(MISCREG_DBGWVR5)
3622  .allPrivileges().exceptUserMode();
3623  InitReg(MISCREG_DBGWVR6)
3624  .allPrivileges().exceptUserMode();
3625  InitReg(MISCREG_DBGWVR7)
3626  .allPrivileges().exceptUserMode();
3627  InitReg(MISCREG_DBGWVR8)
3628  .allPrivileges().exceptUserMode();
3629  InitReg(MISCREG_DBGWVR9)
3630  .allPrivileges().exceptUserMode();
3631  InitReg(MISCREG_DBGWVR10)
3632  .allPrivileges().exceptUserMode();
3633  InitReg(MISCREG_DBGWVR11)
3634  .allPrivileges().exceptUserMode();
3635  InitReg(MISCREG_DBGWVR12)
3636  .allPrivileges().exceptUserMode();
3637  InitReg(MISCREG_DBGWVR13)
3638  .allPrivileges().exceptUserMode();
3639  InitReg(MISCREG_DBGWVR14)
3640  .allPrivileges().exceptUserMode();
3641  InitReg(MISCREG_DBGWVR15)
3642  .allPrivileges().exceptUserMode();
3643  InitReg(MISCREG_DBGWCR0)
3644  .allPrivileges().exceptUserMode();
3645  InitReg(MISCREG_DBGWCR1)
3646  .allPrivileges().exceptUserMode();
3647  InitReg(MISCREG_DBGWCR2)
3648  .allPrivileges().exceptUserMode();
3649  InitReg(MISCREG_DBGWCR3)
3650  .allPrivileges().exceptUserMode();
3651  InitReg(MISCREG_DBGWCR4)
3652  .allPrivileges().exceptUserMode();
3653  InitReg(MISCREG_DBGWCR5)
3654  .allPrivileges().exceptUserMode();
3655  InitReg(MISCREG_DBGWCR6)
3656  .allPrivileges().exceptUserMode();
3657  InitReg(MISCREG_DBGWCR7)
3658  .allPrivileges().exceptUserMode();
3659  InitReg(MISCREG_DBGWCR8)
3660  .allPrivileges().exceptUserMode();
3661  InitReg(MISCREG_DBGWCR9)
3662  .allPrivileges().exceptUserMode();
3663  InitReg(MISCREG_DBGWCR10)
3664  .allPrivileges().exceptUserMode();
3665  InitReg(MISCREG_DBGWCR11)
3666  .allPrivileges().exceptUserMode();
3667  InitReg(MISCREG_DBGWCR12)
3668  .allPrivileges().exceptUserMode();
3669  InitReg(MISCREG_DBGWCR13)
3670  .allPrivileges().exceptUserMode();
3671  InitReg(MISCREG_DBGWCR14)
3672  .allPrivileges().exceptUserMode();
3673  InitReg(MISCREG_DBGWCR15)
3674  .allPrivileges().exceptUserMode();
3675  InitReg(MISCREG_DBGDRAR)
3676  .unimplemented()
3677  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3678  InitReg(MISCREG_DBGBXVR0)
3679  .allPrivileges().exceptUserMode();
3680  InitReg(MISCREG_DBGBXVR1)
3681  .allPrivileges().exceptUserMode();
3682  InitReg(MISCREG_DBGBXVR2)
3683  .allPrivileges().exceptUserMode();
3684  InitReg(MISCREG_DBGBXVR3)
3685  .allPrivileges().exceptUserMode();
3686  InitReg(MISCREG_DBGBXVR4)
3687  .allPrivileges().exceptUserMode();
3688  InitReg(MISCREG_DBGBXVR5)
3689  .allPrivileges().exceptUserMode();
3690  InitReg(MISCREG_DBGBXVR0)
3691  .allPrivileges().exceptUserMode();
3692  InitReg(MISCREG_DBGBXVR6)
3693  .allPrivileges().exceptUserMode();
3694  InitReg(MISCREG_DBGBXVR7)
3695  .allPrivileges().exceptUserMode();
3696  InitReg(MISCREG_DBGBXVR8)
3697  .allPrivileges().exceptUserMode();
3698  InitReg(MISCREG_DBGBXVR9)
3699  .allPrivileges().exceptUserMode();
3700  InitReg(MISCREG_DBGBXVR10)
3701  .allPrivileges().exceptUserMode();
3702  InitReg(MISCREG_DBGBXVR11)
3703  .allPrivileges().exceptUserMode();
3704  InitReg(MISCREG_DBGBXVR12)
3705  .allPrivileges().exceptUserMode();
3706  InitReg(MISCREG_DBGBXVR13)
3707  .allPrivileges().exceptUserMode();
3708  InitReg(MISCREG_DBGBXVR14)
3709  .allPrivileges().exceptUserMode();
3710  InitReg(MISCREG_DBGBXVR15)
3711  .allPrivileges().exceptUserMode();
3712  InitReg(MISCREG_DBGOSLAR)
3713  .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3714  InitReg(MISCREG_DBGOSLSR)
3715  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3716  InitReg(MISCREG_DBGOSDLR)
3717  .unimplemented()
3718  .warnNotFail()
3719  .allPrivileges();
3720  InitReg(MISCREG_DBGPRCR)
3721  .unimplemented()
3722  .allPrivileges();
3723  InitReg(MISCREG_DBGDSAR)
3724  .unimplemented()
3725  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3726  InitReg(MISCREG_DBGCLAIMSET)
3727  .unimplemented()
3728  .allPrivileges();
3729  InitReg(MISCREG_DBGCLAIMCLR)
3730  .unimplemented()
3731  .allPrivileges();
3732  InitReg(MISCREG_DBGAUTHSTATUS)
3733  .unimplemented()
3734  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3735  InitReg(MISCREG_DBGDEVID2)
3736  .unimplemented()
3737  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3738  InitReg(MISCREG_DBGDEVID1)
3739  .unimplemented()
3740  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3741  InitReg(MISCREG_DBGDEVID0)
3742  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3743  InitReg(MISCREG_TEECR)
3744  .unimplemented()
3745  .allPrivileges();
3746  InitReg(MISCREG_JIDR)
3747  .allPrivileges();
3748  InitReg(MISCREG_TEEHBR)
3749  .allPrivileges();
3750  InitReg(MISCREG_JOSCR)
3751  .allPrivileges();
3752  InitReg(MISCREG_JMCR)
3753  .allPrivileges();
3754 
3755  // AArch32 CP15 registers
3756  InitReg(MISCREG_MIDR)
3757  .allPrivileges().exceptUserMode().writes(0);
3758  InitReg(MISCREG_CTR)
3759  .allPrivileges().exceptUserMode().writes(0);
3760  InitReg(MISCREG_TCMTR)
3761  .allPrivileges().exceptUserMode().writes(0);
3762  InitReg(MISCREG_TLBTR)
3763  .allPrivileges().exceptUserMode().writes(0);
3764  InitReg(MISCREG_MPIDR)
3765  .allPrivileges().exceptUserMode().writes(0);
3766  InitReg(MISCREG_REVIDR)
3767  .unimplemented()
3768  .warnNotFail()
3769  .allPrivileges().exceptUserMode().writes(0);
3770  InitReg(MISCREG_ID_PFR0)
3771  .allPrivileges().exceptUserMode().writes(0);
3772  InitReg(MISCREG_ID_PFR1)
3773  .allPrivileges().exceptUserMode().writes(0);
3774  InitReg(MISCREG_ID_DFR0)
3775  .allPrivileges().exceptUserMode().writes(0);
3776  InitReg(MISCREG_ID_AFR0)
3777  .allPrivileges().exceptUserMode().writes(0);
3778  InitReg(MISCREG_ID_MMFR0)
3779  .allPrivileges().exceptUserMode().writes(0);
3780  InitReg(MISCREG_ID_MMFR1)
3781  .allPrivileges().exceptUserMode().writes(0);
3782  InitReg(MISCREG_ID_MMFR2)
3783  .allPrivileges().exceptUserMode().writes(0);
3784  InitReg(MISCREG_ID_MMFR3)
3785  .allPrivileges().exceptUserMode().writes(0);
3786  InitReg(MISCREG_ID_MMFR4)
3787  .allPrivileges().exceptUserMode().writes(0);
3788  InitReg(MISCREG_ID_ISAR0)
3789  .allPrivileges().exceptUserMode().writes(0);
3790  InitReg(MISCREG_ID_ISAR1)
3791  .allPrivileges().exceptUserMode().writes(0);
3792  InitReg(MISCREG_ID_ISAR2)
3793  .allPrivileges().exceptUserMode().writes(0);
3794  InitReg(MISCREG_ID_ISAR3)
3795  .allPrivileges().exceptUserMode().writes(0);
3796  InitReg(MISCREG_ID_ISAR4)
3797  .allPrivileges().exceptUserMode().writes(0);
3798  InitReg(MISCREG_ID_ISAR5)
3799  .allPrivileges().exceptUserMode().writes(0);
3800  InitReg(MISCREG_ID_ISAR6)
3801  .allPrivileges().exceptUserMode().writes(0);
3802  InitReg(MISCREG_CCSIDR)
3803  .allPrivileges().exceptUserMode().writes(0);
3804  InitReg(MISCREG_CLIDR)
3805  .allPrivileges().exceptUserMode().writes(0);
3806  InitReg(MISCREG_AIDR)
3807  .allPrivileges().exceptUserMode().writes(0);
3808  InitReg(MISCREG_CSSELR)
3809  .banked();
3810  InitReg(MISCREG_CSSELR_NS)
3811  .bankedChild()
3812  .privSecure(!aarch32EL3)
3813  .nonSecure().exceptUserMode();
3814  InitReg(MISCREG_CSSELR_S)
3815  .bankedChild()
3816  .secure().exceptUserMode();
3817  InitReg(MISCREG_VPIDR)
3818  .hyp().monNonSecure();
3819  InitReg(MISCREG_VMPIDR)
3820  .hyp().monNonSecure();
3821  InitReg(MISCREG_SCTLR)
3822  .banked()
3823  // readMiscRegNoEffect() uses this metadata
3824  // despite using children (below) as backing store
3825  .res0(0x8d22c600)
3826  .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3827  | (LSMAOE ? 0 : 0x10)
3828  | (nTLSMD ? 0 : 0x8));
3829  InitReg(MISCREG_SCTLR_NS)
3830  .bankedChild()
3831  .privSecure(!aarch32EL3)
3832  .nonSecure().exceptUserMode();
3833  InitReg(MISCREG_SCTLR_S)
3834  .bankedChild()
3835  .secure().exceptUserMode();
3836  InitReg(MISCREG_ACTLR)
3837  .banked();
3838  InitReg(MISCREG_ACTLR_NS)
3839  .bankedChild()
3840  .privSecure(!aarch32EL3)
3841  .nonSecure().exceptUserMode();
3842  InitReg(MISCREG_ACTLR_S)
3843  .bankedChild()
3844  .secure().exceptUserMode();
3845  InitReg(MISCREG_CPACR)
3846  .allPrivileges().exceptUserMode();
3847  InitReg(MISCREG_SDCR)
3848  .mon();
3849  InitReg(MISCREG_SCR)
3850  .mon().secure().exceptUserMode()
3851  .res0(0xff40) // [31:16], [6]
3852  .res1(0x0030); // [5:4]
3853  InitReg(MISCREG_SDER)
3854  .mon();
3855  InitReg(MISCREG_NSACR)
3856  .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3857  InitReg(MISCREG_HSCTLR)
3858  .hyp().monNonSecure()
3859  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3860  | (IESB ? 0 : 0x200000)
3861  | (EnDA ? 0 : 0x8000000)
3862  | (EnIB ? 0 : 0x40000000)
3863  | (EnIA ? 0 : 0x80000000))
3864  .res1(0x30c50830);
3865  InitReg(MISCREG_HACTLR)
3866  .hyp().monNonSecure();
3867  InitReg(MISCREG_HCR)
3868  .hyp().monNonSecure()
3869  .res0(0x90000000);
3870  InitReg(MISCREG_HCR2)
3871  .hyp().monNonSecure()
3872  .res0(0xffa9ff8c);
3873  InitReg(MISCREG_HDCR)
3874  .hyp().monNonSecure();
3875  InitReg(MISCREG_HCPTR)
3876  .hyp().monNonSecure();
3877  InitReg(MISCREG_HSTR)
3878  .hyp().monNonSecure();
3879  InitReg(MISCREG_HACR)
3880  .unimplemented()
3881  .warnNotFail()
3882  .hyp().monNonSecure();
3883  InitReg(MISCREG_TTBR0)
3884  .banked();
3885  InitReg(MISCREG_TTBR0_NS)
3886  .bankedChild()
3887  .privSecure(!aarch32EL3)
3888  .nonSecure().exceptUserMode();
3889  InitReg(MISCREG_TTBR0_S)
3890  .bankedChild()
3891  .secure().exceptUserMode();
3892  InitReg(MISCREG_TTBR1)
3893  .banked();
3894  InitReg(MISCREG_TTBR1_NS)
3895  .bankedChild()
3896  .privSecure(!aarch32EL3)
3897  .nonSecure().exceptUserMode();
3898  InitReg(MISCREG_TTBR1_S)
3899  .bankedChild()
3900  .secure().exceptUserMode();
3901  InitReg(MISCREG_TTBCR)
3902  .banked();
3903  InitReg(MISCREG_TTBCR_NS)
3904  .bankedChild()
3905  .privSecure(!aarch32EL3)
3906  .nonSecure().exceptUserMode();
3907  InitReg(MISCREG_TTBCR_S)
3908  .bankedChild()
3909  .secure().exceptUserMode();
3910  InitReg(MISCREG_HTCR)
3911  .hyp().monNonSecure();
3912  InitReg(MISCREG_VTCR)
3913  .hyp().monNonSecure();
3914  InitReg(MISCREG_DACR)
3915  .banked();
3916  InitReg(MISCREG_DACR_NS)
3917  .bankedChild()
3918  .privSecure(!aarch32EL3)
3919  .nonSecure().exceptUserMode();
3920  InitReg(MISCREG_DACR_S)
3921  .bankedChild()
3922  .secure().exceptUserMode();
3923  InitReg(MISCREG_DFSR)
3924  .banked();
3925  InitReg(MISCREG_DFSR_NS)
3926  .bankedChild()
3927  .privSecure(!aarch32EL3)
3928  .nonSecure().exceptUserMode();
3929  InitReg(MISCREG_DFSR_S)
3930  .bankedChild()
3931  .secure().exceptUserMode();
3932  InitReg(MISCREG_IFSR)
3933  .banked();
3934  InitReg(MISCREG_IFSR_NS)
3935  .bankedChild()
3936  .privSecure(!aarch32EL3)
3937  .nonSecure().exceptUserMode();
3938  InitReg(MISCREG_IFSR_S)
3939  .bankedChild()
3940  .secure().exceptUserMode();
3941  InitReg(MISCREG_ADFSR)
3942  .unimplemented()
3943  .warnNotFail()
3944  .banked();
3945  InitReg(MISCREG_ADFSR_NS)
3946  .unimplemented()
3947  .warnNotFail()
3948  .bankedChild()
3949  .privSecure(!aarch32EL3)
3950  .nonSecure().exceptUserMode();
3951  InitReg(MISCREG_ADFSR_S)
3952  .unimplemented()
3953  .warnNotFail()
3954  .bankedChild()
3955  .secure().exceptUserMode();
3956  InitReg(MISCREG_AIFSR)
3957  .unimplemented()
3958  .warnNotFail()
3959  .banked();
3960  InitReg(MISCREG_AIFSR_NS)
3961  .unimplemented()
3962  .warnNotFail()
3963  .bankedChild()
3964  .privSecure(!aarch32EL3)
3965  .nonSecure().exceptUserMode();
3966  InitReg(MISCREG_AIFSR_S)
3967  .unimplemented()
3968  .warnNotFail()
3969  .bankedChild()
3970  .secure().exceptUserMode();
3971  InitReg(MISCREG_HADFSR)
3972  .hyp().monNonSecure();
3973  InitReg(MISCREG_HAIFSR)
3974  .hyp().monNonSecure();
3975  InitReg(MISCREG_HSR)
3976  .hyp().monNonSecure();
3977  InitReg(MISCREG_DFAR)
3978  .banked();
3979  InitReg(MISCREG_DFAR_NS)
3980  .bankedChild()
3981  .privSecure(!aarch32EL3)
3982  .nonSecure().exceptUserMode();
3983  InitReg(MISCREG_DFAR_S)
3984  .bankedChild()
3985  .secure().exceptUserMode();
3986  InitReg(MISCREG_IFAR)
3987  .banked();
3988  InitReg(MISCREG_IFAR_NS)
3989  .bankedChild()
3990  .privSecure(!aarch32EL3)
3991  .nonSecure().exceptUserMode();
3992  InitReg(MISCREG_IFAR_S)
3993  .bankedChild()
3994  .secure().exceptUserMode();
3995  InitReg(MISCREG_HDFAR)
3996  .hyp().monNonSecure();
3997  InitReg(MISCREG_HIFAR)
3998  .hyp().monNonSecure();
3999  InitReg(MISCREG_HPFAR)
4000  .hyp().monNonSecure();
4001  InitReg(MISCREG_ICIALLUIS)
4002  .unimplemented()
4003  .warnNotFail()
4004  .writes(1).exceptUserMode();
4005  InitReg(MISCREG_BPIALLIS)
4006  .unimplemented()
4007  .warnNotFail()
4008  .writes(1).exceptUserMode();
4009  InitReg(MISCREG_PAR)
4010  .banked();
4011  InitReg(MISCREG_PAR_NS)
4012  .bankedChild()
4013  .privSecure(!aarch32EL3)
4014  .nonSecure().exceptUserMode();
4015  InitReg(MISCREG_PAR_S)
4016  .bankedChild()
4017  .secure().exceptUserMode();
4018  InitReg(MISCREG_ICIALLU)
4019  .writes(1).exceptUserMode();
4020  InitReg(MISCREG_ICIMVAU)
4021  .unimplemented()
4022  .warnNotFail()
4023  .writes(1).exceptUserMode();
4024  InitReg(MISCREG_CP15ISB)
4025  .writes(1);
4026  InitReg(MISCREG_BPIALL)
4027  .unimplemented()
4028  .warnNotFail()
4029  .writes(1).exceptUserMode();
4030  InitReg(MISCREG_BPIMVA)
4031  .unimplemented()
4032  .warnNotFail()
4033  .writes(1).exceptUserMode();
4034  InitReg(MISCREG_DCIMVAC)
4035  .unimplemented()
4036  .warnNotFail()
4037  .writes(1).exceptUserMode();
4038  InitReg(MISCREG_DCISW)
4039  .unimplemented()
4040  .warnNotFail()
4041  .writes(1).exceptUserMode();
4042  InitReg(MISCREG_ATS1CPR)
4043  .writes(1).exceptUserMode();
4044  InitReg(MISCREG_ATS1CPW)
4045  .writes(1).exceptUserMode();
4046  InitReg(MISCREG_ATS1CUR)
4047  .writes(1).exceptUserMode();
4048  InitReg(MISCREG_ATS1CUW)
4049  .writes(1).exceptUserMode();
4050  InitReg(MISCREG_ATS12NSOPR)
4051  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4052  InitReg(MISCREG_ATS12NSOPW)
4053  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4054  InitReg(MISCREG_ATS12NSOUR)
4055  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4056  InitReg(MISCREG_ATS12NSOUW)
4057  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4058  InitReg(MISCREG_DCCMVAC)
4059  .writes(1).exceptUserMode();
4060  InitReg(MISCREG_DCCSW)
4061  .unimplemented()
4062  .warnNotFail()
4063  .writes(1).exceptUserMode();
4064  InitReg(MISCREG_CP15DSB)
4065  .writes(1);
4066  InitReg(MISCREG_CP15DMB)
4067  .writes(1);
4068  InitReg(MISCREG_DCCMVAU)
4069  .unimplemented()
4070  .warnNotFail()
4071  .writes(1).exceptUserMode();
4072  InitReg(MISCREG_DCCIMVAC)
4073  .unimplemented()
4074  .warnNotFail()
4075  .writes(1).exceptUserMode();
4076  InitReg(MISCREG_DCCISW)
4077  .unimplemented()
4078  .warnNotFail()
4079  .writes(1).exceptUserMode();
4080  InitReg(MISCREG_ATS1HR)
4081  .monNonSecureWrite().hypWrite();
4082  InitReg(MISCREG_ATS1HW)
4083  .monNonSecureWrite().hypWrite();
4084  InitReg(MISCREG_TLBIALLIS)
4085  .writes(1).exceptUserMode();
4086  InitReg(MISCREG_TLBIMVAIS)
4087  .writes(1).exceptUserMode();
4088  InitReg(MISCREG_TLBIASIDIS)
4089  .writes(1).exceptUserMode();
4090  InitReg(MISCREG_TLBIMVAAIS)
4091  .writes(1).exceptUserMode();
4092  InitReg(MISCREG_TLBIMVALIS)
4093  .writes(1).exceptUserMode();
4094  InitReg(MISCREG_TLBIMVAALIS)
4095  .writes(1).exceptUserMode();
4096  InitReg(MISCREG_ITLBIALL)
4097  .writes(1).exceptUserMode();
4098  InitReg(MISCREG_ITLBIMVA)
4099  .writes(1).exceptUserMode();
4100  InitReg(MISCREG_ITLBIASID)
4101  .writes(1).exceptUserMode();
4102  InitReg(MISCREG_DTLBIALL)
4103  .writes(1).exceptUserMode();
4104  InitReg(MISCREG_DTLBIMVA)
4105  .writes(1).exceptUserMode();
4106  InitReg(MISCREG_DTLBIASID)
4107  .writes(1).exceptUserMode();
4108  InitReg(MISCREG_TLBIALL)
4109  .writes(1).exceptUserMode();
4110  InitReg(MISCREG_TLBIMVA)
4111  .writes(1).exceptUserMode();
4112  InitReg(MISCREG_TLBIASID)
4113  .writes(1).exceptUserMode();
4114  InitReg(MISCREG_TLBIMVAA)
4115  .writes(1).exceptUserMode();
4116  InitReg(MISCREG_TLBIMVAL)
4117  .writes(1).exceptUserMode();
4118  InitReg(MISCREG_TLBIMVAAL)
4119  .writes(1).exceptUserMode();
4120  InitReg(MISCREG_TLBIIPAS2IS)
4121  .monNonSecureWrite().hypWrite();
4122  InitReg(MISCREG_TLBIIPAS2LIS)
4123  .monNonSecureWrite().hypWrite();
4124  InitReg(MISCREG_TLBIALLHIS)
4125  .monNonSecureWrite().hypWrite();
4126  InitReg(MISCREG_TLBIMVAHIS)
4127  .monNonSecureWrite().hypWrite();
4128  InitReg(MISCREG_TLBIALLNSNHIS)
4129  .monNonSecureWrite().hypWrite();
4130  InitReg(MISCREG_TLBIMVALHIS)
4131  .monNonSecureWrite().hypWrite();
4132  InitReg(MISCREG_TLBIIPAS2)
4133  .monNonSecureWrite().hypWrite();
4134  InitReg(MISCREG_TLBIIPAS2L)
4135  .monNonSecureWrite().hypWrite();
4136  InitReg(MISCREG_TLBIALLH)
4137  .monNonSecureWrite().hypWrite();
4138  InitReg(MISCREG_TLBIMVAH)
4139  .monNonSecureWrite().hypWrite();
4140  InitReg(MISCREG_TLBIALLNSNH)
4141  .monNonSecureWrite().hypWrite();
4142  InitReg(MISCREG_TLBIMVALH)
4143  .monNonSecureWrite().hypWrite();
4144  InitReg(MISCREG_PMCR)
4145  .allPrivileges();
4146  InitReg(MISCREG_PMCNTENSET)
4147  .allPrivileges();
4148  InitReg(MISCREG_PMCNTENCLR)
4149  .allPrivileges();
4150  InitReg(MISCREG_PMOVSR)
4151  .allPrivileges();
4152  InitReg(MISCREG_PMSWINC)
4153  .allPrivileges();
4154  InitReg(MISCREG_PMSELR)
4155  .allPrivileges();
4156  InitReg(MISCREG_PMCEID0)
4157  .allPrivileges();
4158  InitReg(MISCREG_PMCEID1)
4159  .allPrivileges();
4160  InitReg(MISCREG_PMCCNTR)
4161  .allPrivileges();
4162  InitReg(MISCREG_PMXEVTYPER)
4163  .allPrivileges();
4164  InitReg(MISCREG_PMCCFILTR)
4165  .allPrivileges();
4166  InitReg(MISCREG_PMXEVCNTR)
4167  .allPrivileges();
4168  InitReg(MISCREG_PMUSERENR)
4169  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
4170  InitReg(MISCREG_PMINTENSET)
4171  .allPrivileges().exceptUserMode();
4172  InitReg(MISCREG_PMINTENCLR)
4173  .allPrivileges().exceptUserMode();
4174  InitReg(MISCREG_PMOVSSET)
4175  .unimplemented()
4176  .allPrivileges();
4177  InitReg(MISCREG_L2CTLR)
4178  .allPrivileges().exceptUserMode();
4179  InitReg(MISCREG_L2ECTLR)
4180  .unimplemented()
4181  .allPrivileges().exceptUserMode();
4182  InitReg(MISCREG_PRRR)
4183  .banked();
4184  InitReg(MISCREG_PRRR_NS)
4185  .bankedChild()
4186  .privSecure(!aarch32EL3)
4187  .nonSecure().exceptUserMode();
4188  InitReg(MISCREG_PRRR_S)
4189  .bankedChild()
4190  .secure().exceptUserMode();
4191  InitReg(MISCREG_MAIR0)
4192  .banked();
4193  InitReg(MISCREG_MAIR0_NS)
4194  .bankedChild()
4195  .privSecure(!aarch32EL3)
4196  .nonSecure().exceptUserMode();
4197  InitReg(MISCREG_MAIR0_S)
4198  .bankedChild()
4199  .secure().exceptUserMode();
4200  InitReg(MISCREG_NMRR)
4201  .banked();
4202  InitReg(MISCREG_NMRR_NS)
4203  .bankedChild()
4204  .privSecure(!aarch32EL3)
4205  .nonSecure().exceptUserMode();
4206  InitReg(MISCREG_NMRR_S)
4207  .bankedChild()
4208  .secure().exceptUserMode();
4209  InitReg(MISCREG_MAIR1)
4210  .banked();
4211  InitReg(MISCREG_MAIR1_NS)
4212  .bankedChild()
4213  .privSecure(!aarch32EL3)
4214  .nonSecure().exceptUserMode();
4215  InitReg(MISCREG_MAIR1_S)
4216  .bankedChild()
4217  .secure().exceptUserMode();
4218  InitReg(MISCREG_AMAIR0)
4219  .banked();
4220  InitReg(MISCREG_AMAIR0_NS)
4221  .bankedChild()
4222  .privSecure(!aarch32EL3)
4223  .nonSecure().exceptUserMode();
4224  InitReg(MISCREG_AMAIR0_S)
4225  .bankedChild()
4226  .secure().exceptUserMode();
4227  InitReg(MISCREG_AMAIR1)
4228  .banked();
4229  InitReg(MISCREG_AMAIR1_NS)
4230  .bankedChild()
4231  .privSecure(!aarch32EL3)
4232  .nonSecure().exceptUserMode();
4233  InitReg(MISCREG_AMAIR1_S)
4234  .bankedChild()
4235  .secure().exceptUserMode();
4236  InitReg(MISCREG_HMAIR0)
4237  .hyp().monNonSecure();
4238  InitReg(MISCREG_HMAIR1)
4239  .hyp().monNonSecure();
4240  InitReg(MISCREG_HAMAIR0)
4241  .unimplemented()
4242  .warnNotFail()
4243  .hyp().monNonSecure();
4244  InitReg(MISCREG_HAMAIR1)
4245  .unimplemented()
4246  .warnNotFail()
4247  .hyp().monNonSecure();
4248  InitReg(MISCREG_VBAR)
4249  .banked();
4250  InitReg(MISCREG_VBAR_NS)
4251  .bankedChild()
4252  .privSecure(!aarch32EL3)
4253  .nonSecure().exceptUserMode();
4254  InitReg(MISCREG_VBAR_S)
4255  .bankedChild()
4256  .secure().exceptUserMode();
4257  InitReg(MISCREG_MVBAR)
4258  .mon().secure()
4259  .hypRead(FullSystem && system->highestEL() == EL2)
4260  .privRead(FullSystem && system->highestEL() == EL1)
4261  .exceptUserMode();
4262  InitReg(MISCREG_RMR)
4263  .unimplemented()
4264  .mon().secure().exceptUserMode();
4265  InitReg(MISCREG_ISR)
4266  .allPrivileges().exceptUserMode().writes(0);
4267  InitReg(MISCREG_HVBAR)
4268  .hyp().monNonSecure()
4269  .res0(0x1f);
4270  InitReg(MISCREG_FCSEIDR)
4271  .unimplemented()
4272  .warnNotFail()
4273  .allPrivileges().exceptUserMode();
4274  InitReg(MISCREG_CONTEXTIDR)
4275  .banked();
4276  InitReg(MISCREG_CONTEXTIDR_NS)
4277  .bankedChild()
4278  .privSecure(!aarch32EL3)
4279  .nonSecure().exceptUserMode();
4280  InitReg(MISCREG_CONTEXTIDR_S)
4281  .bankedChild()
4282  .secure().exceptUserMode();
4283  InitReg(MISCREG_TPIDRURW)
4284  .banked();
4285  InitReg(MISCREG_TPIDRURW_NS)
4286  .bankedChild()
4287  .allPrivileges()
4288  .privSecure(!aarch32EL3)
4289  .monSecure(0);
4290  InitReg(MISCREG_TPIDRURW_S)
4291  .bankedChild()
4292  .secure();
4293  InitReg(MISCREG_TPIDRURO)
4294  .banked();
4295  InitReg(MISCREG_TPIDRURO_NS)
4296  .bankedChild()
4297  .allPrivileges()
4298  .userNonSecureWrite(0).userSecureRead(1)
4299  .privSecure(!aarch32EL3)
4300  .monSecure(0);
4301  InitReg(MISCREG_TPIDRURO_S)
4302  .bankedChild()
4303  .secure().userSecureWrite(0);
4304  InitReg(MISCREG_TPIDRPRW)
4305  .banked();
4306  InitReg(MISCREG_TPIDRPRW_NS)
4307  .bankedChild()
4308  .nonSecure().exceptUserMode()
4309  .privSecure(!aarch32EL3);
4310  InitReg(MISCREG_TPIDRPRW_S)
4311  .bankedChild()
4312  .secure().exceptUserMode();
4313  InitReg(MISCREG_HTPIDR)
4314  .hyp().monNonSecure();
4315  // BEGIN Generic Timer (AArch32)
4316  InitReg(MISCREG_CNTFRQ)
4317  .reads(1)
4318  .highest(system)
4319  .privSecureWrite(aarch32EL3);
4320  InitReg(MISCREG_CNTPCT)
4321  .unverifiable()
4322  .reads(1);
4323  InitReg(MISCREG_CNTVCT)
4324  .unverifiable()
4325  .reads(1);
4326  InitReg(MISCREG_CNTP_CTL)
4327  .banked();
4328  InitReg(MISCREG_CNTP_CTL_NS)
4329  .bankedChild()
4330  .nonSecure()
4331  .privSecure(!aarch32EL3)
4332  .res0(0xfffffff8);
4333  InitReg(MISCREG_CNTP_CTL_S)
4334  .bankedChild()
4335  .secure()
4336  .privSecure(aarch32EL3)
4337  .res0(0xfffffff8);
4338  InitReg(MISCREG_CNTP_CVAL)
4339  .banked();
4340  InitReg(MISCREG_CNTP_CVAL_NS)
4341  .bankedChild()
4342  .nonSecure()
4343  .privSecure(!aarch32EL3);
4344  InitReg(MISCREG_CNTP_CVAL_S)
4345  .bankedChild()
4346  .secure()
4347  .privSecure(aarch32EL3);
4348  InitReg(MISCREG_CNTP_TVAL)
4349  .banked();
4350  InitReg(MISCREG_CNTP_TVAL_NS)
4351  .bankedChild()
4352  .nonSecure()
4353  .privSecure(!aarch32EL3);
4354  InitReg(MISCREG_CNTP_TVAL_S)
4355  .bankedChild()
4356  .secure()
4357  .privSecure(aarch32EL3);
4358  InitReg(MISCREG_CNTV_CTL)
4359  .allPrivileges()
4360  .res0(0xfffffff8);
4361  InitReg(MISCREG_CNTV_CVAL)
4362  .allPrivileges();
4363  InitReg(MISCREG_CNTV_TVAL)
4364  .allPrivileges();
4365  InitReg(MISCREG_CNTKCTL)
4366  .allPrivileges()
4367  .exceptUserMode()
4368  .res0(0xfffdfc00);
4369  InitReg(MISCREG_CNTHCTL)
4370  .monNonSecure()
4371  .hyp()
4372  .res0(0xfffdff00);
4373  InitReg(MISCREG_CNTHP_CTL)
4374  .monNonSecure()
4375  .hyp()
4376  .res0(0xfffffff8);
4377  InitReg(MISCREG_CNTHP_CVAL)
4378  .monNonSecure()
4379  .hyp();
4380  InitReg(MISCREG_CNTHP_TVAL)
4381  .monNonSecure()
4382  .hyp();
4383  InitReg(MISCREG_CNTVOFF)
4384  .monNonSecure()
4385  .hyp();
4386  // END Generic Timer (AArch32)
4387  InitReg(MISCREG_IL1DATA0)
4388  .unimplemented()
4389  .allPrivileges().exceptUserMode();
4390  InitReg(MISCREG_IL1DATA1)
4391  .unimplemented()
4392  .allPrivileges().exceptUserMode();
4393  InitReg(MISCREG_IL1DATA2)
4394  .unimplemented()
4395  .allPrivileges().exceptUserMode();
4396  InitReg(MISCREG_IL1DATA3)
4397  .unimplemented()
4398  .allPrivileges().exceptUserMode();
4399  InitReg(MISCREG_DL1DATA0)
4400  .unimplemented()
4401  .allPrivileges().exceptUserMode();
4402  InitReg(MISCREG_DL1DATA1)
4403  .unimplemented()
4404  .allPrivileges().exceptUserMode();
4405  InitReg(MISCREG_DL1DATA2)
4406  .unimplemented()
4407  .allPrivileges().exceptUserMode();
4408  InitReg(MISCREG_DL1DATA3)
4409  .unimplemented()
4410  .allPrivileges().exceptUserMode();
4411  InitReg(MISCREG_DL1DATA4)
4412  .unimplemented()
4413  .allPrivileges().exceptUserMode();
4414  InitReg(MISCREG_RAMINDEX)
4415  .unimplemented()
4416  .writes(1).exceptUserMode();
4417  InitReg(MISCREG_L2ACTLR)
4418  .unimplemented()
4419  .allPrivileges().exceptUserMode();
4420  InitReg(MISCREG_CBAR)
4421  .unimplemented()
4422  .allPrivileges().exceptUserMode().writes(0);
4423  InitReg(MISCREG_HTTBR)
4424  .hyp().monNonSecure();
4425  InitReg(MISCREG_VTTBR)
4426  .hyp().monNonSecure();
4427  InitReg(MISCREG_CPUMERRSR)
4428  .unimplemented()
4429  .allPrivileges().exceptUserMode();
4430  InitReg(MISCREG_L2MERRSR)
4431  .unimplemented()
4432  .warnNotFail()
4433  .allPrivileges().exceptUserMode();
4434 
4435  // AArch64 registers (Op0=2);
4436  InitReg(MISCREG_MDCCINT_EL1)
4437  .allPrivileges();
4438  InitReg(MISCREG_OSDTRRX_EL1)
4439  .allPrivileges()
4440  .mapsTo(MISCREG_DBGDTRRXext);
4441  InitReg(MISCREG_MDSCR_EL1)
4442  .allPrivileges()
4443  .mapsTo(MISCREG_DBGDSCRext);
4444  InitReg(MISCREG_OSDTRTX_EL1)
4445  .allPrivileges()
4446  .mapsTo(MISCREG_DBGDTRTXext);
4447  InitReg(MISCREG_OSECCR_EL1)
4448  .allPrivileges()
4449  .mapsTo(MISCREG_DBGOSECCR);
4450  InitReg(MISCREG_DBGBVR0_EL1)
4451  .allPrivileges().exceptUserMode()
4452  .mapsTo(MISCREG_DBGBVR0, MISCREG_DBGBXVR0);
4453  InitReg(MISCREG_DBGBVR1_EL1)
4454  .allPrivileges().exceptUserMode()
4455  .mapsTo(MISCREG_DBGBVR1, MISCREG_DBGBXVR1);
4456  InitReg(MISCREG_DBGBVR2_EL1)
4457  .allPrivileges().exceptUserMode()
4458  .mapsTo(MISCREG_DBGBVR2, MISCREG_DBGBXVR2);
4459  InitReg(MISCREG_DBGBVR3_EL1)
4460  .allPrivileges().exceptUserMode()
4461  .mapsTo(MISCREG_DBGBVR3, MISCREG_DBGBXVR3);
4462  InitReg(MISCREG_DBGBVR4_EL1)
4463  .allPrivileges().exceptUserMode()
4464  .mapsTo(MISCREG_DBGBVR4, MISCREG_DBGBXVR4);
4465  InitReg(MISCREG_DBGBVR5_EL1)
4466  .allPrivileges().exceptUserMode()
4467  .mapsTo(MISCREG_DBGBVR5, MISCREG_DBGBXVR5);
4468  InitReg(MISCREG_DBGBVR6_EL1)
4469  .allPrivileges().exceptUserMode()
4470  .mapsTo(MISCREG_DBGBVR6, MISCREG_DBGBXVR6);
4471  InitReg(MISCREG_DBGBVR7_EL1)
4472  .allPrivileges().exceptUserMode()
4473  .mapsTo(MISCREG_DBGBVR7, MISCREG_DBGBXVR7);
4474  InitReg(MISCREG_DBGBVR8_EL1)
4475  .allPrivileges().exceptUserMode()
4476  .mapsTo(MISCREG_DBGBVR8, MISCREG_DBGBXVR8);
4477  InitReg(MISCREG_DBGBVR9_EL1)
4478  .allPrivileges().exceptUserMode()
4479  .mapsTo(MISCREG_DBGBVR9, MISCREG_DBGBXVR9);
4480  InitReg(MISCREG_DBGBVR10_EL1)
4481  .allPrivileges().exceptUserMode()
4482  .mapsTo(MISCREG_DBGBVR10, MISCREG_DBGBXVR10);
4483  InitReg(MISCREG_DBGBVR11_EL1)
4484  .allPrivileges().exceptUserMode()
4485  .mapsTo(MISCREG_DBGBVR11, MISCREG_DBGBXVR11);
4486  InitReg(MISCREG_DBGBVR12_EL1)
4487  .allPrivileges().exceptUserMode()
4488  .mapsTo(MISCREG_DBGBVR12, MISCREG_DBGBXVR12);
4489  InitReg(MISCREG_DBGBVR13_EL1)
4490  .allPrivileges().exceptUserMode()
4491  .mapsTo(MISCREG_DBGBVR13, MISCREG_DBGBXVR13);
4492  InitReg(MISCREG_DBGBVR14_EL1)
4493  .allPrivileges().exceptUserMode()
4494  .mapsTo(MISCREG_DBGBVR14, MISCREG_DBGBXVR14);
4495  InitReg(MISCREG_DBGBVR15_EL1)
4496  .allPrivileges().exceptUserMode()
4497  .mapsTo(MISCREG_DBGBVR15, MISCREG_DBGBXVR15);
4498  InitReg(MISCREG_DBGBCR0_EL1)
4499  .allPrivileges().exceptUserMode()
4500  .mapsTo(MISCREG_DBGBCR0);
4501  InitReg(MISCREG_DBGBCR1_EL1)
4502  .allPrivileges().exceptUserMode()
4503  .mapsTo(MISCREG_DBGBCR1);
4504  InitReg(MISCREG_DBGBCR2_EL1)
4505  .allPrivileges().exceptUserMode()
4506  .mapsTo(MISCREG_DBGBCR2);
4507  InitReg(MISCREG_DBGBCR3_EL1)
4508  .allPrivileges().exceptUserMode()
4509  .mapsTo(MISCREG_DBGBCR3);
4510  InitReg(MISCREG_DBGBCR4_EL1)
4511  .allPrivileges().exceptUserMode()
4512  .mapsTo(MISCREG_DBGBCR4);
4513  InitReg(MISCREG_DBGBCR5_EL1)
4514  .allPrivileges().exceptUserMode()
4515  .mapsTo(MISCREG_DBGBCR5);
4516  InitReg(MISCREG_DBGBCR6_EL1)
4517  .allPrivileges().exceptUserMode()
4518  .mapsTo(MISCREG_DBGBCR6);
4519  InitReg(MISCREG_DBGBCR7_EL1)
4520  .allPrivileges().exceptUserMode()
4521  .mapsTo(MISCREG_DBGBCR7);
4522  InitReg(MISCREG_DBGBCR8_EL1)
4523  .allPrivileges().exceptUserMode()
4524  .mapsTo(MISCREG_DBGBCR8);
4525  InitReg(MISCREG_DBGBCR9_EL1)
4526  .allPrivileges().exceptUserMode()
4527  .mapsTo(MISCREG_DBGBCR9);
4528  InitReg(MISCREG_DBGBCR10_EL1)
4529  .allPrivileges().exceptUserMode()
4530  .mapsTo(MISCREG_DBGBCR10);
4531  InitReg(MISCREG_DBGBCR11_EL1)
4532  .allPrivileges().exceptUserMode()
4533  .mapsTo(MISCREG_DBGBCR11);
4534  InitReg(MISCREG_DBGBCR12_EL1)
4535  .allPrivileges().exceptUserMode()
4536  .mapsTo(MISCREG_DBGBCR12);
4537  InitReg(MISCREG_DBGBCR13_EL1)
4538  .allPrivileges().exceptUserMode()
4539  .mapsTo(MISCREG_DBGBCR13);
4540  InitReg(MISCREG_DBGBCR14_EL1)
4541  .allPrivileges().exceptUserMode()
4542  .mapsTo(MISCREG_DBGBCR14);
4543  InitReg(MISCREG_DBGBCR15_EL1)
4544  .allPrivileges().exceptUserMode()
4545  .mapsTo(MISCREG_DBGBCR15);
4546  InitReg(MISCREG_DBGWVR0_EL1)
4547  .allPrivileges().exceptUserMode()
4548  .mapsTo(MISCREG_DBGWVR0);
4549  InitReg(MISCREG_DBGWVR1_EL1)
4550  .allPrivileges().exceptUserMode()
4551  .mapsTo(MISCREG_DBGWVR1);
4552  InitReg(MISCREG_DBGWVR2_EL1)
4553  .allPrivileges().exceptUserMode()
4554  .mapsTo(MISCREG_DBGWVR2);
4555  InitReg(MISCREG_DBGWVR3_EL1)
4556  .allPrivileges().exceptUserMode()
4557  .mapsTo(MISCREG_DBGWVR3);
4558  InitReg(MISCREG_DBGWVR4_EL1)
4559  .allPrivileges().exceptUserMode()
4560  .mapsTo(MISCREG_DBGWVR4);
4561  InitReg(MISCREG_DBGWVR5_EL1)
4562  .allPrivileges().exceptUserMode()
4563  .mapsTo(MISCREG_DBGWVR5);
4564  InitReg(MISCREG_DBGWVR6_EL1)
4565  .allPrivileges().exceptUserMode()
4566  .mapsTo(MISCREG_DBGWVR6);
4567  InitReg(MISCREG_DBGWVR7_EL1)
4568  .allPrivileges().exceptUserMode()
4569  .mapsTo(MISCREG_DBGWVR7);
4570  InitReg(MISCREG_DBGWVR8_EL1)
4571  .allPrivileges().exceptUserMode()
4572  .mapsTo(MISCREG_DBGWVR8);
4573  InitReg(MISCREG_DBGWVR9_EL1)
4574  .allPrivileges().exceptUserMode()
4575  .mapsTo(MISCREG_DBGWVR9);
4576  InitReg(MISCREG_DBGWVR10_EL1)
4577  .allPrivileges().exceptUserMode()
4578  .mapsTo(MISCREG_DBGWVR10);
4579  InitReg(MISCREG_DBGWVR11_EL1)
4580  .allPrivileges().exceptUserMode()
4581  .mapsTo(MISCREG_DBGWVR11);
4582  InitReg(MISCREG_DBGWVR12_EL1)
4583  .allPrivileges().exceptUserMode()
4584  .mapsTo(MISCREG_DBGWVR12);
4585  InitReg(MISCREG_DBGWVR13_EL1)
4586  .allPrivileges().exceptUserMode()
4587  .mapsTo(MISCREG_DBGWVR13);
4588  InitReg(MISCREG_DBGWVR14_EL1)
4589  .allPrivileges().exceptUserMode()
4590  .mapsTo(MISCREG_DBGWVR14);
4591  InitReg(MISCREG_DBGWVR15_EL1)
4592  .allPrivileges().exceptUserMode()
4593  .mapsTo(MISCREG_DBGWVR15);
4594  InitReg(MISCREG_DBGWCR0_EL1)
4595  .allPrivileges().exceptUserMode()
4596  .mapsTo(MISCREG_DBGWCR0);
4597  InitReg(MISCREG_DBGWCR1_EL1)
4598  .allPrivileges().exceptUserMode()
4599  .mapsTo(MISCREG_DBGWCR1);
4600  InitReg(MISCREG_DBGWCR2_EL1)
4601  .allPrivileges().exceptUserMode()
4602  .mapsTo(MISCREG_DBGWCR2);
4603  InitReg(MISCREG_DBGWCR3_EL1)
4604  .allPrivileges().exceptUserMode()
4605  .mapsTo(MISCREG_DBGWCR3);
4606  InitReg(MISCREG_DBGWCR4_EL1)
4607  .allPrivileges().exceptUserMode()
4608  .mapsTo(MISCREG_DBGWCR4);
4609  InitReg(MISCREG_DBGWCR5_EL1)
4610  .allPrivileges().exceptUserMode()
4611  .mapsTo(MISCREG_DBGWCR5);
4612  InitReg(MISCREG_DBGWCR6_EL1)
4613  .allPrivileges().exceptUserMode()
4614  .mapsTo(MISCREG_DBGWCR6);
4615  InitReg(MISCREG_DBGWCR7_EL1)
4616  .allPrivileges().exceptUserMode()
4617  .mapsTo(MISCREG_DBGWCR7);
4618  InitReg(MISCREG_DBGWCR8_EL1)
4619  .allPrivileges().exceptUserMode()
4620  .mapsTo(MISCREG_DBGWCR8);
4621  InitReg(MISCREG_DBGWCR9_EL1)
4622  .allPrivileges().exceptUserMode()
4623  .mapsTo(MISCREG_DBGWCR9);
4624  InitReg(MISCREG_DBGWCR10_EL1)
4625  .allPrivileges().exceptUserMode()
4626  .mapsTo(MISCREG_DBGWCR10);
4627  InitReg(MISCREG_DBGWCR11_EL1)
4628  .allPrivileges().exceptUserMode()
4629  .mapsTo(MISCREG_DBGWCR11);
4630  InitReg(MISCREG_DBGWCR12_EL1)
4631  .allPrivileges().exceptUserMode()
4632  .mapsTo(MISCREG_DBGWCR12);
4633  InitReg(MISCREG_DBGWCR13_EL1)
4634  .allPrivileges().exceptUserMode()
4635  .mapsTo(MISCREG_DBGWCR13);
4636  InitReg(MISCREG_DBGWCR14_EL1)
4637  .allPrivileges().exceptUserMode()
4638  .mapsTo(MISCREG_DBGWCR14);
4639  InitReg(MISCREG_DBGWCR15_EL1)
4640  .allPrivileges().exceptUserMode()
4641  .mapsTo(MISCREG_DBGWCR15);
4642  InitReg(MISCREG_MDCCSR_EL0)
4643  .allPrivileges().writes(0)
4644  //monSecureWrite(0).monNonSecureWrite(0)
4645  .mapsTo(MISCREG_DBGDSCRint);
4646  InitReg(MISCREG_MDDTR_EL0)
4647  .allPrivileges();
4648  InitReg(MISCREG_MDDTRTX_EL0)
4649  .allPrivileges();
4650  InitReg(MISCREG_MDDTRRX_EL0)
4651  .allPrivileges();
4652  InitReg(MISCREG_DBGVCR32_EL2)
4653  .hyp().mon()
4654  .mapsTo(MISCREG_DBGVCR);
4655  InitReg(MISCREG_MDRAR_EL1)
4656  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
4657  .mapsTo(MISCREG_DBGDRAR);
4658  InitReg(MISCREG_OSLAR_EL1)
4659  .allPrivileges().monSecureRead(0).monNonSecureRead(0)
4660  .mapsTo(MISCREG_DBGOSLAR);
4661  InitReg(MISCREG_OSLSR_EL1)
4662  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
4663  .mapsTo(MISCREG_DBGOSLSR);
4664  InitReg(MISCREG_OSDLR_EL1)
4665  .allPrivileges()
4666  .mapsTo(MISCREG_DBGOSDLR);
4667  InitReg(MISCREG_DBGPRCR_EL1)
4668  .allPrivileges()
4669  .mapsTo(MISCREG_DBGPRCR);
4670  InitReg(MISCREG_DBGCLAIMSET_EL1)
4671  .allPrivileges()
4672  .mapsTo(MISCREG_DBGCLAIMSET);
4673  InitReg(MISCREG_DBGCLAIMCLR_EL1)
4674  .allPrivileges()
4675  .mapsTo(MISCREG_DBGCLAIMCLR);
4676  InitReg(MISCREG_DBGAUTHSTATUS_EL1)
4677  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
4678  .mapsTo(MISCREG_DBGAUTHSTATUS);
4679  InitReg(MISCREG_TEECR32_EL1);
4680  InitReg(MISCREG_TEEHBR32_EL1);
4681 
4682  // AArch64 registers (Op0=1,3);
4683  InitReg(MISCREG_MIDR_EL1)
4684  .allPrivileges().exceptUserMode().writes(0);
4685  InitReg(MISCREG_MPIDR_EL1)
4686  .allPrivileges().exceptUserMode().writes(0);
4687  InitReg(MISCREG_REVIDR_EL1)
4688  .allPrivileges().exceptUserMode().writes(0);
4689  InitReg(MISCREG_ID_PFR0_EL1)
4690  .allPrivileges().exceptUserMode().writes(0)
4691  .mapsTo(MISCREG_ID_PFR0);
4692  InitReg(MISCREG_ID_PFR1_EL1)
4693  .allPrivileges().exceptUserMode().writes(0)
4694  .mapsTo(MISCREG_ID_PFR1);
4695  InitReg(MISCREG_ID_DFR0_EL1)
4696  .allPrivileges().exceptUserMode().writes(0)
4697  .mapsTo(MISCREG_ID_DFR0);
4698  InitReg(MISCREG_ID_AFR0_EL1)
4699  .allPrivileges().exceptUserMode().writes(0)
4700  .mapsTo(MISCREG_ID_AFR0);
4701  InitReg(MISCREG_ID_MMFR0_EL1)
4702  .allPrivileges().exceptUserMode().writes(0)
4703  .mapsTo(MISCREG_ID_MMFR0);
4704  InitReg(MISCREG_ID_MMFR1_EL1)
4705  .allPrivileges().exceptUserMode().writes(0)
4706  .mapsTo(MISCREG_ID_MMFR1);
4707  InitReg(MISCREG_ID_MMFR2_EL1)
4708  .allPrivileges().exceptUserMode().writes(0)
4709  .mapsTo(MISCREG_ID_MMFR2);
4710  InitReg(MISCREG_ID_MMFR3_EL1)
4711  .allPrivileges().exceptUserMode().writes(0)
4712  .mapsTo(MISCREG_ID_MMFR3);
4713  InitReg(MISCREG_ID_MMFR4_EL1)
4714  .allPrivileges().exceptUserMode().writes(0)
4715  .mapsTo(MISCREG_ID_MMFR4);
4716  InitReg(MISCREG_ID_ISAR0_EL1)
4717  .allPrivileges().exceptUserMode().writes(0)
4718  .mapsTo(MISCREG_ID_ISAR0);
4719  InitReg(MISCREG_ID_ISAR1_EL1)
4720  .allPrivileges().exceptUserMode().writes(0)
4721  .mapsTo(MISCREG_ID_ISAR1);
4722  InitReg(MISCREG_ID_ISAR2_EL1)
4723  .allPrivileges().exceptUserMode().writes(0)
4724  .mapsTo(MISCREG_ID_ISAR2);
4725  InitReg(MISCREG_ID_ISAR3_EL1)
4726  .allPrivileges().exceptUserMode().writes(0)
4727  .mapsTo(MISCREG_ID_ISAR3);
4728  InitReg(MISCREG_ID_ISAR4_EL1)
4729  .allPrivileges().exceptUserMode().writes(0)
4730  .mapsTo(MISCREG_ID_ISAR4);
4731  InitReg(MISCREG_ID_ISAR5_EL1)
4732  .allPrivileges().exceptUserMode().writes(0)
4733  .mapsTo(MISCREG_ID_ISAR5);
4734  InitReg(MISCREG_ID_ISAR6_EL1)
4735  .allPrivileges().exceptUserMode().writes(0)
4736  .mapsTo(MISCREG_ID_ISAR6);
4737  InitReg(MISCREG_MVFR0_EL1)
4738  .allPrivileges().exceptUserMode().writes(0);
4739  InitReg(MISCREG_MVFR1_EL1)
4740  .allPrivileges().exceptUserMode().writes(0);
4741  InitReg(MISCREG_MVFR2_EL1)
4742  .allPrivileges().exceptUserMode().writes(0);
4743  InitReg(MISCREG_ID_AA64PFR0_EL1)
4744  .allPrivileges().exceptUserMode().writes(0);
4745  InitReg(MISCREG_ID_AA64PFR1_EL1)
4746  .allPrivileges().exceptUserMode().writes(0);
4747  InitReg(MISCREG_ID_AA64DFR0_EL1)
4748  .allPrivileges().exceptUserMode().writes(0);
4749  InitReg(MISCREG_ID_AA64DFR1_EL1)
4750  .allPrivileges().exceptUserMode().writes(0);
4751  InitReg(MISCREG_ID_AA64AFR0_EL1)
4752  .allPrivileges().exceptUserMode().writes(0);
4753  InitReg(MISCREG_ID_AA64AFR1_EL1)
4754  .allPrivileges().exceptUserMode().writes(0);
4755  InitReg(MISCREG_ID_AA64ISAR0_EL1)
4756  .allPrivileges().exceptUserMode().writes(0);
4757  InitReg(MISCREG_ID_AA64ISAR1_EL1)
4758  .allPrivileges().exceptUserMode().writes(0);
4759  InitReg(MISCREG_ID_AA64MMFR0_EL1)
4760  .allPrivileges().exceptUserMode().writes(0);
4761  InitReg(MISCREG_ID_AA64MMFR1_EL1)
4762  .allPrivileges().exceptUserMode().writes(0);
4763  InitReg(MISCREG_ID_AA64MMFR2_EL1)
4764  .allPrivileges().exceptUserMode().writes(0);
4765 
4766  InitReg(MISCREG_APDAKeyHi_EL1)
4767  .allPrivileges().exceptUserMode();
4768  InitReg(MISCREG_APDAKeyLo_EL1)
4769  .allPrivileges().exceptUserMode();
4770  InitReg(MISCREG_APDBKeyHi_EL1)
4771  .allPrivileges().exceptUserMode();
4772  InitReg(MISCREG_APDBKeyLo_EL1)
4773  .allPrivileges().exceptUserMode();
4774  InitReg(MISCREG_APGAKeyHi_EL1)
4775  .allPrivileges().exceptUserMode();
4776  InitReg(MISCREG_APGAKeyLo_EL1)
4777  .allPrivileges().exceptUserMode();
4778  InitReg(MISCREG_APIAKeyHi_EL1)
4779  .allPrivileges().exceptUserMode();
4780  InitReg(MISCREG_APIAKeyLo_EL1)
4781  .allPrivileges().exceptUserMode();
4782  InitReg(MISCREG_APIBKeyHi_EL1)
4783  .allPrivileges().exceptUserMode();
4784  InitReg(MISCREG_APIBKeyLo_EL1)
4785  .allPrivileges().exceptUserMode();
4786 
4787  InitReg(MISCREG_CCSIDR_EL1)
4788  .allPrivileges().exceptUserMode().writes(0);
4789  InitReg(MISCREG_CLIDR_EL1)
4790  .allPrivileges().exceptUserMode().writes(0);
4791  InitReg(MISCREG_AIDR_EL1)
4792  .allPrivileges().exceptUserMode().writes(0);
4793  InitReg(MISCREG_CSSELR_EL1)
4794  .allPrivileges().exceptUserMode()
4795  .mapsTo(MISCREG_CSSELR_NS);
4796  InitReg(MISCREG_CTR_EL0)
4797  .reads(1);
4798  InitReg(MISCREG_DCZID_EL0)
4799  .reads(1);
4800  InitReg(MISCREG_VPIDR_EL2)
4801  .hyp().mon()
4802  .mapsTo(MISCREG_VPIDR);
4803  InitReg(MISCREG_VMPIDR_EL2)
4804  .hyp().mon()
4805  .mapsTo(MISCREG_VMPIDR);
4806  InitReg(MISCREG_SCTLR_EL1)
4807  .allPrivileges().exceptUserMode()
4808  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
4809  | (IESB ? 0 : 0x200000)
4810  | (EnDA ? 0 : 0x8000000)
4811  | (EnIB ? 0 : 0x40000000)
4812  | (EnIA ? 0 : 0x80000000))
4813  .res1(0x500800 | (SPAN ? 0 : 0x800000)
4814  | (nTLSMD ? 0 : 0x8000000)
4815  | (LSMAOE ? 0 : 0x10000000))
4816  .mapsTo(MISCREG_SCTLR_NS);
4817  InitReg(MISCREG_SCTLR_EL12)
4818  .allPrivileges().exceptUserMode()
4819  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
4820  | (IESB ? 0 : 0x200000)
4821  | (EnDA ? 0 : 0x8000000)
4822  | (EnIB ? 0 : 0x40000000)
4823  | (EnIA ? 0 : 0x80000000))
4824  .res1(0x500800 | (SPAN ? 0 : 0x800000)
4825  | (nTLSMD ? 0 : 0x8000000)
4826  | (LSMAOE ? 0 : 0x10000000))
4827  .mapsTo(MISCREG_SCTLR_EL1);
4828  InitReg(MISCREG_ACTLR_EL1)
4829  .allPrivileges().exceptUserMode()
4830  .mapsTo(MISCREG_ACTLR_NS);
4831  InitReg(MISCREG_CPACR_EL1)
4832  .allPrivileges().exceptUserMode()
4833  .mapsTo(MISCREG_CPACR);
4834  InitReg(MISCREG_CPACR_EL12)
4835  .allPrivileges().exceptUserMode()
4836  .mapsTo(MISCREG_CPACR_EL1);
4837  InitReg(MISCREG_SCTLR_EL2)
4838  .hyp().mon()
4839  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4840  | (IESB ? 0 : 0x200000)
4841  | (EnDA ? 0 : 0x8000000)
4842  | (EnIB ? 0 : 0x40000000)
4843  | (EnIA ? 0 : 0x80000000))
4844  .res1(0x30c50830)
4845  .mapsTo(MISCREG_HSCTLR);
4846  InitReg(MISCREG_ACTLR_EL2)
4847  .hyp().mon()
4848  .mapsTo(MISCREG_HACTLR);
4849  InitReg(MISCREG_HCR_EL2)
4850  .hyp().mon()
4851  .mapsTo(MISCREG_HCR, MISCREG_HCR2);
4852  InitReg(MISCREG_MDCR_EL2)
4853  .hyp().mon()
4854  .mapsTo(MISCREG_HDCR);
4855  InitReg(MISCREG_CPTR_EL2)
4856  .hyp().mon()
4857  .mapsTo(MISCREG_HCPTR);
4858  InitReg(MISCREG_HSTR_EL2)
4859  .hyp().mon()
4860  .mapsTo(MISCREG_HSTR);
4861  InitReg(MISCREG_HACR_EL2)
4862  .hyp().mon()
4863  .mapsTo(MISCREG_HACR);
4864  InitReg(MISCREG_SCTLR_EL3)
4865  .mon()
4866  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4867  | (IESB ? 0 : 0x200000)
4868  | (EnDA ? 0 : 0x8000000)
4869  | (EnIB ? 0 : 0x40000000)
4870  | (EnIA ? 0 : 0x80000000))
4871  .res1(0x30c50830);
4872  InitReg(MISCREG_ACTLR_EL3)
4873  .mon();
4874  InitReg(MISCREG_SCR_EL3)
4875  .mon()
4876  .mapsTo(MISCREG_SCR); // NAM D7-2005
4877  InitReg(MISCREG_SDER32_EL3)
4878  .mon()
4879  .mapsTo(MISCREG_SDER);
4880  InitReg(MISCREG_CPTR_EL3)
4881  .mon();
4882  InitReg(MISCREG_MDCR_EL3)
4883  .mon()
4884  .mapsTo(MISCREG_SDCR);
4885  InitReg(MISCREG_TTBR0_EL1)
4886  .allPrivileges().exceptUserMode()
4887  .mapsTo(MISCREG_TTBR0_NS);
4888  InitReg(MISCREG_TTBR0_EL12)
4889  .allPrivileges().exceptUserMode()
4890  .mapsTo(MISCREG_TTBR0_EL1);
4891  InitReg(MISCREG_TTBR1_EL1)
4892  .allPrivileges().exceptUserMode()
4893  .mapsTo(MISCREG_TTBR1_NS);
4894  InitReg(MISCREG_TTBR1_EL12)
4895  .allPrivileges().exceptUserMode()
4896  .mapsTo(MISCREG_TTBR1_EL1);
4897  InitReg(MISCREG_TCR_EL1)
4898  .allPrivileges().exceptUserMode()
4899  .mapsTo(MISCREG_TTBCR_NS);
4900  InitReg(MISCREG_TCR_EL12)
4901  .allPrivileges().exceptUserMode()
4902  .mapsTo(MISCREG_TTBCR_NS);
4903  InitReg(MISCREG_TTBR0_EL2)
4904  .hyp().mon()
4905  .mapsTo(MISCREG_HTTBR);
4906  InitReg(MISCREG_TTBR1_EL2)
4907  .hyp().mon();
4908  InitReg(MISCREG_TCR_EL2)
4909  .hyp().mon()
4910  .mapsTo(MISCREG_HTCR);
4911  InitReg(MISCREG_VTTBR_EL2)
4912  .hyp().mon()
4913  .mapsTo(MISCREG_VTTBR);
4914  InitReg(MISCREG_VTCR_EL2)
4915  .hyp().mon()
4916  .mapsTo(MISCREG_VTCR);
4917  InitReg(MISCREG_VSTTBR_EL2)
4918  .hypSecure().mon();
4919  InitReg(MISCREG_VSTCR_EL2)
4920  .hypSecure().mon();
4921  InitReg(MISCREG_TTBR0_EL3)
4922  .mon();
4923  InitReg(MISCREG_TCR_EL3)
4924  .mon();
4925  InitReg(MISCREG_DACR32_EL2)
4926  .hyp().mon()
4927  .mapsTo(MISCREG_DACR_NS);
4928  InitReg(MISCREG_SPSR_EL1)
4929  .allPrivileges().exceptUserMode()
4930  .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4931  InitReg(MISCREG_SPSR_EL12)
4932  .allPrivileges().exceptUserMode()
4933  .mapsTo(MISCREG_SPSR_SVC);
4934  InitReg(MISCREG_ELR_EL1)
4935  .allPrivileges().exceptUserMode();
4936  InitReg(MISCREG_ELR_EL12)
4937  .allPrivileges().exceptUserMode()
4938  .mapsTo(MISCREG_ELR_EL1);
4939  InitReg(MISCREG_SP_EL0)
4940  .allPrivileges().exceptUserMode();
4941  InitReg(MISCREG_SPSEL)
4942  .allPrivileges().exceptUserMode();
4943  InitReg(MISCREG_CURRENTEL)
4944  .allPrivileges().exceptUserMode().writes(0);
4945  InitReg(MISCREG_PAN)
4946  .allPrivileges().exceptUserMode()
4947  .implemented(havePAN);
4948  InitReg(MISCREG_NZCV)
4949  .allPrivileges();
4950  InitReg(MISCREG_DAIF)
4951  .allPrivileges();
4952  InitReg(MISCREG_FPCR)
4953  .allPrivileges();
4954  InitReg(MISCREG_FPSR)
4955  .allPrivileges();
4956  InitReg(MISCREG_DSPSR_EL0)
4957  .allPrivileges();
4958  InitReg(MISCREG_DLR_EL0)
4959  .allPrivileges();
4960  InitReg(MISCREG_SPSR_EL2)
4961  .hyp().mon()
4962  .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4963  InitReg(MISCREG_ELR_EL2)
4964  .hyp().mon();
4965  InitReg(MISCREG_SP_EL1)
4966  .hyp().mon();
4967  InitReg(MISCREG_SPSR_IRQ_AA64)
4968  .hyp().mon();
4969  InitReg(MISCREG_SPSR_ABT_AA64)
4970  .hyp().mon();
4971  InitReg(MISCREG_SPSR_UND_AA64)
4972  .hyp().mon();
4973  InitReg(MISCREG_SPSR_FIQ_AA64)
4974  .hyp().mon();
4975  InitReg(MISCREG_SPSR_EL3)
4976  .mon()
4977  .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4978  InitReg(MISCREG_ELR_EL3)
4979  .mon();
4980  InitReg(MISCREG_SP_EL2)
4981  .mon();
4982  InitReg(MISCREG_AFSR0_EL1)
4983  .allPrivileges().exceptUserMode()
4984  .mapsTo(MISCREG_ADFSR_NS);
4985  InitReg(MISCREG_AFSR0_EL12)
4986  .allPrivileges().exceptUserMode()
4987  .mapsTo(MISCREG_ADFSR_NS);
4988  InitReg(MISCREG_AFSR1_EL1)
4989  .allPrivileges().exceptUserMode()
4990  .mapsTo(MISCREG_AIFSR_NS);
4991  InitReg(MISCREG_AFSR1_EL12)
4992  .allPrivileges().exceptUserMode()
4993  .mapsTo(MISCREG_AIFSR_NS);
4994  InitReg(MISCREG_ESR_EL1)
4995  .allPrivileges().exceptUserMode();
4996  InitReg(MISCREG_ESR_EL12)
4997  .allPrivileges().exceptUserMode()
4998  .mapsTo(MISCREG_ESR_EL1);
4999  InitReg(MISCREG_IFSR32_EL2)
5000  .hyp().mon()
5001  .mapsTo(MISCREG_IFSR_NS);
5002  InitReg(MISCREG_AFSR0_EL2)
5003  .hyp().mon()
5004  .mapsTo(MISCREG_HADFSR);
5005  InitReg(MISCREG_AFSR1_EL2)
5006  .hyp().mon()
5007  .mapsTo(MISCREG_HAIFSR);
5008  InitReg(MISCREG_ESR_EL2)
5009  .hyp().mon()
5010  .mapsTo(MISCREG_HSR);
5011  InitReg(MISCREG_FPEXC32_EL2)
5012  .hyp().mon().mapsTo(MISCREG_FPEXC);
5013  InitReg(MISCREG_AFSR0_EL3)
5014  .mon();
5015  InitReg(MISCREG_AFSR1_EL3)
5016  .mon();
5017  InitReg(MISCREG_ESR_EL3)
5018  .mon();
5019  InitReg(MISCREG_FAR_EL1)
5020  .allPrivileges().exceptUserMode()
5021  .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
5022  InitReg(MISCREG_FAR_EL12)
5023  .allPrivileges().exceptUserMode()
5024  .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
5025  InitReg(MISCREG_FAR_EL2)
5026  .hyp().mon()
5027  .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
5028  InitReg(MISCREG_HPFAR_EL2)
5029  .hyp().mon()
5030  .mapsTo(MISCREG_HPFAR);
5031  InitReg(MISCREG_FAR_EL3)
5032  .mon();
5033  InitReg(MISCREG_IC_IALLUIS)
5034  .warnNotFail()
5035  .writes(1).exceptUserMode();
5036  InitReg(MISCREG_PAR_EL1)
5037  .allPrivileges().exceptUserMode()
5038  .mapsTo(MISCREG_PAR_NS);
5039  InitReg(MISCREG_IC_IALLU)
5040  .warnNotFail()
5041  .writes(1).exceptUserMode();
5042  InitReg(MISCREG_DC_IVAC_Xt)
5043  .warnNotFail()
5044  .writes(1).exceptUserMode();
5045  InitReg(MISCREG_DC_ISW_Xt)
5046  .warnNotFail()
5047  .writes(1).exceptUserMode();
5048  InitReg(MISCREG_AT_S1E1R_Xt)
5049  .writes(1).exceptUserMode();
5050  InitReg(MISCREG_AT_S1E1W_Xt)
5051  .writes(1).exceptUserMode();
5052  InitReg(MISCREG_AT_S1E0R_Xt)
5053  .writes(1).exceptUserMode();
5054  InitReg(MISCREG_AT_S1E0W_Xt)
5055  .writes(1).exceptUserMode();
5056  InitReg(MISCREG_DC_CSW_Xt)
5057  .warnNotFail()
5058  .writes(1).exceptUserMode();
5059  InitReg(MISCREG_DC_CISW_Xt)
5060  .warnNotFail()
5061  .writes(1).exceptUserMode();
5062  InitReg(MISCREG_DC_ZVA_Xt)
5063  .warnNotFail()
5064  .writes(1).userSecureWrite(0);
5065  InitReg(MISCREG_IC_IVAU_Xt)
5066  .writes(1);
5067  InitReg(MISCREG_DC_CVAC_Xt)
5068  .warnNotFail()
5069  .writes(1);
5070  InitReg(MISCREG_DC_CVAU_Xt)
5071  .warnNotFail()
5072  .writes(1);
5073  InitReg(MISCREG_DC_CIVAC_Xt)
5074  .warnNotFail()
5075  .writes(1);
5076  InitReg(MISCREG_AT_S1E2R_Xt)
5077  .monNonSecureWrite().hypWrite();
5078  InitReg(MISCREG_AT_S1E2W_Xt)
5079  .monNonSecureWrite().hypWrite();
5080  InitReg(MISCREG_AT_S12E1R_Xt)
5081  .hypWrite().monSecureWrite().monNonSecureWrite();
5082  InitReg(MISCREG_AT_S12E1W_Xt)
5083  .hypWrite().monSecureWrite().monNonSecureWrite();
5084  InitReg(MISCREG_AT_S12E0R_Xt)
5085  .hypWrite().monSecureWrite().monNonSecureWrite();
5086  InitReg(MISCREG_AT_S12E0W_Xt)
5087  .hypWrite().monSecureWrite().monNonSecureWrite();
5088  InitReg(MISCREG_AT_S1E3R_Xt)
5089  .monSecureWrite().monNonSecureWrite();
5090  InitReg(MISCREG_AT_S1E3W_Xt)
5091  .monSecureWrite().monNonSecureWrite();
5092  InitReg(MISCREG_TLBI_VMALLE1IS)
5093  .writes(1).exceptUserMode();
5094  InitReg(MISCREG_TLBI_VAE1IS_Xt)
5095  .writes(1).exceptUserMode();
5096  InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
5097  .writes(1).exceptUserMode();
5098  InitReg(MISCREG_TLBI_VAAE1IS_Xt)
5099  .writes(1).exceptUserMode();
5100  InitReg(MISCREG_TLBI_VALE1IS_Xt)
5101  .writes(1).exceptUserMode();
5102  InitReg(MISCREG_TLBI_VAALE1IS_Xt)
5103  .writes(1).exceptUserMode();
5104  InitReg(MISCREG_TLBI_VMALLE1)
5105  .writes(1).exceptUserMode();
5106  InitReg(MISCREG_TLBI_VAE1_Xt)
5107  .writes(1).exceptUserMode();
5108  InitReg(MISCREG_TLBI_ASIDE1_Xt)
5109  .writes(1).exceptUserMode();
5110  InitReg(MISCREG_TLBI_VAAE1_Xt)
5111  .writes(1).exceptUserMode();
5112  InitReg(MISCREG_TLBI_VALE1_Xt)
5113  .writes(1).exceptUserMode();
5114  InitReg(MISCREG_TLBI_VAALE1_Xt)
5115  .writes(1).exceptUserMode();
5116  InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
5117  .hypWrite().monSecureWrite().monNonSecureWrite();
5118  InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
5119  .hypWrite().monSecureWrite().monNonSecureWrite();
5120  InitReg(MISCREG_TLBI_ALLE2IS)
5121  .monNonSecureWrite().hypWrite();
5122  InitReg(MISCREG_TLBI_VAE2IS_Xt)
5123  .monNonSecureWrite().hypWrite();
5124  InitReg(MISCREG_TLBI_ALLE1IS)
5125  .hypWrite().monSecureWrite().monNonSecureWrite();
5126  InitReg(MISCREG_TLBI_VALE2IS_Xt)
5127  .monNonSecureWrite().hypWrite();
5128  InitReg(MISCREG_TLBI_VMALLS12E1IS)
5129  .hypWrite().monSecureWrite().monNonSecureWrite();
5130  InitReg(MISCREG_TLBI_IPAS2E1_Xt)
5131  .hypWrite().monSecureWrite().monNonSecureWrite();
5132  InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
5133  .hypWrite().monSecureWrite().monNonSecureWrite();
5134  InitReg(MISCREG_TLBI_ALLE2)
5135  .monNonSecureWrite().hypWrite();
5136  InitReg(MISCREG_TLBI_VAE2_Xt)
5137  .monNonSecureWrite().hypWrite();
5138  InitReg(MISCREG_TLBI_ALLE1)
5139  .hypWrite().monSecureWrite().monNonSecureWrite();
5140  InitReg(MISCREG_TLBI_VALE2_Xt)
5141  .monNonSecureWrite().hypWrite();
5142  InitReg(MISCREG_TLBI_VMALLS12E1)
5143  .hypWrite().monSecureWrite().monNonSecureWrite();
5144  InitReg(MISCREG_TLBI_ALLE3IS)
5145  .monSecureWrite().monNonSecureWrite();
5146  InitReg(MISCREG_TLBI_VAE3IS_Xt)
5147  .monSecureWrite().monNonSecureWrite();
5148  InitReg(MISCREG_TLBI_VALE3IS_Xt)
5149  .monSecureWrite().monNonSecureWrite();
5150  InitReg(MISCREG_TLBI_ALLE3)
5151  .monSecureWrite().monNonSecureWrite();
5152  InitReg(MISCREG_TLBI_VAE3_Xt)
5153  .monSecureWrite().monNonSecureWrite();
5154  InitReg(MISCREG_TLBI_VALE3_Xt)
5155  .monSecureWrite().monNonSecureWrite();
5156  InitReg(MISCREG_PMINTENSET_EL1)
5157  .allPrivileges().exceptUserMode()
5158  .mapsTo(MISCREG_PMINTENSET);
5159  InitReg(MISCREG_PMINTENCLR_EL1)
5160  .allPrivileges().exceptUserMode()
5161  .mapsTo(MISCREG_PMINTENCLR);
5162  InitReg(MISCREG_PMCR_EL0)
5163  .allPrivileges()
5164  .mapsTo(MISCREG_PMCR);
5165  InitReg(MISCREG_PMCNTENSET_EL0)
5166  .allPrivileges()
5167  .mapsTo(MISCREG_PMCNTENSET);
5168  InitReg(MISCREG_PMCNTENCLR_EL0)
5169  .allPrivileges()
5170  .mapsTo(MISCREG_PMCNTENCLR);
5171  InitReg(MISCREG_PMOVSCLR_EL0)
5172  .allPrivileges();
5173 // .mapsTo(MISCREG_PMOVSCLR);
5174  InitReg(MISCREG_PMSWINC_EL0)
5175  .writes(1).user()
5176  .mapsTo(MISCREG_PMSWINC);
5177  InitReg(MISCREG_PMSELR_EL0)
5178  .allPrivileges()
5179  .mapsTo(MISCREG_PMSELR);
5180  InitReg(MISCREG_PMCEID0_EL0)
5181  .reads(1).user()
5182  .mapsTo(MISCREG_PMCEID0);
5183  InitReg(MISCREG_PMCEID1_EL0)
5184  .reads(1).user()
5185  .mapsTo(MISCREG_PMCEID1);
5186  InitReg(MISCREG_PMCCNTR_EL0)
5187  .allPrivileges()
5188  .mapsTo(MISCREG_PMCCNTR);
5189  InitReg(MISCREG_PMXEVTYPER_EL0)
5190  .allPrivileges()
5191  .mapsTo(MISCREG_PMXEVTYPER);
5192  InitReg(MISCREG_PMCCFILTR_EL0)
5193  .allPrivileges();
5194  InitReg(MISCREG_PMXEVCNTR_EL0)
5195  .allPrivileges()
5196  .mapsTo(MISCREG_PMXEVCNTR);
5197  InitReg(MISCREG_PMUSERENR_EL0)
5198  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
5199  .mapsTo(MISCREG_PMUSERENR);
5200  InitReg(MISCREG_PMOVSSET_EL0)
5201  .allPrivileges()
5202  .mapsTo(MISCREG_PMOVSSET);
5203  InitReg(MISCREG_MAIR_EL1)
5204  .allPrivileges().exceptUserMode()
5205  .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
5206  InitReg(MISCREG_MAIR_EL12)
5207  .allPrivileges().exceptUserMode()
5208  .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
5209  InitReg(MISCREG_AMAIR_EL1)
5210  .allPrivileges().exceptUserMode()
5211  .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
5212  InitReg(MISCREG_AMAIR_EL12)
5213  .allPrivileges().exceptUserMode()
5214  .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
5215  InitReg(MISCREG_MAIR_EL2)
5216  .hyp().mon()
5217  .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
5218  InitReg(MISCREG_AMAIR_EL2)
5219  .hyp().mon()
5220  .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
5221  InitReg(MISCREG_MAIR_EL3)
5222  .mon();
5223  InitReg(MISCREG_AMAIR_EL3)
5224  .mon();
5225  InitReg(MISCREG_L2CTLR_EL1)
5226  .allPrivileges().exceptUserMode();
5227  InitReg(MISCREG_L2ECTLR_EL1)
5228  .allPrivileges().exceptUserMode();
5229  InitReg(MISCREG_VBAR_EL1)
5230  .allPrivileges().exceptUserMode()
5231  .mapsTo(MISCREG_VBAR_NS);
5232  InitReg(MISCREG_VBAR_EL12)
5233  .allPrivileges().exceptUserMode()
5234  .mapsTo(MISCREG_VBAR_NS);
5235  InitReg(MISCREG_RVBAR_EL1)
5236  .allPrivileges().exceptUserMode().writes(0);
5237  InitReg(MISCREG_ISR_EL1)
5238  .allPrivileges().exceptUserMode().writes(0);
5239  InitReg(MISCREG_VBAR_EL2)
5240  .hyp().mon()
5241  .res0(0x7ff)
5242  .mapsTo(MISCREG_HVBAR);
5243  InitReg(MISCREG_RVBAR_EL2)
5244  .mon().hyp().writes(0);
5245  InitReg(MISCREG_VBAR_EL3)
5246  .mon();
5247  InitReg(MISCREG_RVBAR_EL3)
5248  .mon().writes(0);
5249  InitReg(MISCREG_RMR_EL3)
5250  .mon();
5251  InitReg(MISCREG_CONTEXTIDR_EL1)
5252  .allPrivileges().exceptUserMode()
5253  .mapsTo(MISCREG_CONTEXTIDR_NS);
5254  InitReg(MISCREG_CONTEXTIDR_EL12)
5255  .allPrivileges().exceptUserMode()
5256  .mapsTo(MISCREG_CONTEXTIDR_NS);
5257  InitReg(MISCREG_TPIDR_EL1)
5258  .allPrivileges().exceptUserMode()
5259  .mapsTo(MISCREG_TPIDRPRW_NS);
5260  InitReg(MISCREG_TPIDR_EL0)
5261  .allPrivileges()
5262  .mapsTo(MISCREG_TPIDRURW_NS);
5263  InitReg(MISCREG_TPIDRRO_EL0)
5264  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
5265  .mapsTo(MISCREG_TPIDRURO_NS);
5266  InitReg(MISCREG_TPIDR_EL2)
5267  .hyp().mon()
5268  .mapsTo(MISCREG_HTPIDR);
5269  InitReg(MISCREG_TPIDR_EL3)
5270  .mon();
5271  // BEGIN Generic Timer (AArch64)
5272  InitReg(MISCREG_CNTFRQ_EL0)
5273  .reads(1)
5274  .highest(system)
5275  .privSecureWrite(aarch32EL3)
5276  .mapsTo(MISCREG_CNTFRQ);
5277  InitReg(MISCREG_CNTPCT_EL0)
5278  .unverifiable()
5279  .reads(1)
5280  .mapsTo(MISCREG_CNTPCT);
5281  InitReg(MISCREG_CNTVCT_EL0)
5282  .unverifiable()
5283  .reads(1)
5284  .mapsTo(MISCREG_CNTVCT);
5285  InitReg(MISCREG_CNTP_CTL_EL0)
5286  .allPrivileges()
5287  .res0(0xfffffffffffffff8)
5288  .mapsTo(MISCREG_CNTP_CTL_NS);
5289  InitReg(MISCREG_CNTP_CVAL_EL0)
5290  .allPrivileges()
5291  .mapsTo(MISCREG_CNTP_CVAL_NS);
5292  InitReg(MISCREG_CNTP_TVAL_EL0)
5293  .allPrivileges()
5294  .res0(0xffffffff00000000)
5295  .mapsTo(MISCREG_CNTP_TVAL_NS);
5296  InitReg(MISCREG_CNTV_CTL_EL0)
5297  .allPrivileges()
5298  .res0(0xfffffffffffffff8)
5299  .mapsTo(MISCREG_CNTV_CTL);
5300  InitReg(MISCREG_CNTV_CVAL_EL0)
5301  .allPrivileges()
5302  .mapsTo(MISCREG_CNTV_CVAL);
5303  InitReg(MISCREG_CNTV_TVAL_EL0)
5304  .allPrivileges()
5305  .res0(0xffffffff00000000)
5306  .mapsTo(MISCREG_CNTV_TVAL);
5307  InitReg(MISCREG_CNTP_CTL_EL02)
5308  .monE2H()
5309  .hypE2H()
5310  .res0(0xfffffffffffffff8)
5311  .mapsTo(MISCREG_CNTP_CTL_NS);
5312  InitReg(MISCREG_CNTP_CVAL_EL02)
5313  .monE2H()
5314  .hypE2H()
5315  .mapsTo(MISCREG_CNTP_CVAL_NS);
5316  InitReg(MISCREG_CNTP_TVAL_EL02)
5317  .monE2H()
5318  .hypE2H()
5319  .res0(0xffffffff00000000)
5320  .mapsTo(MISCREG_CNTP_TVAL_NS);
5321  InitReg(MISCREG_CNTV_CTL_EL02)
5322  .monE2H()
5323  .hypE2H()
5324  .res0(0xfffffffffffffff8)
5325  .mapsTo(MISCREG_CNTV_CTL);
5326  InitReg(MISCREG_CNTV_CVAL_EL02)
5327  .monE2H()
5328  .hypE2H()
5329  .mapsTo(MISCREG_CNTV_CVAL);
5330  InitReg(MISCREG_CNTV_TVAL_EL02)
5331  .monE2H()
5332  .hypE2H()
5333  .res0(0xffffffff00000000)
5334  .mapsTo(MISCREG_CNTV_TVAL);
5335  InitReg(MISCREG_CNTKCTL_EL1)
5336  .allPrivileges()
5337  .exceptUserMode()
5338  .res0(0xfffffffffffdfc00)
5339  .mapsTo(MISCREG_CNTKCTL);
5340  InitReg(MISCREG_CNTKCTL_EL12)
5341  .monE2H()
5342  .hypE2H()
5343  .res0(0xfffffffffffdfc00)
5344  .mapsTo(MISCREG_CNTKCTL);
5345  InitReg(MISCREG_CNTPS_CTL_EL1)
5346  .mon()
5347  .privSecure()
5348  .res0(0xfffffffffffffff8);
5349  InitReg(MISCREG_CNTPS_CVAL_EL1)
5350  .mon()
5351  .privSecure();
5352  InitReg(MISCREG_CNTPS_TVAL_EL1)
5353  .mon()
5354  .privSecure()
5355  .res0(0xffffffff00000000);
5356  InitReg(MISCREG_CNTHCTL_EL2)
5357  .mon()
5358  .hyp()
5359  .res0(0xfffffffffffc0000)
5360  .mapsTo(MISCREG_CNTHCTL);
5361  InitReg(MISCREG_CNTHP_CTL_EL2)
5362  .mon()
5363  .hyp()
5364  .res0(0xfffffffffffffff8)
5365  .mapsTo(MISCREG_CNTHP_CTL);
5366  InitReg(MISCREG_CNTHP_CVAL_EL2)
5367  .mon()
5368  .hyp()
5369  .mapsTo(MISCREG_CNTHP_CVAL);
5370  InitReg(MISCREG_CNTHP_TVAL_EL2)
5371  .mon()
5372  .hyp()
5373  .res0(0xffffffff00000000)
5374  .mapsTo(MISCREG_CNTHP_TVAL);
5375  InitReg(MISCREG_CNTHPS_CTL_EL2)
5376  .mon()
5377  .hyp()
5378  .res0(0xfffffffffffffff8)
5379  .unimplemented();
5380  InitReg(MISCREG_CNTHPS_CVAL_EL2)
5381  .mon()
5382  .hyp()
5383  .res0(0xfffffffffffffff8)
5384  .unimplemented();
5385  InitReg(MISCREG_CNTHPS_TVAL_EL2)
5386  .mon()
5387  .hyp()
5388  .res0(0xfffffffffffffff8)
5389  .unimplemented();
5390  InitReg(MISCREG_CNTHV_CTL_EL2)
5391  .mon()
5392  .hyp()
5393  .res0(0xfffffffffffffff8);
5394  InitReg(MISCREG_CNTHV_CVAL_EL2)
5395  .mon()
5396  .hyp();
5397  InitReg(MISCREG_CNTHV_TVAL_EL2)
5398  .mon()
5399  .hyp()
5400  .res0(0xffffffff00000000);
5401  InitReg(MISCREG_CNTHVS_CTL_EL2)
5402  .mon()
5403  .hyp()
5404  .res0(0xfffffffffffffff8)
5405  .unimplemented();
5406  InitReg(MISCREG_CNTHVS_CVAL_EL2)
5407  .mon()
5408  .hyp()
5409  .res0(0xfffffffffffffff8)
5410  .unimplemented();
5411  InitReg(MISCREG_CNTHVS_TVAL_EL2)
5412  .mon()
5413  .hyp()
5414  .res0(0xfffffffffffffff8)
5415  .unimplemented();
5416  // ENDIF Armv8.1-VHE
5417  InitReg(MISCREG_CNTVOFF_EL2)
5418  .mon()
5419  .hyp()
5420  .mapsTo(MISCREG_CNTVOFF);
5421  // END Generic Timer (AArch64)
5422  InitReg(MISCREG_PMEVCNTR0_EL0)
5423  .allPrivileges();
5424 // .mapsTo(MISCREG_PMEVCNTR0);
5425  InitReg(MISCREG_PMEVCNTR1_EL0)
5426  .allPrivileges();
5427 // .mapsTo(MISCREG_PMEVCNTR1);
5428  InitReg(MISCREG_PMEVCNTR2_EL0)
5429  .allPrivileges();
5430 // .mapsTo(MISCREG_PMEVCNTR2);
5431  InitReg(MISCREG_PMEVCNTR3_EL0)
5432  .allPrivileges();
5433 // .mapsTo(MISCREG_PMEVCNTR3);
5434  InitReg(MISCREG_PMEVCNTR4_EL0)
5435  .allPrivileges();
5436 // .mapsTo(MISCREG_PMEVCNTR4);
5437  InitReg(MISCREG_PMEVCNTR5_EL0)
5438  .allPrivileges();
5439 // .mapsTo(MISCREG_PMEVCNTR5);
5440  InitReg(MISCREG_PMEVTYPER0_EL0)
5441  .allPrivileges();
5442 // .mapsTo(MISCREG_PMEVTYPER0);
5443  InitReg(MISCREG_PMEVTYPER1_EL0)
5444  .allPrivileges();
5445 // .mapsTo(MISCREG_PMEVTYPER1);
5446  InitReg(MISCREG_PMEVTYPER2_EL0)
5447  .allPrivileges();
5448 // .mapsTo(MISCREG_PMEVTYPER2);
5449  InitReg(MISCREG_PMEVTYPER3_EL0)
5450  .allPrivileges();
5451 // .mapsTo(MISCREG_PMEVTYPER3);
5452  InitReg(MISCREG_PMEVTYPER4_EL0)
5453  .allPrivileges();
5454 // .mapsTo(MISCREG_PMEVTYPER4);
5455  InitReg(MISCREG_PMEVTYPER5_EL0)
5456  .allPrivileges();
5457 // .mapsTo(MISCREG_PMEVTYPER5);
5458  InitReg(MISCREG_IL1DATA0_EL1)
5459  .allPrivileges().exceptUserMode();
5460  InitReg(MISCREG_IL1DATA1_EL1)
5461  .allPrivileges().exceptUserMode();
5462  InitReg(MISCREG_IL1DATA2_EL1)
5463  .allPrivileges().exceptUserMode();
5464  InitReg(MISCREG_IL1DATA3_EL1)
5465  .allPrivileges().exceptUserMode();
5466  InitReg(MISCREG_DL1DATA0_EL1)
5467  .allPrivileges().exceptUserMode();
5468  InitReg(MISCREG_DL1DATA1_EL1)
5469  .allPrivileges().exceptUserMode();
5470  InitReg(MISCREG_DL1DATA2_EL1)
5471  .allPrivileges().exceptUserMode();
5472  InitReg(MISCREG_DL1DATA3_EL1)
5473  .allPrivileges().exceptUserMode();
5474  InitReg(MISCREG_DL1DATA4_EL1)
5475  .allPrivileges().exceptUserMode();
5476  InitReg(MISCREG_L2ACTLR_EL1)
5477  .allPrivileges().exceptUserMode();
5478  InitReg(MISCREG_CPUACTLR_EL1)
5479  .allPrivileges().exceptUserMode();
5480  InitReg(MISCREG_CPUECTLR_EL1)
5481  .allPrivileges().exceptUserMode();
5482  InitReg(MISCREG_CPUMERRSR_EL1)
5483  .allPrivileges().exceptUserMode();
5484  InitReg(MISCREG_L2MERRSR_EL1)
5485  .unimplemented()
5486  .warnNotFail()
5487  .allPrivileges().exceptUserMode();
5488  InitReg(MISCREG_CBAR_EL1)
5489  .allPrivileges().exceptUserMode().writes(0);
5490  InitReg(MISCREG_CONTEXTIDR_EL2)
5491  .mon().hyp();
5492 
5493  // GICv3 AArch64
5494  InitReg(MISCREG_ICC_PMR_EL1)
5495  .res0(0xffffff00) // [31:8]
5496  .allPrivileges().exceptUserMode()
5497  .mapsTo(MISCREG_ICC_PMR);
5498  InitReg(MISCREG_ICC_IAR0_EL1)
5499  .allPrivileges().exceptUserMode().writes(0)
5500  .mapsTo(MISCREG_ICC_IAR0);
5501  InitReg(MISCREG_ICC_EOIR0_EL1)
5502  .allPrivileges().exceptUserMode().reads(0)
5503  .mapsTo(MISCREG_ICC_EOIR0);
5504  InitReg(MISCREG_ICC_HPPIR0_EL1)
5505  .allPrivileges().exceptUserMode().writes(0)
5506  .mapsTo(MISCREG_ICC_HPPIR0);
5507  InitReg(MISCREG_ICC_BPR0_EL1)
5508  .res0(0xfffffff8) // [31:3]
5509  .allPrivileges().exceptUserMode()
5510  .mapsTo(MISCREG_ICC_BPR0);
5511  InitReg(MISCREG_ICC_AP0R0_EL1)
5512  .allPrivileges().exceptUserMode()
5513  .mapsTo(MISCREG_ICC_AP0R0);
5514  InitReg(MISCREG_ICC_AP0R1_EL1)
5515  .allPrivileges().exceptUserMode()
5516  .mapsTo(MISCREG_ICC_AP0R1);
5517  InitReg(MISCREG_ICC_AP0R2_EL1)
5518  .allPrivileges().exceptUserMode()
5519  .mapsTo(MISCREG_ICC_AP0R2);
5520  InitReg(MISCREG_ICC_AP0R3_EL1)
5521  .allPrivileges().exceptUserMode()
5522  .mapsTo(MISCREG_ICC_AP0R3);
5523  InitReg(MISCREG_ICC_AP1R0_EL1)
5524  .banked64()
5525  .mapsTo(MISCREG_ICC_AP1R0);
5526  InitReg(MISCREG_ICC_AP1R0_EL1_NS)
5527  .bankedChild()
5528  .allPrivileges().exceptUserMode()
5529  .mapsTo(MISCREG_ICC_AP1R0_NS);
5530  InitReg(MISCREG_ICC_AP1R0_EL1_S)
5531  .bankedChild()
5532  .allPrivileges().exceptUserMode()
5533  .mapsTo(MISCREG_ICC_AP1R0_S);
5534  InitReg(MISCREG_ICC_AP1R1_EL1)
5535  .banked64()
5536  .mapsTo(MISCREG_ICC_AP1R1);
5537  InitReg(MISCREG_ICC_AP1R1_EL1_NS)
5538  .bankedChild()
5539  .allPrivileges().exceptUserMode()
5540  .mapsTo(MISCREG_ICC_AP1R1_NS);
5541  InitReg(MISCREG_ICC_AP1R1_EL1_S)
5542  .bankedChild()
5543  .allPrivileges().exceptUserMode()
5544  .mapsTo(MISCREG_ICC_AP1R1_S);
5545  InitReg(MISCREG_ICC_AP1R2_EL1)
5546  .banked64()
5547  .mapsTo(MISCREG_ICC_AP1R2);
5548  InitReg(MISCREG_ICC_AP1R2_EL1_NS)
5549  .bankedChild()
5550  .allPrivileges().exceptUserMode()
5551  .mapsTo(MISCREG_ICC_AP1R2_NS);
5552  InitReg(MISCREG_ICC_AP1R2_EL1_S)
5553  .bankedChild()
5554  .allPrivileges().exceptUserMode()
5555  .mapsTo(MISCREG_ICC_AP1R2_S);
5556  InitReg(MISCREG_ICC_AP1R3_EL1)
5557  .banked64()
5558  .mapsTo(MISCREG_ICC_AP1R3);
5559  InitReg(MISCREG_ICC_AP1R3_EL1_NS)
5560  .bankedChild()
5561  .allPrivileges().exceptUserMode()
5562  .mapsTo(MISCREG_ICC_AP1R3_NS);
5563  InitReg(MISCREG_ICC_AP1R3_EL1_S)
5564  .bankedChild()
5565  .allPrivileges().exceptUserMode()
5566  .mapsTo(MISCREG_ICC_AP1R3_S);
5567  InitReg(MISCREG_ICC_DIR_EL1)
5568  .res0(0xFF000000) // [31:24]
5569  .allPrivileges().exceptUserMode().reads(0)
5570  .mapsTo(MISCREG_ICC_DIR);
5571  InitReg(MISCREG_ICC_RPR_EL1)
5572  .allPrivileges().exceptUserMode().writes(0)
5573  .mapsTo(MISCREG_ICC_RPR);
5574  InitReg(MISCREG_ICC_SGI1R_EL1)
5575  .allPrivileges().exceptUserMode().reads(0)
5576  .mapsTo(MISCREG_ICC_SGI1R);
5577  InitReg(MISCREG_ICC_ASGI1R_EL1)
5578  .allPrivileges().exceptUserMode().reads(0)
5579  .mapsTo(MISCREG_ICC_ASGI1R);
5580  InitReg(MISCREG_ICC_SGI0R_EL1)
5581  .allPrivileges().exceptUserMode().reads(0)
5582  .mapsTo(MISCREG_ICC_SGI0R);
5583  InitReg(MISCREG_ICC_IAR1_EL1)
5584  .allPrivileges().exceptUserMode().writes(0)
5585  .mapsTo(MISCREG_ICC_IAR1);
5586  InitReg(MISCREG_ICC_EOIR1_EL1)
5587  .res0(0xFF000000) // [31:24]
5588  .allPrivileges().exceptUserMode().reads(0)
5589  .mapsTo(MISCREG_ICC_EOIR1);
5590  InitReg(MISCREG_ICC_HPPIR1_EL1)
5591  .allPrivileges().exceptUserMode().writes(0)
5592  .mapsTo(MISCREG_ICC_HPPIR1);
5593  InitReg(MISCREG_ICC_BPR1_EL1)
5594  .banked64()
5595  .mapsTo(MISCREG_ICC_BPR1);
5596  InitReg(MISCREG_ICC_BPR1_EL1_NS)
5597  .bankedChild()
5598  .res0(0xfffffff8) // [31:3]
5599  .allPrivileges().exceptUserMode()
5600  .mapsTo(MISCREG_ICC_BPR1_NS);
5601  InitReg(MISCREG_ICC_BPR1_EL1_S)
5602  .bankedChild()
5603  .res0(0xfffffff8) // [31:3]
5604  .secure().exceptUserMode()
5605  .mapsTo(MISCREG_ICC_BPR1_S);
5606  InitReg(MISCREG_ICC_CTLR_EL1)
5607  .banked64()
5608  .mapsTo(MISCREG_ICC_CTLR);
5609  InitReg(MISCREG_ICC_CTLR_EL1_NS)
5610  .bankedChild()
5611  .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
5612  .allPrivileges().exceptUserMode()
5613  .mapsTo(MISCREG_ICC_CTLR_NS);
5614  InitReg(MISCREG_ICC_CTLR_EL1_S)
5615  .bankedChild()
5616  .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
5617  .secure().exceptUserMode()
5618  .mapsTo(MISCREG_ICC_CTLR_S);
5619  InitReg(MISCREG_ICC_SRE_EL1)
5620  .banked()
5621  .mapsTo(MISCREG_ICC_SRE);
5622  InitReg(MISCREG_ICC_SRE_EL1_NS)
5623  .bankedChild()
5624  .res0(0xFFFFFFF8) // [31:3]
5625  .allPrivileges().exceptUserMode()
5626  .mapsTo(MISCREG_ICC_SRE_NS);
5627  InitReg(MISCREG_ICC_SRE_EL1_S)
5628  .bankedChild()
5629  .res0(0xFFFFFFF8) // [31:3]
5630  .secure().exceptUserMode()
5631  .mapsTo(MISCREG_ICC_SRE_S);
5632  InitReg(MISCREG_ICC_IGRPEN0_EL1)
5633  .res0(0xFFFFFFFE) // [31:1]
5634  .allPrivileges().exceptUserMode()
5635  .mapsTo(MISCREG_ICC_IGRPEN0);
5636  InitReg(MISCREG_ICC_IGRPEN1_EL1)
5637  .banked64()
5638  .mapsTo(MISCREG_ICC_IGRPEN1);
5639  InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
5640  .bankedChild()
5641  .res0(0xFFFFFFFE) // [31:1]
5642  .allPrivileges().exceptUserMode()
5643  .mapsTo(MISCREG_ICC_IGRPEN1_NS);
5644  InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
5645  .bankedChild()
5646  .res0(0xFFFFFFFE) // [31:1]
5647  .secure().exceptUserMode()
5648  .mapsTo(MISCREG_ICC_IGRPEN1_S);
5649  InitReg(MISCREG_ICC_SRE_EL2)
5650  .hyp().mon()
5651  .mapsTo(MISCREG_ICC_HSRE);
5652  InitReg(MISCREG_ICC_CTLR_EL3)
5653  .allPrivileges().exceptUserMode()
5654  .mapsTo(MISCREG_ICC_MCTLR);
5655  InitReg(MISCREG_ICC_SRE_EL3)
5656  .allPrivileges().exceptUserMode()
5657  .mapsTo(MISCREG_ICC_MSRE);
5658  InitReg(MISCREG_ICC_IGRPEN1_EL3)
5659  .allPrivileges().exceptUserMode()
5660  .mapsTo(MISCREG_ICC_MGRPEN1);
5661 
5662  InitReg(MISCREG_ICH_AP0R0_EL2)
5663  .hyp().mon()
5664  .mapsTo(MISCREG_ICH_AP0R0);
5665  InitReg(MISCREG_ICH_AP0R1_EL2)
5666  .hyp().mon()
5667  .unimplemented()
5668  .mapsTo(MISCREG_ICH_AP0R1);
5669  InitReg(MISCREG_ICH_AP0R2_EL2)
5670  .hyp().mon()
5671  .unimplemented()
5672  .mapsTo(MISCREG_ICH_AP0R2);
5673  InitReg(MISCREG_ICH_AP0R3_EL2)
5674  .hyp().mon()
5675  .unimplemented()
5676  .mapsTo(MISCREG_ICH_AP0R3);
5677  InitReg(MISCREG_ICH_AP1R0_EL2)
5678  .hyp().mon()
5679  .mapsTo(MISCREG_ICH_AP1R0);
5680  InitReg(MISCREG_ICH_AP1R1_EL2)
5681  .hyp().mon()
5682  .unimplemented()
5683  .mapsTo(MISCREG_ICH_AP1R1);
5684  InitReg(MISCREG_ICH_AP1R2_EL2)
5685  .hyp().mon()
5686  .unimplemented()
5687  .mapsTo(MISCREG_ICH_AP1R2);
5688  InitReg(MISCREG_ICH_AP1R3_EL2)
5689  .hyp().mon()
5690  .unimplemented()
5691  .mapsTo(MISCREG_ICH_AP1R3);
5692  InitReg(MISCREG_ICH_HCR_EL2)
5693  .hyp().mon()
5694  .mapsTo(MISCREG_ICH_HCR);
5695  InitReg(MISCREG_ICH_VTR_EL2)
5696  .hyp().mon().writes(0)
5697  .mapsTo(MISCREG_ICH_VTR);
5698  InitReg(MISCREG_ICH_MISR_EL2)
5699  .hyp().mon().writes(0)
5700  .mapsTo(MISCREG_ICH_MISR);
5701  InitReg(MISCREG_ICH_EISR_EL2)
5702  .hyp().mon().writes(0)
5703  .mapsTo(MISCREG_ICH_EISR);
5704  InitReg(MISCREG_ICH_ELRSR_EL2)
5705  .hyp().mon().writes(0)
5706  .mapsTo(MISCREG_ICH_ELRSR);
5707  InitReg(MISCREG_ICH_VMCR_EL2)
5708  .hyp().mon()
5709  .mapsTo(MISCREG_ICH_VMCR);
5710  InitReg(MISCREG_ICH_LR0_EL2)
5711  .hyp().mon()
5712  .allPrivileges().exceptUserMode();
5713  InitReg(MISCREG_ICH_LR1_EL2)
5714  .hyp().mon()
5715  .allPrivileges().exceptUserMode();
5716  InitReg(MISCREG_ICH_LR2_EL2)
5717  .hyp().mon()
5718  .allPrivileges().exceptUserMode();
5719  InitReg(MISCREG_ICH_LR3_EL2)
5720  .hyp().mon()
5721  .allPrivileges().exceptUserMode();
5722  InitReg(MISCREG_ICH_LR4_EL2)
5723  .hyp().mon()
5724  .allPrivileges().exceptUserMode();
5725  InitReg(MISCREG_ICH_LR5_EL2)
5726  .hyp().mon()
5727  .allPrivileges().exceptUserMode();
5728  InitReg(MISCREG_ICH_LR6_EL2)
5729  .hyp().mon()
5730  .allPrivileges().exceptUserMode();
5731  InitReg(MISCREG_ICH_LR7_EL2)
5732  .hyp().mon()
5733  .allPrivileges().exceptUserMode();
5734  InitReg(MISCREG_ICH_LR8_EL2)
5735  .hyp().mon()
5736  .allPrivileges().exceptUserMode();
5737  InitReg(MISCREG_ICH_LR9_EL2)
5738  .hyp().mon()
5739  .allPrivileges().exceptUserMode();
5740  InitReg(MISCREG_ICH_LR10_EL2)
5741  .hyp().mon()
5742  .allPrivileges().exceptUserMode();
5743  InitReg(MISCREG_ICH_LR11_EL2)
5744  .hyp().mon()
5745  .allPrivileges().exceptUserMode();
5746  InitReg(MISCREG_ICH_LR12_EL2)
5747  .hyp().mon()
5748  .allPrivileges().exceptUserMode();
5749  InitReg(MISCREG_ICH_LR13_EL2)
5750  .hyp().mon()
5751  .allPrivileges().exceptUserMode();
5752  InitReg(MISCREG_ICH_LR14_EL2)
5753  .hyp().mon()
5754  .allPrivileges().exceptUserMode();
5755  InitReg(MISCREG_ICH_LR15_EL2)
5756  .hyp().mon()
5757  .allPrivileges().exceptUserMode();
5758 
5759  // GICv3 AArch32
5760  InitReg(MISCREG_ICC_AP0R0)
5761  .allPrivileges().exceptUserMode();
5762  InitReg(MISCREG_ICC_AP0R1)
5763  .allPrivileges().exceptUserMode();
5764  InitReg(MISCREG_ICC_AP0R2)
5765  .allPrivileges().exceptUserMode();
5766  InitReg(MISCREG_ICC_AP0R3)
5767  .allPrivileges().exceptUserMode();
5768  InitReg(MISCREG_ICC_AP1R0)
5769  .allPrivileges().exceptUserMode();
5770  InitReg(MISCREG_ICC_AP1R0_NS)
5771  .allPrivileges().exceptUserMode();
5772  InitReg(MISCREG_ICC_AP1R0_S)
5773  .allPrivileges().exceptUserMode();
5774  InitReg(MISCREG_ICC_AP1R1)
5775  .allPrivileges().exceptUserMode();
5776  InitReg(MISCREG_ICC_AP1R1_NS)
5777  .allPrivileges().exceptUserMode();
5778  InitReg(MISCREG_ICC_AP1R1_S)
5779  .allPrivileges().exceptUserMode();
5780  InitReg(MISCREG_ICC_AP1R2)
5781  .allPrivileges().exceptUserMode();
5782  InitReg(MISCREG_ICC_AP1R2_NS)
5783  .allPrivileges().exceptUserMode();
5784  InitReg(MISCREG_ICC_AP1R2_S)
5785  .allPrivileges().exceptUserMode();
5786  InitReg(MISCREG_ICC_AP1R3)
5787  .allPrivileges().exceptUserMode();
5788  InitReg(MISCREG_ICC_AP1R3_NS)
5789  .allPrivileges().exceptUserMode();
5790  InitReg(MISCREG_ICC_AP1R3_S)
5791  .allPrivileges().exceptUserMode();
5792  InitReg(MISCREG_ICC_ASGI1R)
5793  .allPrivileges().exceptUserMode().reads(0);
5794  InitReg(MISCREG_ICC_BPR0)
5795  .allPrivileges().exceptUserMode();
5796  InitReg(MISCREG_ICC_BPR1)
5797  .allPrivileges().exceptUserMode();
5798  InitReg(MISCREG_ICC_BPR1_NS)
5799  .allPrivileges().exceptUserMode();
5800  InitReg(MISCREG_ICC_BPR1_S)
5801  .allPrivileges().exceptUserMode();
5802  InitReg(MISCREG_ICC_CTLR)
5803  .allPrivileges().exceptUserMode();
5804  InitReg(MISCREG_ICC_CTLR_NS)
5805  .allPrivileges().exceptUserMode();
5806  InitReg(MISCREG_ICC_CTLR_S)
5807  .allPrivileges().exceptUserMode();
5808  InitReg(MISCREG_ICC_DIR)
5809  .allPrivileges().exceptUserMode().reads(0);
5810  InitReg(MISCREG_ICC_EOIR0)
5811  .allPrivileges().exceptUserMode().reads(0);
5812  InitReg(MISCREG_ICC_EOIR1)
5813  .allPrivileges().exceptUserMode().reads(0);
5814  InitReg(MISCREG_ICC_HPPIR0)
5815  .allPrivileges().exceptUserMode().writes(0);
5816  InitReg(MISCREG_ICC_HPPIR1)
5817  .allPrivileges().exceptUserMode().writes(0);
5818  InitReg(MISCREG_ICC_HSRE)
5819  .allPrivileges().exceptUserMode();
5820  InitReg(MISCREG_ICC_IAR0)
5821  .allPrivileges().exceptUserMode().writes(0);
5822  InitReg(MISCREG_ICC_IAR1)
5823  .allPrivileges().exceptUserMode().writes(0);
5824  InitReg(MISCREG_ICC_IGRPEN0)
5825  .allPrivileges().exceptUserMode();
5826  InitReg(MISCREG_ICC_IGRPEN1)
5827  .allPrivileges().exceptUserMode();
5828  InitReg(MISCREG_ICC_IGRPEN1_NS)
5829  .allPrivileges().exceptUserMode();
5830  InitReg(MISCREG_ICC_IGRPEN1_S)
5831  .allPrivileges().exceptUserMode();
5832  InitReg(MISCREG_ICC_MCTLR)
5833  .allPrivileges().exceptUserMode();
5834  InitReg(MISCREG_ICC_MGRPEN1)
5835  .allPrivileges().exceptUserMode();
5836  InitReg(MISCREG_ICC_MSRE)
5837  .allPrivileges().exceptUserMode();
5838  InitReg(MISCREG_ICC_PMR)
5839  .allPrivileges().exceptUserMode();
5840  InitReg(MISCREG_ICC_RPR)
5841  .allPrivileges().exceptUserMode().writes(0);
5842  InitReg(MISCREG_ICC_SGI0R)
5843  .allPrivileges().exceptUserMode().reads(0);
5844  InitReg(MISCREG_ICC_SGI1R)
5845  .allPrivileges().exceptUserMode().reads(0);
5846  InitReg(MISCREG_ICC_SRE)
5847  .allPrivileges().exceptUserMode();
5848  InitReg(MISCREG_ICC_SRE_NS)
5849  .allPrivileges().exceptUserMode();
5850  InitReg(MISCREG_ICC_SRE_S)
5851  .allPrivileges().exceptUserMode();
5852 
5853  InitReg(MISCREG_ICH_AP0R0)
5854  .hyp().mon();
5855  InitReg(MISCREG_ICH_AP0R1)
5856  .hyp().mon();
5857  InitReg(MISCREG_ICH_AP0R2)
5858  .hyp().mon();
5859  InitReg(MISCREG_ICH_AP0R3)
5860  .hyp().mon();
5861  InitReg(MISCREG_ICH_AP1R0)
5862  .hyp().mon();
5863  InitReg(MISCREG_ICH_AP1R1)
5864  .hyp().mon();
5865  InitReg(MISCREG_ICH_AP1R2)
5866  .hyp().mon();
5867  InitReg(MISCREG_ICH_AP1R3)
5868  .hyp().mon();
5869  InitReg(MISCREG_ICH_HCR)
5870  .hyp().mon();
5871  InitReg(MISCREG_ICH_VTR)
5872  .hyp().mon().writes(0);
5873  InitReg(MISCREG_ICH_MISR)
5874  .hyp().mon().writes(0);
5875  InitReg(MISCREG_ICH_EISR)
5876  .hyp().mon().writes(0);
5877  InitReg(MISCREG_ICH_ELRSR)
5878  .hyp().mon().writes(0);
5879  InitReg(MISCREG_ICH_VMCR)
5880  .hyp().mon();
5881  InitReg(MISCREG_ICH_LR0)
5882  .hyp().mon();
5883  InitReg(MISCREG_ICH_LR1)
5884  .hyp().mon();
5885  InitReg(MISCREG_ICH_LR2)
5886  .hyp().mon();
5887  InitReg(MISCREG_ICH_LR3)
5888  .hyp().mon();
5889  InitReg(MISCREG_ICH_LR4)
5890  .hyp().mon();
5891  InitReg(MISCREG_ICH_LR5)
5892  .hyp().mon();
5893  InitReg(MISCREG_ICH_LR6)
5894  .hyp().mon();
5895  InitReg(MISCREG_ICH_LR7)
5896  .hyp().mon();
5897  InitReg(MISCREG_ICH_LR8)
5898  .hyp().mon();
5899  InitReg(MISCREG_ICH_LR9)
5900  .hyp().mon();
5901  InitReg(MISCREG_ICH_LR10)
5902  .hyp().mon();
5903  InitReg(MISCREG_ICH_LR11)
5904  .hyp().mon();
5905  InitReg(MISCREG_ICH_LR12)
5906  .hyp().mon();
5907  InitReg(MISCREG_ICH_LR13)
5908  .hyp().mon();
5909  InitReg(MISCREG_ICH_LR14)
5910  .hyp().mon();
5911  InitReg(MISCREG_ICH_LR15)
5912  .hyp().mon();
5913  InitReg(MISCREG_ICH_LRC0)
5914  .mapsTo(MISCREG_ICH_LR0)
5915  .hyp().mon();
5916  InitReg(MISCREG_ICH_LRC1)
5917  .mapsTo(MISCREG_ICH_LR1)
5918  .hyp().mon();
5919  InitReg(MISCREG_ICH_LRC2)
5920  .mapsTo(MISCREG_ICH_LR2)
5921  .hyp().mon();
5922  InitReg(MISCREG_ICH_LRC3)
5923  .mapsTo(MISCREG_ICH_LR3)
5924  .hyp().mon();
5925  InitReg(MISCREG_ICH_LRC4)
5926  .mapsTo(MISCREG_ICH_LR4)
5927  .hyp().mon();
5928  InitReg(MISCREG_ICH_LRC5)
5929  .mapsTo(MISCREG_ICH_LR5)
5930  .hyp().mon();
5931  InitReg(MISCREG_ICH_LRC6)
5932  .mapsTo(MISCREG_ICH_LR6)
5933  .hyp().mon();
5934  InitReg(MISCREG_ICH_LRC7)
5935  .mapsTo(MISCREG_ICH_LR7)
5936  .hyp().mon();
5937  InitReg(MISCREG_ICH_LRC8)
5938  .mapsTo(MISCREG_ICH_LR8)
5939  .hyp().mon();
5940  InitReg(MISCREG_ICH_LRC9)
5941  .mapsTo(MISCREG_ICH_LR9)
5942  .hyp().mon();
5943  InitReg(MISCREG_ICH_LRC10)
5944  .mapsTo(MISCREG_ICH_LR10)
5945  .hyp().mon();
5946  InitReg(MISCREG_ICH_LRC11)
5947  .mapsTo(MISCREG_ICH_LR11)
5948  .hyp().mon();
5949  InitReg(MISCREG_ICH_LRC12)
5950  .mapsTo(MISCREG_ICH_LR12)
5951  .hyp().mon();
5952  InitReg(MISCREG_ICH_LRC13)
5953  .mapsTo(MISCREG_ICH_LR13)
5954  .hyp().mon();
5955  InitReg(MISCREG_ICH_LRC14)
5956  .mapsTo(MISCREG_ICH_LR14)
5957  .hyp().mon();
5958  InitReg(MISCREG_ICH_LRC15)
5959  .mapsTo(MISCREG_ICH_LR15)
5960  .hyp().mon();
5961 
5962  // SVE
5963  InitReg(MISCREG_ID_AA64ZFR0_EL1)
5964  .allPrivileges().exceptUserMode().writes(0);
5965  InitReg(MISCREG_ZCR_EL3)
5966  .mon();
5967  InitReg(MISCREG_ZCR_EL2)
5968  .hyp().mon();
5969  InitReg(MISCREG_ZCR_EL12)
5970  .allPrivileges().exceptUserMode()
5971  .mapsTo(MISCREG_ZCR_EL1);
5972  InitReg(MISCREG_ZCR_EL1)
5973  .allPrivileges().exceptUserMode();
5974 
5975  // Dummy registers
5976  InitReg(MISCREG_NOP)
5977  .allPrivileges();
5978  InitReg(MISCREG_RAZ)
5979  .allPrivileges().exceptUserMode().writes(0);
5980  InitReg(MISCREG_CP14_UNIMPL)
5981  .unimplemented()
5982  .warnNotFail();
5983  InitReg(MISCREG_CP15_UNIMPL)
5984  .unimplemented()
5985  .warnNotFail();
5986  InitReg(MISCREG_UNKNOWN);
5987  InitReg(MISCREG_IMPDEF_UNIMPL)
5988  .unimplemented()
5989  .warnNotFail(impdefAsNop);
5990 
5991  // RAS extension (unimplemented)
5992  InitReg(MISCREG_ERRIDR_EL1)
5993  .unimplemented()
5994  .warnNotFail();
5995  InitReg(MISCREG_ERRSELR_EL1)
5996  .unimplemented()
5997  .warnNotFail();
5998  InitReg(MISCREG_ERXFR_EL1)
5999  .unimplemented()
6000  .warnNotFail();
6001  InitReg(MISCREG_ERXCTLR_EL1)
6002  .unimplemented()
6003  .warnNotFail();
6004  InitReg(MISCREG_ERXSTATUS_EL1)
6005  .unimplemented()
6006  .warnNotFail();
6007  InitReg(MISCREG_ERXADDR_EL1)
6008  .unimplemented()
6009  .warnNotFail();
6010  InitReg(MISCREG_ERXMISC0_EL1)
6011  .unimplemented()
6012  .warnNotFail();
6013  InitReg(MISCREG_ERXMISC1_EL1)
6014  .unimplemented()
6015  .warnNotFail();
6016  InitReg(MISCREG_DISR_EL1)
6017  .unimplemented()
6018  .warnNotFail();
6019  InitReg(MISCREG_VSESR_EL2)
6020  .unimplemented()
6021  .warnNotFail();
6022  InitReg(MISCREG_VDISR_EL2)
6023  .unimplemented()
6024  .warnNotFail();
6025 
6026  // Register mappings for some unimplemented registers:
6027  // ESR_EL1 -> DFSR
6028  // RMR_EL1 -> RMR
6029  // RMR_EL2 -> HRMR
6030  // DBGDTR_EL0 -> DBGDTR{R or T}Xint
6031  // DBGDTRRX_EL0 -> DBGDTRRXint
6032  // DBGDTRTX_EL0 -> DBGDTRRXint
6033  // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
6034 
6035  completed = true;
6036 }
6037 
6038 } // namespace ArmISA
6039 } // namespace gem5
gem5::ArmISA::MISCREG_USR_NS_RD
@ MISCREG_USR_NS_RD
Definition: misc.hh:1121
gem5::ArmISA::MISCREG_APDAKeyLo_EL1
@ MISCREG_APDAKeyLo_EL1
Definition: misc.hh:826
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:575
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: misc.hh:616
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: misc.hh:316
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: misc.hh:283
gem5::ArmISA::MISCREG_PMSWINC
@ MISCREG_PMSWINC
Definition: misc.hh:355
gem5::ArmISA::MISCREG_CSSELR_NS
@ MISCREG_CSSELR_NS
Definition: misc.hh:231
gem5::ArmISA::MISCREG_DL1DATA1
@ MISCREG_DL1DATA1
Definition: misc.hh:440
gem5::ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition: misc.hh:1129
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:649
gem5::ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: misc.hh:165
gem5::ArmISA::MISCREG_HAMAIR0
@ MISCREG_HAMAIR0
Definition: misc.hh:389
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: misc.hh:245
gem5::ArmISA::MISCREG_IC_IALLUIS
@ MISCREG_IC_IALLUIS
Definition: misc.hh:654
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::MISCREG_IL1DATA3_EL1
@ MISCREG_IL1DATA3_EL1
Definition: misc.hh:805
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:219
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:588
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS
@ MISCREG_ICC_CTLR_EL1_NS
Definition: misc.hh:870
gem5::ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition: misc.hh:1122
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:483
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: misc.hh:361
gem5::ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition: misc.hh:498
gem5::ArmISA::MISCREG_ICC_CTLR_EL3
@ MISCREG_ICC_CTLR_EL3
Definition: misc.hh:880
gem5::ArmISA::MISCREG_PMCEID1
@ MISCREG_PMCEID1
Definition: misc.hh:358
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:325
gem5::ArmISA::MISCREG_ICH_AP0R2_EL2
@ MISCREG_ICH_AP0R2_EL2
Definition: misc.hh:887
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: misc.hh:448
gem5::ArmISA::MISCREG_DL1DATA3_EL1
@ MISCREG_DL1DATA3_EL1
Definition: misc.hh:809
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:351
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: misc.hh:427
gem5::ArmISA::MISCREG_ICH_LR13
@ MISCREG_ICH_LR13
Definition: misc.hh:1033
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS
@ MISCREG_ICC_AP1R0_EL1_NS
Definition: misc.hh:847
gem5::ArmISA::MISCREG_ICC_AP0R3_EL1
@ MISCREG_ICC_AP0R3_EL1
Definition: misc.hh:845
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:230
gem5::ArmISA::MISCREG_MDDTRRX_EL0
@ MISCREG_MDDTRRX_EL0
Definition: misc.hh:525
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: misc.hh:95
gem5::ArmISA::MISCREG_ICC_HSRE
@ MISCREG_ICC_HSRE
Definition: misc.hh:988
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: misc.hh:312
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:603
gem5::ArmISA::MISCREG_DBGPRCR_EL1
@ MISCREG_DBGPRCR_EL1
Definition: misc.hh:531
gem5::ArmISA::MISCREG_DBGBXVR9
@ MISCREG_DBGBXVR9
Definition: misc.hh:180
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:728
gem5::ArmISA::MISCREG_AMAIR0_NS
@ MISCREG_AMAIR0_NS
Definition: misc.hh:382
gem5::ArmISA::MISCREG_DBGWVR5
@ MISCREG_DBGWVR5
Definition: misc.hh:143
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition: misc.hh:742
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:674
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition: misc.hh:722
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monE2H
chain monE2H(bool v=true) const
Definition: isa.hh:339
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition: misc.hh:721
gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_TVAL_EL2
Definition: misc.hh:786
gem5::ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: misc.hh:131
gem5::ArmISA::MISCREG_ICC_BPR0_EL1
@ MISCREG_ICC_BPR0_EL1
Definition: misc.hh:841
gem5::ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition: misc.hh:262
gem5::ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition: misc.hh:729
gem5::ArmISA::MISCREG_PRI_S_RD
@ MISCREG_PRI_S_RD
Definition: misc.hh:1128
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::MISCREG_PMOVSCLR_EL0
@ MISCREG_PMOVSCLR_EL0
Definition: misc.hh:715
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:333
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:252
gem5::ArmISA::MISCREG_ICH_LR13_EL2
@ MISCREG_ICH_LR13_EL2
Definition: misc.hh:912
gem5::ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition: misc.hh:354
gem5::ArmISA::MISCREG_DBGWVR15
@ MISCREG_DBGWVR15
Definition: misc.hh:153
gem5::ArmISA::MISCREG_ICC_IAR0_EL1
@ MISCREG_ICC_IAR0_EL1
Definition: misc.hh:838
gem5::ArmISA::MISCREG_ICH_LRC6
@ MISCREG_ICH_LRC6
Definition: misc.hh:1042
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:596
gem5::ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: misc.hh:367
gem5::ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:704
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: misc.hh:609
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition: misc.hh:491
warn
#define warn(...)
Definition: logging.hh:245
gem5::ArmISA::MISCREG_ICC_EOIR1
@ MISCREG_ICC_EOIR1
Definition: misc.hh:985
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S
@ MISCREG_ICC_CTLR_EL1_S
Definition: misc.hh:871
gem5::ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition: misc.hh:664
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:225
gem5::ArmISA::MISCREG_CONTEXTIDR_S
@ MISCREG_CONTEXTIDR_S
Definition: misc.hh:401
gem5::ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: misc.hh:384
gem5::ArmISA::MISCREG_CNTP_CTL_EL02
@ MISCREG_CNTP_CTL_EL02
Definition: misc.hh:762
gem5::ArmISA::MISCREG_DBGDTRRXext
@ MISCREG_DBGDTRRXext
Definition: misc.hh:102
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition: misc.hh:669
gem5::ArmISA::canWriteAArch64SysReg
bool canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: misc.cc:1418
gem5::ArmISA::MISCREG_DBGWVR1
@ MISCREG_DBGWVR1
Definition: misc.hh:139
gem5::ArmISA::MISCREG_TPIDRURO_NS
@ MISCREG_TPIDRURO_NS
Definition: misc.hh:406
gem5::ArmISA::MISCREG_ICC_AP1R3
@ MISCREG_ICC_AP1R3
Definition: misc.hh:972
gem5::ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition: misc.hh:353
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_NS
@ MISCREG_ICC_AP1R1_EL1_NS
Definition: misc.hh:850
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:681
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:591
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:520
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: misc.hh:346
gem5::ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: misc.hh:381
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: misc.hh:677
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: misc.hh:297
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:801
gem5::ArmISA::MISCREG_ICH_AP0R3_EL2
@ MISCREG_ICH_AP0R3_EL2
Definition: misc.hh:888
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::MISCREG_CONTEXTIDR_NS
@ MISCREG_CONTEXTIDR_NS
Definition: misc.hh:400
gem5::ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition: misc.hh:590
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:770
gem5::ArmISA::MISCREG_DBGBVR15
@ MISCREG_DBGBVR15
Definition: misc.hh:121
gem5::ArmISA::MISCREG_IL1DATA0
@ MISCREG_IL1DATA0
Definition: misc.hh:435
gem5::ArmISA::MISCREG_ICC_BPR1_NS
@ MISCREG_ICC_BPR1_NS
Definition: misc.hh:978
gem5::ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition: misc.hh:641
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:205
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:509
gem5::ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: misc.hh:618
gem5::ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition: misc.hh:549
gem5::ArmISA::MISCREG_ICC_IGRPEN1_NS
@ MISCREG_ICC_IGRPEN1_NS
Definition: misc.hh:993
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: misc.hh:254
gem5::ArmISA::MISCREG_DBGBXVR10
@ MISCREG_DBGBXVR10
Definition: misc.hh:181
gem5::ArmISA::canWriteCoprocReg
std::tuple< bool, bool > canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to write coprocessor registers.
Definition: misc.cc:1255
gem5::ArmISA::MISCREG_PRRR_MAIR0_S
@ MISCREG_PRRR_MAIR0_S
Definition: misc.hh:86
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:701
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: misc.hh:415
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:675
gem5::ArmISA::MISCREG_CPUACTLR_EL1
@ MISCREG_CPUACTLR_EL1
Definition: misc.hh:812
gem5::ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: misc.hh:169
gem5::ArmISA::MISCREG_ICH_AP1R0_EL2
@ MISCREG_ICH_AP1R0_EL2
Definition: misc.hh:889
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition: misc.hh:577
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::warnNotFail
chain warnNotFail(bool v=true) const
Definition: isa.hh:181
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition: misc.hh:573
gem5::ArmISA::MISCREG_CP15DMB
@ MISCREG_CP15DMB
Definition: misc.hh:315
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: misc.hh:164
gem5::ArmISA::MISCREG_DBGBXVR11
@ MISCREG_DBGBXVR11
Definition: misc.hh:182
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: misc.hh:209
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:413
gem5::ArmISA::MISCREG_ICH_EISR
@ MISCREG_ICH_EISR
Definition: misc.hh:1017
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_PMINTENCLR_EL1
@ MISCREG_PMINTENCLR_EL1
Definition: misc.hh:711
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:399
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mutex
chain mutex(bool v=true) const
Definition: isa.hh:185
gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
Definition: misc.hh:779
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
Definition: misc.hh:785
gem5::ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition: misc.hh:552
gem5::ArmISA::MISCREG_DBGWVR9
@ MISCREG_DBGWVR9
Definition: misc.hh:147
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: misc.hh:307
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition: misc.hh:667
gem5::ArmISA::MISCREG_PRRR_MAIR0_NS
@ MISCREG_PRRR_MAIR0_NS
Definition: misc.hh:85
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:489
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:772
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: misc.hh:63
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:756
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:328
gem5::ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: misc.hh:71
gem5::ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition: misc.hh:650
gem5::ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: misc.hh:242
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:690
gem5::ArmISA::MISCREG_DBGBXVR1
@ MISCREG_DBGBXVR1
Definition: misc.hh:172
gem5::ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: misc.hh:236
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: misc.hh:233
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: misc.hh:162
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition: misc.hh:589
gem5::ArmISA::MISCREG_PMEVCNTR5_EL0
@ MISCREG_PMEVCNTR5_EL0
Definition: misc.hh:795
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: misc.hh:127
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:475
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::allPrivileges
chain allPrivileges(bool v=true) const
Definition: isa.hh:381
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:687
gem5::ArmISA::MISCREG_ICH_MISR_EL2
@ MISCREG_ICH_MISR_EL2
Definition: misc.hh:895
gem5::ArmISA::MISCREG_ICC_IAR1
@ MISCREG_ICC_IAR1
Definition: misc.hh:990
gem5::ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: misc.hh:163
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:338
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: misc.hh:73
gem5::ArmISA::MISCREG_CNTHCTL
@ MISCREG_CNTHCTL
Definition: misc.hh:429
gem5::ArmISA::MISCREG_TEEHBR32_EL1
@ MISCREG_TEEHBR32_EL1
Definition: misc.hh:536
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: misc.hh:310
gem5::ArmISA::MISCREG_DBGWVR10
@ MISCREG_DBGWVR10
Definition: misc.hh:148
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition: misc.hh:825
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: misc.hh:313
gem5::ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition: misc.hh:717
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: misc.hh:344
gem5::ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: misc.hh:347
gem5::ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition: misc.hh:666
gem5::ArmISA::MISCREG_ICH_LR6
@ MISCREG_ICH_LR6
Definition: misc.hh:1026
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_NS
@ MISCREG_ICC_AP1R3_EL1_NS
Definition: misc.hh:856
gem5::ArmISA::MISCREG_CNTP_CVAL_S
@ MISCREG_CNTP_CVAL_S
Definition: misc.hh:421
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: misc.hh:619
gem5::ArmISA::MISCREG_DL1DATA3
@ MISCREG_DL1DATA3
Definition: misc.hh:442
gem5::ArmISA::MISCREG_CNTKCTL
@ MISCREG_CNTKCTL
Definition: misc.hh:428
gem5::ArmISA::MISCREG_ACTLR_EL3
@ MISCREG_ACTLR_EL3
Definition: misc.hh:592
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition: misc.hh:1142
gem5::ArmISA::MISCREG_ACTLR_NS
@ MISCREG_ACTLR_NS
Definition: misc.hh:239
gem5::ArmISA::MISCREG_ICH_LRC2
@ MISCREG_ICH_LRC2
Definition: misc.hh:1038
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::MISCREG_AMAIR1_NS
@ MISCREG_AMAIR1_NS
Definition: misc.hh:385
gem5::ArmISA::MISCREG_ICC_EOIR0_EL1
@ MISCREG_ICC_EOIR0_EL1
Definition: misc.hh:839
gem5::ArmISA::MISCREG_DISR_EL1
@ MISCREG_DISR_EL1
Definition: misc.hh:1088
gem5::ArmISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:1331
gem5::ArmISA::MISCREG_ICH_AP0R1_EL2
@ MISCREG_ICH_AP0R1_EL2
Definition: misc.hh:886
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypWrite
chain hypWrite(bool v=true) const
Definition: isa.hh:313
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:518
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition: misc.hh:663
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: misc.hh:122
gem5::ArmISA::canReadAArch64SysReg
bool canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: misc.cc:1371
gem5::ArmISA::MISCREG_HAMAIR1
@ MISCREG_HAMAIR1
Definition: misc.hh:390
gem5::ArmISA::MISCREG_HYP_E2H_NS_RD
@ MISCREG_HYP_E2H_NS_RD
Definition: misc.hh:1136
gem5::ArmISA::MISCREG_BPIMVA
@ MISCREG_BPIMVA
Definition: misc.hh:301
gem5::ArmISA::unflattenResultMiscReg
int unflattenResultMiscReg[NUM_MISCREGS]
If the reg is a child reg of a banked set, then the parent is the last banked one in the list.
Definition: misc.cc:1346
gem5::ArmISA::MISCREG_SDER32_EL3
@ MISCREG_SDER32_EL3
Definition: misc.hh:594
gem5::ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition: misc.hh:556
gem5::ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition: misc.hh:504
gem5::ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition: misc.hh:1127
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: misc.hh:298
gem5::ArmISA::MISCREG_TPIDRURW_S
@ MISCREG_TPIDRURW_S
Definition: misc.hh:404
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition: misc.hh:493
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: misc.hh:345
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:691
gem5::ArmISA::MISCREG_DBGVCR
@ MISCREG_DBGVCR
Definition: misc.hh:101
gem5::ArmISA::MISCREG_ICH_LRC8
@ MISCREG_ICH_LRC8
Definition: misc.hh:1044
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:620
gem5::ArmISA::MISCREG_CNTP_TVAL
@ MISCREG_CNTP_TVAL
Definition: misc.hh:422
gem5::ArmISA::MISCREG_ICC_RPR_EL1
@ MISCREG_ICC_RPR_EL1
Definition: misc.hh:859
gem5::ArmISA::MISCREG_ICH_LR0
@ MISCREG_ICH_LR0
Definition: misc.hh:1020
gem5::ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition: misc.hh:828
gem5::ArmISA::MISCREG_MAIR1_NS
@ MISCREG_MAIR1_NS
Definition: misc.hh:379
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:599
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:740
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:260
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:696
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:702
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:643
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:337
gem5::ArmISA::MISCREG_ICC_SRE_EL3
@ MISCREG_ICC_SRE_EL3
Definition: misc.hh:881
gem5::ArmISA::MISCREG_TPIDRPRW_NS
@ MISCREG_TPIDRPRW_NS
Definition: misc.hh:409
gem5::ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition: misc.hh:546
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:201
gem5::ArmISA::MISCREG_MDRAR_EL1
@ MISCREG_MDRAR_EL1
Definition: misc.hh:527
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: misc.hh:303
gem5::ArmISA::MISCREG_ICH_LR5
@ MISCREG_ICH_LR5
Definition: misc.hh:1025
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:246
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::MISCREG_SPSR_FIQ_AA64
@ MISCREG_SPSR_FIQ_AA64
Definition: misc.hh:631
gem5::ArmISA::MISCREG_DBGBVR7
@ MISCREG_DBGBVR7
Definition: misc.hh:113
gem5::ArmISA::MISCREG_ICH_LR11_EL2
@ MISCREG_ICH_LR11_EL2
Definition: misc.hh:910
gem5::ArmISA::MISCREG_MAIR0_NS
@ MISCREG_MAIR0_NS
Definition: misc.hh:373
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:644
GEM5_FALLTHROUGH
#define GEM5_FALLTHROUGH
Definition: compiler.hh:61
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:662
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:515
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:695
gem5::ArmISA::MISCREG_HACTLR
@ MISCREG_HACTLR
Definition: misc.hh:247
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:516
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:321
gem5::ArmISA::MISCREG_ICC_AP1R2_NS
@ MISCREG_ICC_AP1R2_NS
Definition: misc.hh:970
gem5::ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition: misc.hh:503
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: misc.hh:529
gem5::ArmISA::MISCREG_L2MERRSR
@ MISCREG_L2MERRSR
Definition: misc.hh:450
gem5::ArmISA::MISCREG_DBGDTRRXint
@ MISCREG_DBGDTRRXint
Definition: misc.hh:99
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::res0
chain res0(uint64_t mask) const
Definition: isa.hh:154
gem5::ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition: misc.hh:832
gem5::ArmISA::MISCREG_CP14_UNIMPL
@ MISCREG_CP14_UNIMPL
Definition: misc.hh:1070
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:482
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: misc.hh:341
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:710
gem5::ArmISA::decodeAArch64SysReg
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition: misc.cc:1454
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:682
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:208
gem5::ArmISA::MISCREG_TPIDR_EL3
@ MISCREG_TPIDR_EL3
Definition: misc.hh:751
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:745
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:566
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition: misc.hh:459
gem5::ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition: misc.hh:860
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:329
gem5::ArmISA::MISCREG_IL1DATA0_EL1
@ MISCREG_IL1DATA0_EL1
Definition: misc.hh:802
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:610
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition: misc.hh:553
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:290
gem5::ArmISA::MISCREG_DBGBVR2
@ MISCREG_DBGBVR2
Definition: misc.hh:108
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: misc.hh:83
gem5::ArmISA::MISCREG_DFSR_S
@ MISCREG_DFSR_S
Definition: misc.hh:270
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:331
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureWrite
chain monNonSecureWrite(bool v=true) const
Definition: isa.hh:359
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition: misc.hh:554
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: misc.hh:158
gem5::ArmISA::MISCREG_AMAIR_EL3
@ MISCREG_AMAIR_EL3
Definition: misc.hh:733
gem5::ArmISA::MISCREG_TTBR0_NS
@ MISCREG_TTBR0_NS
Definition: misc.hh:255
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:223
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:487
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: misc.hh:350
gem5::ArmISA::MISCREG_ICH_LRC5
@ MISCREG_ICH_LRC5
Definition: misc.hh:1041
gem5::ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition: misc.hh:555
gem5::ArmISA::MISCREG_ICH_LR9_EL2
@ MISCREG_ICH_LR9_EL2
Definition: misc.hh:908
gem5::ArmISA::MISCREG_CNTP_TVAL_NS
@ MISCREG_CNTP_TVAL_NS
Definition: misc.hh:423
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:486
gem5::ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition: misc.hh:87
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:218
gem5::ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: misc.hh:167
gem5::ArmISA::MISCREG_MAIR_EL3
@ MISCREG_MAIR_EL3
Definition: misc.hh:732
gem5::ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition: misc.hh:84
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: misc.hh:66
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:187
gem5::ArmISA::MISCREG_ICC_IGRPEN1
@ MISCREG_ICC_IGRPEN1
Definition: misc.hh:992
gem5::ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition: misc.hh:501
gem5::ArmISA::MISCREG_ICH_LR2
@ MISCREG_ICH_LR2
Definition: misc.hh:1022
gem5::ArmISA::MISCREG_ICC_MGRPEN1
@ MISCREG_ICC_MGRPEN1
Definition: misc.hh:996
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: misc.hh:366
gem5::ArmISA::MISCREG_ICH_AP1R2
@ MISCREG_ICH_AP1R2
Definition: misc.hh:1012
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:726
gem5::ArmISA::MISCREG_ICH_LR1_EL2
@ MISCREG_ICH_LR1_EL2
Definition: misc.hh:900
gem5::ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition: misc.hh:363
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: misc.hh:318
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: misc.hh:370
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:688
gem5::ArmISA::MISCREG_PRRR_S
@ MISCREG_PRRR_S
Definition: misc.hh:371
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:221
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: misc.hh:309
gem5::ArmISA::MISCREG_CNTP_CTL_NS
@ MISCREG_CNTP_CTL_NS
Definition: misc.hh:417
gem5::ArmISA::MISCREG_DBGBVR6
@ MISCREG_DBGBVR6
Definition: misc.hh:112
gem5::ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition: misc.hh:615
gem5::ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition: misc.hh:716
gem5::ArmISA::MISCREG_ICC_PMR
@ MISCREG_ICC_PMR
Definition: misc.hh:998
gem5::ArmISA::MISCREG_DFSR_NS
@ MISCREG_DFSR_NS
Definition: misc.hh:269
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: misc.hh:914
gem5::ArmISA::MISCREG_DL1DATA0_EL1
@ MISCREG_DL1DATA0_EL1
Definition: misc.hh:806
gem5::ArmISA::MISCREG_NMRR_MAIR1_NS
@ MISCREG_NMRR_MAIR1_NS
Definition: misc.hh:88
gem5::ArmISA::ISA::havePAN
bool havePAN
Definition: isa.hh:100
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:679
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:106
gem5::ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition: misc.hh:720
gem5::ArmISA::MISCREG_BPIALLIS
@ MISCREG_BPIALLIS
Definition: misc.hh:293
gem5::ArmISA::MISCREG_DL1DATA2
@ MISCREG_DL1DATA2
Definition: misc.hh:441
gem5::ArmISA::MISCREG_ADFSR_NS
@ MISCREG_ADFSR_NS
Definition: misc.hh:275
gem5::ArmISA::MISCREG_CNTV_CVAL_EL02
@ MISCREG_CNTV_CVAL_EL02
Definition: misc.hh:766
gem5::ArmISA::MISCREG_DL1DATA2_EL1
@ MISCREG_DL1DATA2_EL1
Definition: misc.hh:808
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:564
gem5::ArmISA::MISCREG_ICC_EOIR0
@ MISCREG_ICC_EOIR0
Definition: misc.hh:984
gem5::ArmISA::MISCREG_ICH_LR3
@ MISCREG_ICH_LR3
Definition: misc.hh:1023
gem5::ArmISA::MISCREG_L2ACTLR_EL1
@ MISCREG_L2ACTLR_EL1
Definition: misc.hh:811
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:235
gem5::ArmISA::MISCREG_DBGBXVR15
@ MISCREG_DBGBXVR15
Definition: misc.hh:186
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition: misc.hh:1124
gem5::ArmISA::MISCREG_ICH_AP0R0
@ MISCREG_ICH_AP0R0
Definition: misc.hh:1006
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: misc.hh:655
gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: misc.hh:706
gem5::ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: misc.hh:959
gem5::ArmISA::MISCREG_ACTLR_S
@ MISCREG_ACTLR_S
Definition: misc.hh:240
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:755
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:754
gem5::ArmISA::MISCREG_MAIR1_S
@ MISCREG_MAIR1_S
Definition: misc.hh:380
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:511
gem5::ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: misc.hh:161
gem5::ArmISA::MISCREG_TPIDRRO_EL0
@ MISCREG_TPIDRRO_EL0
Definition: misc.hh:749
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: misc.hh:416
gem5::ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition: misc.hh:473
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:703
gem5::ArmISA::MISCREG_ICH_LR12_EL2
@ MISCREG_ICH_LR12_EL2
Definition: misc.hh:911
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S
@ MISCREG_ICC_AP1R0_EL1_S
Definition: misc.hh:848
gem5::ArmISA::MISCREG_DBGBVR3
@ MISCREG_DBGBVR3
Definition: misc.hh:109
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:199
gem5::ArmISA::MISCREG_CNTP_TVAL_EL02
@ MISCREG_CNTP_TVAL_EL02
Definition: misc.hh:764
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:216
gem5::ArmISA::MISCREG_ICH_LR12
@ MISCREG_ICH_LR12
Definition: misc.hh:1032
gem5::ArmISA::MISCREG_CNTV_TVAL_EL02
@ MISCREG_CNTV_TVAL_EL02
Definition: misc.hh:767
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:901
gem5::ArmISA::MISCREG_OSDLR_EL1
@ MISCREG_OSDLR_EL1
Definition: misc.hh:530
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: misc.hh:137
gem5::ArmISA::MISCREG_CNTKCTL_EL12
@ MISCREG_CNTKCTL_EL12
Definition: misc.hh:769
gem5::ArmISA::MISCREG_ICH_LR10
@ MISCREG_ICH_LR10
Definition: misc.hh:1030
gem5::ArmISA::MISCREG_CPSR_MODE
@ MISCREG_CPSR_MODE
Definition: misc.hh:78
gem5::ArmISA::MISCREG_ICC_AP1R1
@ MISCREG_ICC_AP1R1
Definition: misc.hh:966
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:544
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:202
gem5::ArmISA::MISCREG_L2CTLR_EL1
@ MISCREG_L2CTLR_EL1
Definition: misc.hh:734
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:606
gem5::ArmISA::MISCREG_ICH_VTR_EL2
@ MISCREG_ICH_VTR_EL2
Definition: misc.hh:894
gem5::ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: misc.hh:128
gem5::ArmISA::MISCREG_DBGBXVR4
@ MISCREG_DBGBXVR4
Definition: misc.hh:175
gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1
@ MISCREG_ICC_HPPIR0_EL1
Definition: misc.hh:840
gem5::ArmISA::MISCREG_ICH_LRC1
@ MISCREG_ICH_LRC1
Definition: misc.hh:1037
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:700
gem5::ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: misc.cc:3397
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:512
gem5::ArmISA::MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_DBGCLAIMCLR_EL1
Definition: misc.hh:533
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: misc.hh:265
gem5::ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition: misc.hh:543
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition: misc.hh:499
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: misc.hh:157
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:220
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:768
gem5::ArmISA::MISCREG_ICH_AP0R2
@ MISCREG_ICH_AP0R2
Definition: misc.hh:1008
gem5::ArmISA::MISCREG_HTCR
@ MISCREG_HTCR
Definition: misc.hh:263
gem5::ArmISA::MISCREG_DBGBXVR3
@ MISCREG_DBGBXVR3
Definition: misc.hh:174
gem5::ArmISA::MISCREG_ICC_SRE_NS
@ MISCREG_ICC_SRE_NS
Definition: misc.hh:1003
gem5::ArmISA::MISCREG_ICC_IGRPEN0
@ MISCREG_ICC_IGRPEN0
Definition: misc.hh:991
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:103
gem5::ArmISA::MISCREG_ICC_AP1R2_S
@ MISCREG_ICC_AP1R2_S
Definition: misc.hh:971
gem5::ArmISA::MISCREG_CPUMERRSR_EL1
@ MISCREG_CPUMERRSR_EL1
Definition: misc.hh:814
gem5::ArmISA::MISCREG_OSECCR_EL1
@ MISCREG_OSECCR_EL1
Definition: misc.hh:457
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:730
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition: misc.hh:191
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:217
gem5::ArmISA::decodeCP14Reg
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: misc.cc:54
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:271
gem5::ArmISA::MISCREG_ICC_HPPIR1
@ MISCREG_ICC_HPPIR1
Definition: misc.hh:987
gem5::ArmISA::MISCREG_ICH_LR4_EL2
@ MISCREG_ICH_LR4_EL2
Definition: misc.hh:903
gem5::ArmISA::MISCREG_APIBKeyHi_EL1
@ MISCREG_APIBKeyHi_EL1
Definition: misc.hh:833
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:458
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:332
gem5::ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition: misc.hh:600
gem5::ArmISA::MISCREG_ICH_LRC0
@ MISCREG_ICH_LRC0
Definition: misc.hh:1036
gem5::ArmISA::MISCREG_ICH_AP1R1
@ MISCREG_ICH_AP1R1
Definition: misc.hh:1011
gem5::ArmISA::MISCREG_VTCR
@ MISCREG_VTCR
Definition: misc.hh:264
gem5::ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: misc.hh:237
gem5::ArmISA::MISCREG_DBGWVR12
@ MISCREG_DBGWVR12
Definition: misc.hh:150
gem5::ArmISA::MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_DBGAUTHSTATUS_EL1
Definition: misc.hh:534
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_S
@ MISCREG_ICC_AP1R3_EL1_S
Definition: misc.hh:857
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:521
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition: misc.hh:776
gem5::ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: misc.hh:249
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:773
gem5::ArmISA::MISCREG_ICH_HCR_EL2
@ MISCREG_ICH_HCR_EL2
Definition: misc.hh:893
gem5::ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition: misc.hh:542
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unverifiable
chain unverifiable(bool v=true) const
Definition: isa.hh:177
gem5::ArmISA::MISCREG_PAR_S
@ MISCREG_PAR_S
Definition: misc.hh:296
gem5::ArmISA::MISCREG_CPUMERRSR
@ MISCREG_CPUMERRSR
Definition: misc.hh:449
gem5::ArmISA::MISCREG_ERRSELR_EL1
@ MISCREG_ERRSELR_EL1
Definition: misc.hh:1081
gem5::ArmISA::MISCREG_ICC_MCTLR
@ MISCREG_ICC_MCTLR
Definition: misc.hh:995
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:433
gem5::ArmISA::MISCREG_NOP
@ MISCREG_NOP
Definition: misc.hh:1068
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1
@ MISCREG_ICC_AP1R0_EL1
Definition: misc.hh:846
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:614
gem5::ArmISA::MISCREG_ICH_LR0_EL2
@ MISCREG_ICH_LR0_EL2
Definition: misc.hh:899
gem5::ArmISA::MISCREG_ICH_AP1R0
@ MISCREG_ICH_AP1R0
Definition: misc.hh:1010
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:331
gem5::ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: misc.hh:339
gem5::ArmISA::MISCREG_DBGCLAIMSET_EL1
@ MISCREG_DBGCLAIMSET_EL1
Definition: misc.hh:532
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: misc.hh:123
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:369
gem5::ArmISA::MISCREG_FCSEIDR
@ MISCREG_FCSEIDR
Definition: misc.hh:398
gem5::ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition: misc.hh:472
gem5::ArmISA::MISCREG_DBGDCCINT
@ MISCREG_DBGDCCINT
Definition: misc.hh:97
gem5::ArmISA::MISCREG_ICC_MSRE
@ MISCREG_ICC_MSRE
Definition: misc.hh:997
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition: misc.hh:170
gem5::ArmISA::canReadCoprocReg
std::tuple< bool, bool > canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to read coprocessor registers.
Definition: misc.cc:1209
gem5::ArmISA::MISCREG_PMEVCNTR1_EL0
@ MISCREG_PMEVCNTR1_EL0
Definition: misc.hh:791
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:209
gem5::ArmISA::MISCREG_L2ECTLR_EL1
@ MISCREG_L2ECTLR_EL1
Definition: misc.hh:735
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:154
gem5::ArmISA::MISCREG_ICC_AP0R1_EL1
@ MISCREG_ICC_AP0R1_EL1
Definition: misc.hh:843
gem5::ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: misc.hh:738
gem5::ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: misc.hh:130
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::writes
chain writes(bool v) const
Definition: isa.hh:428
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: misc.hh:132
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ArmISA::MISCREG_ICC_DIR_EL1
@ MISCREG_ICC_DIR_EL1
Definition: misc.hh:858
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked64
chain banked64(bool v=true) const
Definition: isa.hh:193
gem5::ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: misc.hh:168
gem5::ArmISA::MISCREG_ICH_VTR
@ MISCREG_ICH_VTR
Definition: misc.hh:1015
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition: misc.hh:463
gem5::ArmISA::MISCREG_HMAIR1
@ MISCREG_HMAIR1
Definition: misc.hh:388
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: misc.hh:306
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:562
gem5::ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition: misc.hh:580
gem5::ArmISA::MISCREG_ERRIDR_EL1
@ MISCREG_ERRIDR_EL1
Definition: misc.hh:1080
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:508
gem5::ArmISA::MISCREG_TPIDRURW_NS
@ MISCREG_TPIDRURW_NS
Definition: misc.hh:403
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: misc.hh:125
gem5::ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition: misc.hh:583
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:822
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:222
gem5::ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: misc.hh:1051
gem5::ArmISA::MISCREG_CP15ISB
@ MISCREG_CP15ISB
Definition: misc.hh:299
gem5::ArmISA::MISCREG_MDDTRTX_EL0
@ MISCREG_MDDTRTX_EL0
Definition: misc.hh:524
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition: misc.hh:548
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::banked
chain banked(bool v=true) const
Definition: isa.hh:189
gem5::ArmISA::MISCREG_PMCNTENSET
@ MISCREG_PMCNTENSET
Definition: misc.hh:352
gem5::ArmISA::MISCREG_ICH_LR10_EL2
@ MISCREG_ICH_LR10_EL2
Definition: misc.hh:909
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:250
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:595
gem5::ArmISA::MISCREG_CBAR_EL1
@ MISCREG_CBAR_EL1
Definition: misc.hh:816
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:224
gem5::ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition: misc.hh:602
gem5::ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition: misc.hh:453
gem5::ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition: misc.hh:746
gem5::ArmISA::MISCREG_DBGAUTHSTATUS
@ MISCREG_DBGAUTHSTATUS
Definition: misc.hh:194
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureWrite
chain monSecureWrite(bool v=true) const
Definition: isa.hh:349
gem5::ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: misc.hh:136
gem5::ArmISA::MISCREG_DBGWVR13
@ MISCREG_DBGWVR13
Definition: misc.hh:151
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:394
gem5::ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition: misc.hh:462
gem5::ArmISA::MISCREG_HACR
@ MISCREG_HACR
Definition: misc.hh:253
gem5::ArmISA::MISCREG_DL1DATA1_EL1
@ MISCREG_DL1DATA1_EL1
Definition: misc.hh:807
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:725
gem5::ArmISA::MISCREG_ERXMISC1_EL1
@ MISCREG_ERXMISC1_EL1
Definition: misc.hh:1087
gem5::ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition: misc.hh:492
gem5::ArmISA::MISCREG_OSDTRRX_EL1
@ MISCREG_OSDTRRX_EL1
Definition: misc.hh:454
gem5::ArmISA::MISCREG_BPIALL
@ MISCREG_BPIALL
Definition: misc.hh:300
gem5::ArmISA::MISCREG_DL1DATA4_EL1
@ MISCREG_DL1DATA4_EL1
Definition: misc.hh:810
gem5::ArmISA::MISCREG_CPUECTLR_EL1
@ MISCREG_CPUECTLR_EL1
Definition: misc.hh:813
gem5::ArmISA::MISCREG_DBGWVR6
@ MISCREG_DBGWVR6
Definition: misc.hh:144
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: misc.hh:159
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: misc.hh:356
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:378
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition: misc.hh:541
gem5::ArmISA::MISCREG_SPSR_IRQ_AA64
@ MISCREG_SPSR_IRQ_AA64
Definition: misc.hh:628
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: misc.hh:414
gem5::ArmISA::MISCREG_ICC_AP1R1_NS
@ MISCREG_ICC_AP1R1_NS
Definition: misc.hh:967
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:731
gem5::ArmISA::decodeCP15Reg64
MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1)
Definition: misc.cc:1150
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: misc.hh:64
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_S
@ MISCREG_ICC_AP1R1_EL1_S
Definition: misc.hh:851
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: misc.hh:75
gem5::ArmISA::MISCREG_TPIDRURW
@ MISCREG_TPIDRURW
Definition: misc.hh:402
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: misc.hh:539
gem5::ArmISA::MISCREG_DBGBXVR7
@ MISCREG_DBGBXVR7
Definition: misc.hh:178
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:660
gem5::ArmISA::MISCREG_ICC_SRE_EL1_NS
@ MISCREG_ICC_SRE_EL1_NS
Definition: misc.hh:873
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition: misc.hh:775
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:565
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1096
isa.hh
gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2
@ MISCREG_CNTHVS_CTL_EL2
Definition: misc.hh:784
gem5::ArmISA::MISCREG_PMEVTYPER2_EL0
@ MISCREG_PMEVTYPER2_EL0
Definition: misc.hh:798
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:288
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition: isa.hh:149
gem5::ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition: misc.hh:468
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:227
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_S
@ MISCREG_ICC_AP1R2_EL1_S
Definition: misc.hh:854
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:510
gem5::ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: misc.hh:74
gem5::ArmISA::MISCREG_HTTBR
@ MISCREG_HTTBR
Definition: misc.hh:447
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: misc.hh:62
gem5::ArmISA::MISCREG_CSSELR_S
@ MISCREG_CSSELR_S
Definition: misc.hh:232
gem5::ArmISA::MISCREG_CNTHP_TVAL
@ MISCREG_CNTHP_TVAL
Definition: misc.hh:432
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition: misc.hh:490
gem5::ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition: misc.hh:1145
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:364
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: misc.hh:292
gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition: misc.hh:861
gem5::ArmISA::MISCREG_ICC_AP1R3_NS
@ MISCREG_ICC_AP1R3_NS
Definition: misc.hh:973
gem5::ArmISA::MISCREG_CNTPS_CVAL_EL1
@ MISCREG_CNTPS_CVAL_EL1
Definition: misc.hh:771
gem5::ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition: misc.hh:723
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:234
gem5::ArmISA::MISCREG_CP15_UNIMPL
@ MISCREG_CP15_UNIMPL
Definition: misc.hh:1071
gem5::ArmISA::AArch32isUndefinedGenericTimer
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:1301
gem5::ArmISA::MISCREG_VSESR_EL2
@ MISCREG_VSESR_EL2
Definition: misc.hh:1089
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:90
gem5::ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: misc.hh:343
gem5::ArmISA::MISCREG_ICH_AP0R1
@ MISCREG_ICH_AP0R1
Definition: misc.hh:1007
gem5::ArmISA::MISCREG_HYP_E2H_S_RD
@ MISCREG_HYP_E2H_S_RD
Definition: misc.hh:1138
gem5::ArmISA::MISCREG_DBGCLAIMSET
@ MISCREG_DBGCLAIMSET
Definition: misc.hh:192
gem5::ArmISA::MISCREG_ICH_LR4
@ MISCREG_ICH_LR4
Definition: misc.hh:1024
gem5::ArmISA::MISCREG_HMAIR0
@ MISCREG_HMAIR0
Definition: misc.hh:387
gem5::ArmISA::MISCREG_ADFSR_S
@ MISCREG_ADFSR_S
Definition: misc.hh:276
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:507
gem5::ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition: misc.hh:317
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: misc.hh:882
gem5::ArmISA::MISCREG_MON_NS1_RD
@ MISCREG_MON_NS1_RD
Definition: misc.hh:1144
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:582
gem5::ArmISA::MISCREG_HYP_S_RD
@ MISCREG_HYP_S_RD
Definition: misc.hh:1133
gem5::ArmISA::MISCREG_ICH_LR1
@ MISCREG_ICH_LR1
Definition: misc.hh:1021
gem5::ArmISA::MISCREG_DBGBXVR8
@ MISCREG_DBGBXVR8
Definition: misc.hh:179
gem5::ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition: misc.hh:526
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: misc.hh:319
gem5::ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition: misc.hh:559
gem5::ArmISA::MISCREG_ICH_LRC10
@ MISCREG_ICH_LRC10
Definition: misc.hh:1046
gem5::ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: misc.hh:133
gem5::ArmISA::MISCREG_ICH_LR5_EL2
@ MISCREG_ICH_LR5_EL2
Definition: misc.hh:904
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition: misc.hh:551
gem5::ArmISA::MISCREG_DBGBVR8
@ MISCREG_DBGBVR8
Definition: misc.hh:114
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:274
gem5::ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition: misc.hh:364
gem5::ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition: misc.hh:200
gem5::ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition: misc.hh:585
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: misc.hh:617
gem5::ArmISA::MISCREG_TPIDRURO
@ MISCREG_TPIDRURO
Definition: misc.hh:405
gem5::ArmISA::MISCREG_ICH_AP1R1_EL2
@ MISCREG_ICH_AP1R1_EL2
Definition: misc.hh:890
gem5::ArmISA::MISCREG_DFAR_NS
@ MISCREG_DFAR_NS
Definition: misc.hh:284
gem5::ArmISA::MISCREG_ICH_ELRSR
@ MISCREG_ICH_ELRSR
Definition: misc.hh:1018
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:540
gem5::ArmISA::MISCREG_RAZ
@ MISCREG_RAZ
Definition: misc.hh:1069
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: misc.hh:238
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:680
gem5::ArmISA::MISCREG_DBGWVR11
@ MISCREG_DBGWVR11
Definition: misc.hh:149
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:625
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: misc.hh:286
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS
@ MISCREG_ICC_BPR1_EL1_NS
Definition: misc.hh:867
gem5::ArmISA::MISCREG_ERXCTLR_EL1
@ MISCREG_ERXCTLR_EL1
Definition: misc.hh:1083
gem5::ArmISA::MISCREG_ICC_EOIR1_EL1
@ MISCREG_ICC_EOIR1_EL1
Definition: misc.hh:864
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:665
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:627
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:661
gem5::ArmISA::MISCREG_ICC_AP1R1_S
@ MISCREG_ICC_AP1R1_S
Definition: misc.hh:968
gem5::ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition: misc.hh:975
gem5::ArmISA::MISCREG_DACR_NS
@ MISCREG_DACR_NS
Definition: misc.hh:266
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: misc.hh:396
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: misc.hh:741
gem5::ArmISA::MISCREG_HADFSR
@ MISCREG_HADFSR
Definition: misc.hh:280
gem5::ArmISA::MISCREG_DBGWVR14
@ MISCREG_DBGWVR14
Definition: misc.hh:152
gem5::ArmISA::MISCREG_ID_ISAR6_EL1
@ MISCREG_ID_ISAR6_EL1
Definition: misc.hh:557
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:214
gem5::ArmISA::MISCREG_ICC_BPR1_EL1
@ MISCREG_ICC_BPR1_EL1
Definition: misc.hh:866
gem5::ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition: misc.hh:834
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: misc.hh:205
gem5::ArmISA::MISCREG_APIAKeyHi_EL1
@ MISCREG_APIAKeyHi_EL1
Definition: misc.hh:831
gem5::ArmISA::MISCREG_DBGDEVID1
@ MISCREG_DBGDEVID1
Definition: misc.hh:196
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:478
gem5::ArmISA::MISCREG_IFSR_NS
@ MISCREG_IFSR_NS
Definition: misc.hh:272
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::MISCREG_PMCNTENSET_EL0
@ MISCREG_PMCNTENSET_EL0
Definition: misc.hh:713
gem5::ArmISA::MISCREG_ICH_VMCR_EL2
@ MISCREG_ICH_VMCR_EL2
Definition: misc.hh:898
gem5::ArmISA::MISCREG_DBGBXVR14
@ MISCREG_DBGBXVR14
Definition: misc.hh:185
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition: misc.hh:460
gem5::ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: misc.hh:294
gem5::ArmISA::MISCREG_CNTP_CVAL
@ MISCREG_CNTP_CVAL
Definition: misc.hh:419
gem5::ArmISA::MISCREG_BANKED
@ MISCREG_BANKED
Definition: misc.hh:1109
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition: misc.hh:774
gem5::ArmISA::MISCREG_CNTV_CTL_EL02
@ MISCREG_CNTV_CTL_EL02
Definition: misc.hh:765
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecure
chain monNonSecure(bool v=true) const
Definition: isa.hh:376
gem5::ArmISA::MISCREG_DL1DATA0
@ MISCREG_DL1DATA0
Definition: misc.hh:439
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hypSecure
chain hypSecure(bool v=true) const
Definition: isa.hh:319
gem5::ArmISA::MISCREG_ICC_SRE_S
@ MISCREG_ICC_SRE_S
Definition: misc.hh:1004
gem5::ArmISA::MISCREG_ICH_AP1R2_EL2
@ MISCREG_ICH_AP1R2_EL2
Definition: misc.hh:891
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: misc.hh:190
gem5::ArmISA::MISCREG_ICC_IGRPEN1_S
@ MISCREG_ICC_IGRPEN1_S
Definition: misc.hh:994
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:212
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:563
gem5::ArmISA::MISCREG_APDBKeyHi_EL1
@ MISCREG_APDBKeyHi_EL1
Definition: misc.hh:827
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::bankedChild
chain bankedChild(bool v=true) const
Definition: isa.hh:197
gem5::ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition: misc.hh:426
gem5::ArmISA::MISCREG_ICH_LR2_EL2
@ MISCREG_ICH_LR2_EL2
Definition: misc.hh:901
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:760
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition: misc.hh:878
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:289
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_ZCR_EL12
@ MISCREG_ZCR_EL12
Definition: misc.hh:1057
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:612
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: misc.hh:743
gem5::ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition: misc.hh:1001
gem5::ArmISA::MISCREG_PRI_NS_RD
@ MISCREG_PRI_NS_RD
Definition: misc.hh:1126
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S
@ MISCREG_ICC_BPR1_EL1_S
Definition: misc.hh:868
gem5::ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: misc.hh:393
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition: misc.hh:574
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:207
gem5::ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: misc.hh:134
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:334
gem5::ArmISA::MISCREG_PAR_NS
@ MISCREG_PAR_NS
Definition: misc.hh:295
gem5::ArmISA::MISCREG_HYP_E2H_NS_WR
@ MISCREG_HYP_E2H_NS_WR
Definition: misc.hh:1137
gem5::ArmISA::MISCREG_DBGDEVID2
@ MISCREG_DBGDEVID2
Definition: misc.hh:195
gem5::ArmISA::MISCREG_DBGBVR13
@ MISCREG_DBGBVR13
Definition: misc.hh:119
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: misc.hh:376
gem5::ArmISA::MISCREG_LOCKADDR
@ MISCREG_LOCKADDR
Definition: misc.hh:82
gem5::ArmISA::MISCREG_PMEVCNTR4_EL0
@ MISCREG_PMEVCNTR4_EL0
Definition: misc.hh:794
gem5::ArmISA::MISCREG_CNTHP_CVAL
@ MISCREG_CNTHP_CVAL
Definition: misc.hh:431
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition: misc.hh:189
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:268
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:375
gem5::ArmISA::MISCREG_ICH_AP1R3_EL2
@ MISCREG_ICH_AP1R3_EL2
Definition: misc.hh:892
gem5::ArmISA::MISCREG_APGAKeyLo_EL1
@ MISCREG_APGAKeyLo_EL1
Definition: misc.hh:830
gem5::ArmISA::MISCREG_DBGBXVR5
@ MISCREG_DBGBXVR5
Definition: misc.hh:176
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:474
gem5::ArmISA::MISCREG_PMCEID1_EL0
@ MISCREG_PMCEID1_EL0
Definition: misc.hh:719
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::MISCREG_IL1DATA1
@ MISCREG_IL1DATA1
Definition: misc.hh:436
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::unimplemented
chain unimplemented() const
Definition: isa.hh:174
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:758
gem5::ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition: misc.hh:560
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:642
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: misc.hh:257
gem5::ArmISA::MISCREG_RMR_EL3
@ MISCREG_RMR_EL3
Definition: misc.hh:744
gem5::ArmISA::MISCREG_MAIR0_S
@ MISCREG_MAIR0_S
Definition: misc.hh:374
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: misc.cc:3400
gem5::ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: misc.hh:288
gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1
@ MISCREG_ICC_IGRPEN0_EL1
Definition: misc.hh:875
gem5::ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition: misc.hh:638
gem5::ArmISA::MISCREG_HTPIDR
@ MISCREG_HTPIDR
Definition: misc.hh:411
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: misc.hh:634
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: misc.hh:1054
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: misc.hh:155
gem5::ArmISA::MISCREG_TTBR0_S
@ MISCREG_TTBR0_S
Definition: misc.hh:256
gem5::ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition: misc.hh:750
gem5::ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition: misc.hh:502
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:698
gem5::ArmISA::MISCREG_IC_IALLU
@ MISCREG_IC_IALLU
Definition: misc.hh:656
gem5::ArmISA::MISCREG_ICH_LRC13
@ MISCREG_ICH_LRC13
Definition: misc.hh:1049
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:90
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:481
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:479
full_system.hh
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:372
gem5::ArmISA::MISCREG_ICH_LRC11
@ MISCREG_ICH_LRC11
Definition: misc.hh:1047
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::reads
chain reads(bool v) const
Definition: isa.hh:418
gem5::ArmISA::MISCREG_DBGWVR4
@ MISCREG_DBGWVR4
Definition: misc.hh:142
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:683
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition: misc.hh:545
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1
@ MISCREG_ICC_AP1R3_EL1
Definition: misc.hh:855
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition: misc.hh:244
gem5::ArmISA::ISA::haveSecurity
bool haveSecurity
Definition: isa.hh:91
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:484
gem5::ArmISA::MISCREG_HYP_S_WR
@ MISCREG_HYP_S_WR
Definition: misc.hh:1134
gem5::ArmISA::MISCREG_AFSR0_EL3
@ MISCREG_AFSR0_EL3
Definition: misc.hh:646
gem5::ArmISA::MISCREG_DBGBVR14
@ MISCREG_DBGBVR14
Definition: misc.hh:120
gem5::ArmISA::MISCREG_DLR_EL0
@ MISCREG_DLR_EL0
Definition: misc.hh:624
gem5::ArmISA::MISCREG_ICC_SRE_EL1_S
@ MISCREG_ICC_SRE_EL1_S
Definition: misc.hh:874
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::MISCREG_CBAR
@ MISCREG_CBAR
Definition: misc.hh:446
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: misc.hh:126
gem5::ArmISA::MISCREG_DBGWVR3
@ MISCREG_DBGWVR3
Definition: misc.hh:141
gem5::ArmISA::MISCREG_MON_NS0_RD
@ MISCREG_MON_NS0_RD
Definition: misc.hh:1141
gem5::ArmISA::MISCREG_PMINTENCLR
@ MISCREG_PMINTENCLR
Definition: misc.hh:365
gem5::ArmISA::MISCREG_SPSR_UND_AA64
@ MISCREG_SPSR_UND_AA64
Definition: misc.hh:630
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:323
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::ArmISA::MISCREG_IL1DATA2_EL1
@ MISCREG_IL1DATA2_EL1
Definition: misc.hh:804
gem5::ArmISA::MISCREG_MDDTR_EL0
@ MISCREG_MDDTR_EL0
Definition: misc.hh:523
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:788
gem5::ArmISA::MISCREG_SPSR_ABT_AA64
@ MISCREG_SPSR_ABT_AA64
Definition: misc.hh:629
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:506
gem5::ArmISA::MISCREG_ICH_LR15
@ MISCREG_ICH_LR15
Definition: misc.hh:1035
gem5::ArmISA::MISCREG_ICC_AP1R0_S
@ MISCREG_ICC_AP1R0_S
Definition: misc.hh:965
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: misc.hh:308
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:229
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: misc.hh:632
gem5::ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: misc.hh:160
gem5::ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition: misc.hh:1000
gem5::ArmISA::MISCREG_RMR
@ MISCREG_RMR
Definition: misc.hh:395
gem5::ArmISA::MISCREG_VBAR_NS
@ MISCREG_VBAR_NS
Definition: misc.hh:392
gem5::ArmISA::MISCREG_ICH_EISR_EL2
@ MISCREG_ICH_EISR_EL2
Definition: misc.hh:896
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:517
gem5::ArmISA::MISCREG_IL1DATA1_EL1
@ MISCREG_IL1DATA1_EL1
Definition: misc.hh:803
gem5::ArmISA::MISCREG_APGAKeyHi_EL1
@ MISCREG_APGAKeyHi_EL1
Definition: misc.hh:829
gem5::ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition: misc.hh:277
gem5::ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: misc.hh:81
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: misc.hh:302
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: misc.hh:305
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition: misc.hh:467
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:206
gem5::ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: misc.hh:1093
gem5::ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition: misc.hh:497
gem5::ArmISA::MISCREG_DBGOSECCR
@ MISCREG_DBGOSECCR
Definition: misc.hh:105
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition: misc.hh:198
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:330
gem5::ArmISA::MISCREG_ICC_CTLR_NS
@ MISCREG_ICC_CTLR_NS
Definition: misc.hh:981
gem5::ArmISA::MISCREG_DBGBXVR13
@ MISCREG_DBGBXVR13
Definition: misc.hh:184
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:248
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: misc.hh:285
gem5::ArmISA::MISCREG_ICC_DIR
@ MISCREG_ICC_DIR
Definition: misc.hh:983
gem5::ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition: misc.hh:862
gem5::ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: misc.hh:342
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: misc.hh:320
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition: misc.hh:274
gem5::ArmISA::MISCREG_ICC_AP0R2
@ MISCREG_ICC_AP0R2
Definition: misc.hh:961
gem5::ArmISA::MISCREG_PMXEVCNTR
@ MISCREG_PMXEVCNTR
Definition: misc.hh:362
gem5::ArmISA::MISCREG_ICC_AP0R3
@ MISCREG_ICC_AP0R3
Definition: misc.hh:962
gem5::ArmISA::MISCREG_IFSR_S
@ MISCREG_IFSR_S
Definition: misc.hh:273
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:261
gem5::ArmISA::MISCREG_AFSR1_EL3
@ MISCREG_AFSR1_EL3
Definition: misc.hh:647
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: misc.hh:311
gem5::ArmISA::MISCREG_AIFSR_NS
@ MISCREG_AIFSR_NS
Definition: misc.hh:278
gem5::ArmISA::MISCREG_ICH_LR8
@ MISCREG_ICH_LR8
Definition: misc.hh:1028
gem5::ArmISA::MISCREG_CNTHP_CTL
@ MISCREG_CNTHP_CTL
Definition: misc.hh:430
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: misc.hh:65
gem5::ArmISA::MISCREG_L2MERRSR_EL1
@ MISCREG_L2MERRSR_EL1
Definition: misc.hh:815
gem5::ArmISA::MISCREG_ICC_SRE
@ MISCREG_ICC_SRE
Definition: misc.hh:1002
gem5::ArmISA::MISCREG_ICH_LR8_EL2
@ MISCREG_ICH_LR8_EL2
Definition: misc.hh:907
gem5::ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: misc.hh:80
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:676
gem5::ArmISA::ISA::InitReg
const MiscRegLUTEntryInitializer InitReg(uint32_t reg)
Definition: isa.hh:453
gem5::ArmISA::MISCREG_TPIDRURO_S
@ MISCREG_TPIDRURO_S
Definition: misc.hh:407
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:757
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: misc.hh:1058
gem5::ArmISA::MISCREG_VDISR_EL2
@ MISCREG_VDISR_EL2
Definition: misc.hh:1090
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:686
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:228
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: misc.hh:605
gem5::ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: misc.hh:885
gem5::ArmISA::MISCREG_L2ACTLR
@ MISCREG_L2ACTLR
Definition: misc.hh:445
gem5::ArmISA::MISCREG_DBGBVR12
@ MISCREG_DBGBVR12
Definition: misc.hh:118
gem5::ArmISA::MISCREG_ICH_ELRSR_EL2
@ MISCREG_ICH_ELRSR_EL2
Definition: misc.hh:897
gem5::ArmISA::MISCREG_DSPSR_EL0
@ MISCREG_DSPSR_EL0
Definition: misc.hh:623
gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition: misc.hh:783
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:326
gem5::ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: misc.hh:348
gem5::ArmISA::MISCREG_ICH_VMCR
@ MISCREG_ICH_VMCR
Definition: misc.hh:1019
gem5::ArmISA::MISCREG_ICC_SRE_EL1
@ MISCREG_ICC_SRE_EL1
Definition: misc.hh:872
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:689
gem5::ArmISA::MISCREG_ICH_HCR
@ MISCREG_ICH_HCR
Definition: misc.hh:1014
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: misc.hh:124
gem5::ArmISA::MISCREG_DBGWVR8
@ MISCREG_DBGWVR8
Definition: misc.hh:146
gem5::ArmISA::MISCREG_AMAIR0_S
@ MISCREG_AMAIR0_S
Definition: misc.hh:383
misc.hh
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:476
gem5::ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition: misc.hh:466
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:513
gem5::ArmISA::MISCREG_PMEVCNTR3_EL0
@ MISCREG_PMEVCNTR3_EL0
Definition: misc.hh:793
gem5::ArmISA::MISCREG_ICH_LRC3
@ MISCREG_ICH_LRC3
Definition: misc.hh:1039
gem5::ArmISA::MISCREG_CNTP_CVAL_NS
@ MISCREG_CNTP_CVAL_NS
Definition: misc.hh:420
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_NS
@ MISCREG_ICC_AP1R2_EL1_NS
Definition: misc.hh:853
gem5::ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:72
gem5::ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:162
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:188
gem5::ArmISA::MISCREG_DBGWVR2
@ MISCREG_DBGWVR2
Definition: misc.hh:140
gem5::ArmISA::MISCREG_TPIDRPRW_S
@ MISCREG_TPIDRPRW_S
Definition: misc.hh:410
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: misc.hh:837
gem5::ArmISA::MISCREG_AIFSR_S
@ MISCREG_AIFSR_S
Definition: misc.hh:279
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
gem5::ArmISA::MISCREG_ICC_AP1R0_NS
@ MISCREG_ICC_AP1R0_NS
Definition: misc.hh:964
gem5::ArmISA::MISCREG_ICC_CTLR_S
@ MISCREG_ICC_CTLR_S
Definition: misc.hh:982
gem5::ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition: misc.hh:547
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition: misc.hh:648
gem5::ArmISA::MISCREG_UNKNOWN
@ MISCREG_UNKNOWN
Definition: misc.hh:1072
gem5::ArmISA::MISCREG_ICH_AP0R3
@ MISCREG_ICH_AP0R3
Definition: misc.hh:1009
gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2
@ MISCREG_CNTHPS_CTL_EL2
Definition: misc.hh:777
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:626
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:211
gem5::ArmISA::MISCREG_CP15DSB
@ MISCREG_CP15DSB
Definition: misc.hh:314
gem5::ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition: misc.hh:494
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:289
gem5::ArmISA::MISCREG_VSTCR_EL2
@ MISCREG_VSTCR_EL2
Definition: misc.hh:608
gem5::ArmISA::MISCREG_ICH_LR9
@ MISCREG_ICH_LR9
Definition: misc.hh:1029
gem5::ArmISA::MISCREG_PMEVTYPER1_EL0
@ MISCREG_PMEVTYPER1_EL0
Definition: misc.hh:797
gem5::ArmISA::MISCREG_ICH_LR3_EL2
@ MISCREG_ICH_LR3_EL2
Definition: misc.hh:902
logging.hh
gem5::ArmISA::MISCREG_DBGBXVR0
@ MISCREG_DBGBXVR0
Definition: misc.hh:171
gem5::ArmISA::MISCREG_DBGDTRTXext
@ MISCREG_DBGDTRTXext
Definition: misc.hh:104
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:578
gem5::ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition: misc.hh:727
gem5::ArmISA::MISCREG_ICC_IAR0
@ MISCREG_ICC_IAR0
Definition: misc.hh:989
gem5::ArmISA::MISCREG_PMEVTYPER3_EL0
@ MISCREG_PMEVTYPER3_EL0
Definition: misc.hh:799
gem5::ArmISA::MISCREG_ICH_LRC4
@ MISCREG_ICH_LRC4
Definition: misc.hh:1040
gem5::ArmISA::MISCREG_DBGWFAR
@ MISCREG_DBGWFAR
Definition: misc.hh:100
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:790
gem5::ArmISA::MISCREG_ICC_CTLR
@ MISCREG_ICC_CTLR
Definition: misc.hh:980
gem5::ArmISA::MISCREG_ICC_BPR0
@ MISCREG_ICC_BPR0
Definition: misc.hh:976
gem5::ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:707
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:210
gem5::ArmISA::MISCREG_NMRR_S
@ MISCREG_NMRR_S
Definition: misc.hh:377
gem5::ArmISA::MISCREG_ICC_CTLR_EL1
@ MISCREG_ICC_CTLR_EL1
Definition: misc.hh:869
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:480
gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_CVAL_EL2
Definition: misc.hh:778
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: misc.hh:67
gem5::ArmISA::MISCREG_ICC_IAR1_EL1
@ MISCREG_ICC_IAR1_EL1
Definition: misc.hh:863
gem5::ArmISA::MISCREG_OSDTRTX_EL1
@ MISCREG_OSDTRTX_EL1
Definition: misc.hh:456
gem5::ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition: misc.hh:505
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: misc.hh:70
gem5::ArmISA::MISCREG_ERXMISC0_EL1
@ MISCREG_ERXMISC0_EL1
Definition: misc.hh:1086
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:622
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: misc.hh:1055
gem5::ArmISA::MISCREG_DBGBVR10
@ MISCREG_DBGBVR10
Definition: misc.hh:116
gem5::ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition: misc.hh:465
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition: misc.hh:397
gem5::ArmISA::snsBankedIndex
int snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:1313
gem5::ArmISA::MISCREG_USR_S_RD
@ MISCREG_USR_S_RD
Definition: misc.hh:1123
gem5::ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition: misc.hh:391
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:635
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: misc.hh:360
gem5::ArmISA::MISCREG_ICH_LR11
@ MISCREG_ICH_LR11
Definition: misc.hh:1031
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition: misc.hh:282
gem5::ArmISA::MISCREG_ICC_AP0R1
@ MISCREG_ICC_AP0R1
Definition: misc.hh:960
gem5::ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition: misc.hh:636
gem5::ArmISA::MISCREG_DBGBXVR6
@ MISCREG_DBGBXVR6
Definition: misc.hh:177
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:226
gem5::ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition: misc.hh:197
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:817
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition: misc.hh:633
gem5::ArmISA::MISCREG_DACR_S
@ MISCREG_DACR_S
Definition: misc.hh:267
gem5::ArmISA::MISCREG_HYP_E2H_S_WR
@ MISCREG_HYP_E2H_S_WR
Definition: misc.hh:1139
gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition: misc.hh:782
gem5::ArmISA::MISCREG_IFAR_NS
@ MISCREG_IFAR_NS
Definition: misc.hh:287
gem5::ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition: misc.hh:424
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: misc.hh:576
gem5::ArmISA::MISCREG_TTBR1_NS
@ MISCREG_TTBR1_NS
Definition: misc.hh:258
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:621
gem5::ArmISA::MISCREG_ICH_LRC7
@ MISCREG_ICH_LRC7
Definition: misc.hh:1043
gem5::ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition: misc.hh:657
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:753
gem5::ArmISA::MISCREG_DBGBVR0
@ MISCREG_DBGBVR0
Definition: misc.hh:106
gem5::ArmISA::MISCREG_TPIDR_EL0
@ MISCREG_TPIDR_EL0
Definition: misc.hh:748
gem5::ArmISA::MISCREG_PMCEID0_EL0
@ MISCREG_PMCEID0_EL0
Definition: misc.hh:718
gem5::ArmISA::MISCREG_PMCEID0
@ MISCREG_PMCEID0
Definition: misc.hh:357
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition: misc.hh:668
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:326
gem5::ArmISA::MISCREG_ICH_LRC14
@ MISCREG_ICH_LRC14
Definition: misc.hh:1050
gem5::ArmISA::MISCREG_TTBR1_S
@ MISCREG_TTBR1_S
Definition: misc.hh:259
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: misc.hh:156
gem5::ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition: misc.hh:464
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:322
gem5::ArmISA::MISCREG_ICC_SRE_EL2
@ MISCREG_ICC_SRE_EL2
Definition: misc.hh:879
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:673
gem5::ArmISA::MISCREG_RAMINDEX
@ MISCREG_RAMINDEX
Definition: misc.hh:444
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_ICC_AP0R2_EL1
@ MISCREG_ICC_AP0R2_EL1
Definition: misc.hh:844
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:637
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:694
gem5::ArmISA::MISCREG_VSTTBR_EL2
@ MISCREG_VSTTBR_EL2
Definition: misc.hh:607
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:335
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: misc.hh:304
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:597
gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1
@ MISCREG_ICC_HPPIR1_EL1
Definition: misc.hh:865
gem5::ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition: misc.hh:1077
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:485
gem5::ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: misc.hh:709
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureWrite
chain privSecureWrite(bool v=true) const
Definition: isa.hh:241
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:699
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:336
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: misc.hh:1056
gem5::ArmISA::MISCREG_PMEVTYPER4_EL0
@ MISCREG_PMEVTYPER4_EL0
Definition: misc.hh:800
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:651
gem5::ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: misc.hh:91
gem5::ArmISA::MISCREG_DBGBVR4
@ MISCREG_DBGBVR4
Definition: misc.hh:110
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition: misc.hh:653
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:684
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:514
gem5::ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition: misc.hh:470
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: misc.hh:96
gem5::ArmISA::MISCREG_ICC_BPR1_S
@ MISCREG_ICC_BPR1_S
Definition: misc.hh:979
gem5::ArmISA::MISCREG_DBGCLAIMCLR
@ MISCREG_DBGCLAIMCLR
Definition: misc.hh:193
gem5::ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: misc.hh:166
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: misc.hh:652
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:324
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:685
gem5::ArmISA::MISCREG_ICH_LR14
@ MISCREG_ICH_LR14
Definition: misc.hh:1034
gem5::ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition: misc.hh:645
gem5::ArmISA::MISCREG_ICH_LR7_EL2
@ MISCREG_ICH_LR7_EL2
Definition: misc.hh:906
gem5::ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition: misc.hh:598
gem5::ArmISA::MISCREG_PMCCNTR
@ MISCREG_PMCCNTR
Definition: misc.hh:359
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: misc.hh:425
gem5::ArmISA::MISCREG_CNTP_CTL_S
@ MISCREG_CNTP_CTL_S
Definition: misc.hh:418
gem5::ArmISA::MISCREG_ERXFR_EL1
@ MISCREG_ERXFR_EL1
Definition: misc.hh:1082
gem5::ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition: misc.hh:724
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: misc.hh:349
gem5::ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition: misc.hh:581
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition: misc.hh:571
gem5::ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition: misc.hh:89
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition: misc.hh:781
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1
@ MISCREG_ICC_IGRPEN1_EL1
Definition: misc.hh:876
gem5::ArmISA::MISCREG_DBGBXVR12
@ MISCREG_DBGBXVR12
Definition: misc.hh:183
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition: misc.hh:291
gem5::ArmISA::MISCREG_ERXADDR_EL1
@ MISCREG_ERXADDR_EL1
Definition: misc.hh:1085
gem5::ArmISA::MISCREG_CNTP_CVAL_EL02
@ MISCREG_CNTP_CVAL_EL02
Definition: misc.hh:763
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:639
gem5::ArmISA::MISCREG_ICH_AP1R3
@ MISCREG_ICH_AP1R3
Definition: misc.hh:1013
gem5::ArmISA::MISCREG_TPIDR_EL1
@ MISCREG_TPIDR_EL1
Definition: misc.hh:747
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:215
gem5::ArmISA::MISCREG_DBGWVR7
@ MISCREG_DBGWVR7
Definition: misc.hh:145
gem5::ArmISA::MISCREG_ICH_LR14_EL2
@ MISCREG_ICH_LR14_EL2
Definition: misc.hh:913
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition: misc.hh:877
gem5::ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition: misc.hh:611
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:678
gem5::ArmISA::MISCREG_ICC_HPPIR0
@ MISCREG_ICC_HPPIR0
Definition: misc.hh:986
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:736
gem5::ArmISA::MISCREG_ICC_AP1R2
@ MISCREG_ICC_AP1R2
Definition: misc.hh:969
gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:705
gem5::ArmISA::MISCREG_AMAIR1_S
@ MISCREG_AMAIR1_S
Definition: misc.hh:386
gem5::ArmISA::MISCREG_TPIDRPRW
@ MISCREG_TPIDRPRW
Definition: misc.hh:408
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:697
gem5::ArmISA::MISCREG_PMCNTENCLR_EL0
@ MISCREG_PMCNTENCLR_EL0
Definition: misc.hh:714
gem5::ArmISA::MISCREG_IL1DATA2
@ MISCREG_IL1DATA2
Definition: misc.hh:437
gem5::ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition: misc.hh:496
gem5::ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition: misc.hh:640
gem5::ArmISA::MISCREG_DBGBVR11
@ MISCREG_DBGBVR11
Definition: misc.hh:117
gem5::ArmISA::MISCREG_MON_E2H_RD
@ MISCREG_MON_E2H_RD
Definition: misc.hh:1147
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:241
gem5::ArmISA::MISCREG_IL1DATA3
@ MISCREG_IL1DATA3
Definition: misc.hh:438
gem5::ArmISA::decodeCP15Reg
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: misc.cc:340
gem5::ArmISA::MISCREG_MON_E2H_WR
@ MISCREG_MON_E2H_WR
Definition: misc.hh:1148
gem5::ArmISA::MISCREG_ID_MMFR4_EL1
@ MISCREG_ID_MMFR4_EL1
Definition: misc.hh:550
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:455
gem5::ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition: misc.hh:500
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:488
gem5::ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition: misc.hh:737
gem5::ArmISA::MISCREG_ICH_LR7
@ MISCREG_ICH_LR7
Definition: misc.hh:1027
gem5::ArmISA::MISCREG_ICC_BPR1
@ MISCREG_ICC_BPR1
Definition: misc.hh:977
gem5::ArmISA::MISCREG_PMEVCNTR2_EL0
@ MISCREG_PMEVCNTR2_EL0
Definition: misc.hh:792
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: misc.hh:68
gem5::ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: misc.cc:1349
gem5::ArmISA::MISCREG_TEECR32_EL1
@ MISCREG_TEECR32_EL1
Definition: misc.hh:535
gem5::ArmISA::MISCREG_ICC_RPR
@ MISCREG_ICC_RPR
Definition: misc.hh:999
gem5::ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: misc.hh:129
gem5::ArmISA::MISCREG_BANKED_CHILD
@ MISCREG_BANKED_CHILD
Definition: misc.hh:1115
gem5::ArmISA::MISCREG_HYP_NS_RD
@ MISCREG_HYP_NS_RD
Definition: misc.hh:1131
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: misc.hh:739
thread_context.hh
gem5::ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition: misc.hh:658
gem5::ArmISA::MISCREG_ICC_AP1R3_S
@ MISCREG_ICC_AP1R3_S
Definition: misc.hh:974
gem5::ArmISA::MISCREG_ICH_LRC12
@ MISCREG_ICH_LRC12
Definition: misc.hh:1048
gem5::ArmISA::MISCREG_HAIFSR
@ MISCREG_HAIFSR
Definition: misc.hh:281
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:567
gem5::ArmISA::MISCREG_ICH_MISR
@ MISCREG_ICH_MISR
Definition: misc.hh:1016
gem5::ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition: misc.hh:572
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:528
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:659
gem5::ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition: misc.hh:471
gem5::ArmISA::MISCREG_DBGDTRTXint
@ MISCREG_DBGDTRTXint
Definition: misc.hh:98
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:820
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:213
gem5::ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: misc.hh:135
gem5::ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition: misc.hh:613
gem5::ArmISA::MISCREG_PMCR_EL0
@ MISCREG_PMCR_EL0
Definition: misc.hh:712
gem5::ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition: misc.hh:558
gem5::ArmISA::MISCREG_ICH_LRC9
@ MISCREG_ICH_LRC9
Definition: misc.hh:1045
gem5::ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition: misc.hh:796
gem5::ArmISA::MISCREG_DBGBVR5
@ MISCREG_DBGBVR5
Definition: misc.hh:111
gem5::ArmISA::MISCREG_DBGBVR1
@ MISCREG_DBGBVR1
Definition: misc.hh:107
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: misc.hh:340
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:327
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:693
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:1365
gem5::ArmISA::MISCREG_ICC_AP0R0_EL1
@ MISCREG_ICC_AP0R0_EL1
Definition: misc.hh:842
gem5::ArmISA::MISCREG_DBGBXVR2
@ MISCREG_DBGBXVR2
Definition: misc.hh:173
gem5::ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition: misc.hh:138
gem5::ArmISA::MISCREG_DL1DATA4
@ MISCREG_DL1DATA4
Definition: misc.hh:443
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:601
gem5::ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition: misc.hh:461
gem5::ArmISA::ISA::impdefAsNop
bool impdefAsNop
If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED ...
Definition: isa.hh:111
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::MISCREG_L2ECTLR
@ MISCREG_L2ECTLR
Definition: misc.hh:368
gem5::ArmISA::MISCREG_DBGBVR9
@ MISCREG_DBGBVR9
Definition: misc.hh:115
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:692
gem5::ArmISA::MISCREG_ICC_AP1R0
@ MISCREG_ICC_AP1R0
Definition: misc.hh:963
gem5::ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition: misc.hh:469
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition: misc.hh:522
gem5::ArmISA::MISCREG_ICH_LR6_EL2
@ MISCREG_ICH_LR6_EL2
Definition: misc.hh:905
gem5::ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: misc.hh:708
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1
@ MISCREG_ICC_AP1R1_EL1
Definition: misc.hh:849
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1
@ MISCREG_ICC_AP1R2_EL1
Definition: misc.hh:852
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:761
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:670
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:519
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: misc.hh:79
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: misc.hh:69
gem5::ArmISA::MISCREG_HYP_NS_WR
@ MISCREG_HYP_NS_WR
Definition: misc.hh:1132
gem5::ArmISA::MISCREG_ERXSTATUS_EL1
@ MISCREG_ERXSTATUS_EL1
Definition: misc.hh:1084
gem5::ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition: misc.hh:495
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