isa.hh

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/*
 * Copyright (c) 2020 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Copyright 2020 Google Inc.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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#ifndef __ARCH_GENERIC_ISA_HH__
#define __ARCH_GENERIC_ISA_HH__
 
#include <vector>
 
#include "cpu/reg_class.hh"
#include "enums/VecRegRenameMode.hh"
#include "sim/sim_object.hh"
 
namespace gem5
{
 
class ThreadContext;
 
class BaseISA : public SimObject
{
  public:
    typedef std::vector<RegClassInfo> RegClasses;
 
  protected:
    using SimObject::SimObject;
 
    ThreadContext *tc = nullptr;
 
    RegClasses _regClasses;
 
  public:
    virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) {}
    virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
 
    virtual uint64_t getExecutingAsid() const { return 0; }
    virtual bool inUserMode() const = 0;
    virtual void copyRegsFrom(ThreadContext *src) = 0;
 
    virtual enums::VecRegRenameMode
    initVecRegRenameMode() const
    {
        return enums::Full;
    }
 
    virtual enums::VecRegRenameMode
    vecRegRenameMode(ThreadContext *_tc) const
    {
        return initVecRegRenameMode();
    }
 
    const RegClasses &regClasses() const { return _regClasses; }
};
 
} // namespace gem5
 
#endif // __ARCH_GENERIC_ISA_HH__