stage2_lookup.hh

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#ifndef __ARCH_ARM_STAGE2_LOOKUP_HH__
#define __ARCH_ARM_STAGE2_LOOKUP_HH__
 
#include <list>
 
#include "arch/arm/system.hh"
#include "arch/arm/table_walker.hh"
#include "arch/arm/tlb.hh"
#include "arch/generic/mmu.hh"
#include "mem/request.hh"
 
namespace gem5
{
 
class ThreadContext;
 
namespace ArmISA {
class Translation;
class TLB;
 
 
class Stage2LookUp : public BaseMMU::Translation
{
  private:
    TLB                     *stage1Tlb;
    TLB               *stage2Tlb;
    TlbEntry                stage1Te;
    RequestPtr              s1Req;
    BaseMMU::Translation    *transState;
    BaseMMU::Mode           mode;
    bool                    timing;
    bool                    functional;
    TLB::ArmTranslationType tranType;
    TlbEntry                *stage2Te;
    RequestPtr              req;
    Fault                   fault;
    bool                    complete;
    bool                    selfDelete;
    bool                    secure;
 
  public:
    Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, const RequestPtr &_req,
        BaseMMU::Translation *_transState, BaseMMU::Mode _mode, bool _timing,
        bool _functional, bool _secure, TLB::ArmTranslationType _tranType) :
        stage1Tlb(s1Tlb), stage2Tlb(s2Tlb), stage1Te(s1Te), s1Req(_req),
        transState(_transState), mode(_mode), timing(_timing),
        functional(_functional), tranType(_tranType), stage2Te(nullptr),
        fault(NoFault), complete(false), selfDelete(false), secure(_secure)
    {
        req = std::make_shared<Request>();
        req->setVirt(s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(),
                     s1Req->getFlags(), s1Req->requestorId(), 0);
    }
 
    Fault getTe(ThreadContext *tc, TlbEntry *destTe);
 
    void mergeTe(const RequestPtr &req, BaseMMU::Mode mode);
 
    void setSelfDelete() { selfDelete = true; }
 
    bool isComplete() const { return complete; }
 
    void markDelayed() {}
 
    void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
                BaseMMU::Mode mode);
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif //__ARCH_ARM_STAGE2_LOOKUP_HH__