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isa.cc
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37 
38 #include "arch/arm/isa.hh"
39 
40 #include "arch/arm/decoder.hh"
41 #include "arch/arm/faults.hh"
42 #include "arch/arm/htm.hh"
43 #include "arch/arm/interrupts.hh"
44 #include "arch/arm/mmu.hh"
45 #include "arch/arm/pmu.hh"
46 #include "arch/arm/regs/misc.hh"
47 #include "arch/arm/self_debug.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/tlbi_op.hh"
50 #include "arch/arm/utility.hh"
51 #include "arch/generic/decoder.hh"
52 #include "base/cprintf.hh"
53 #include "cpu/base.hh"
54 #include "cpu/checker/cpu.hh"
55 #include "cpu/reg_class.hh"
56 #include "debug/Arm.hh"
57 #include "debug/LLSC.hh"
58 #include "debug/MiscRegs.hh"
59 #include "dev/arm/generic_timer.hh"
60 #include "dev/arm/gic_v3.hh"
61 #include "dev/arm/gic_v3_cpu_interface.hh"
62 #include "params/ArmISA.hh"
63 #include "sim/faults.hh"
64 #include "sim/stat_control.hh"
65 #include "sim/system.hh"
66 
67 namespace gem5
68 {
69 
70 namespace ArmISA
71 {
72 
73 class MiscRegClassOps : public RegClassOps
74 {
75  public:
76  std::string
77  regName(const RegId &id) const override
78  {
79  return miscRegName[id.index()];
80  }
81 } miscRegClassOps;
82 
83 ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
84  _decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
85  afterStartup(false)
86 {
87  _regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
88  _regClasses.emplace_back(0);
89  _regClasses.emplace_back(NumVecRegs);
90  _regClasses.emplace_back(NumVecRegs * TheISA::NumVecElemPerVecReg);
91  _regClasses.emplace_back(NumVecPredRegs);
92  _regClasses.emplace_back(NUM_CCREGS);
93  _regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);
94 
95  miscRegs[MISCREG_SCTLR_RST] = 0;
96 
97  // Hook up a dummy device if we haven't been configured with a
98  // real PMU. By using a dummy device, we don't need to check that
99  // the PMU exist every time we try to access a PMU register.
100  if (!pmu)
101  pmu = &dummyDevice;
102 
103  // Give all ISA devices a pointer to this ISA
104  pmu->setISA(this);
105 
106  system = dynamic_cast<ArmSystem *>(p.system);
107 
108  // Cache system-level properties
109  if (FullSystem && system) {
110  highestELIs64 = system->highestELIs64();
111  haveLargeAsid64 = system->haveLargeAsid64();
112  physAddrRange = system->physAddrRange();
113  sveVL = system->sveVL();
114 
115  release = system->releaseFS();
116  } else {
117  highestELIs64 = true; // ArmSystem::highestELIs64 does the same
118  haveLargeAsid64 = false;
119  physAddrRange = 32; // dummy value
120  sveVL = p.sve_vl_se;
121 
122  release = p.release_se;
123  }
124 
125  selfDebug = new SelfDebug();
126  initializeMiscRegMetadata();
127  preUnflattenMiscReg();
128 
129  clear();
130 }
131 
132 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
133 
134 void
135 ISA::clear()
136 {
137  const Params &p(params());
138 
139  // Invalidate cached copies of miscregs in the TLBs
140  if (tc) {
141  getMMUPtr(tc)->invalidateMiscReg();
142  }
143 
144  SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
145  memset(miscRegs, 0, sizeof(miscRegs));
146 
147  initID32(p);
148 
149  // We always initialize AArch64 ID registers even
150  // if we are in AArch32. This is done since if we
151  // are in SE mode we don't know if our ArmProcess is
152  // AArch32 or AArch64
153  initID64(p);
154 
155  // Start with an event in the mailbox
156  miscRegs[MISCREG_SEV_MAILBOX] = 1;
157 
158  // Separate Instruction and Data TLBs
159  miscRegs[MISCREG_TLBTR] = 1;
160 
161  MVFR0 mvfr0 = 0;
162  mvfr0.advSimdRegisters = 2;
163  mvfr0.singlePrecision = 2;
164  mvfr0.doublePrecision = 2;
165  mvfr0.vfpExceptionTrapping = 0;
166  mvfr0.divide = 1;
167  mvfr0.squareRoot = 1;
168  mvfr0.shortVectors = 1;
169  mvfr0.roundingModes = 1;
170  miscRegs[MISCREG_MVFR0] = mvfr0;
171 
172  MVFR1 mvfr1 = 0;
173  mvfr1.flushToZero = 1;
174  mvfr1.defaultNaN = 1;
175  mvfr1.advSimdLoadStore = 1;
176  mvfr1.advSimdInteger = 1;
177  mvfr1.advSimdSinglePrecision = 1;
178  mvfr1.advSimdHalfPrecision = 1;
179  mvfr1.vfpHalfPrecision = 1;
180  miscRegs[MISCREG_MVFR1] = mvfr1;
181 
182  // Reset values of PRRR and NMRR are implementation dependent
183 
184  // @todo: PRRR and NMRR in secure state?
185  miscRegs[MISCREG_PRRR_NS] =
186  (1 << 19) | // 19
187  (0 << 18) | // 18
188  (0 << 17) | // 17
189  (1 << 16) | // 16
190  (2 << 14) | // 15:14
191  (0 << 12) | // 13:12
192  (2 << 10) | // 11:10
193  (2 << 8) | // 9:8
194  (2 << 6) | // 7:6
195  (2 << 4) | // 5:4
196  (1 << 2) | // 3:2
197  0; // 1:0
198 
199  miscRegs[MISCREG_NMRR_NS] =
200  (1 << 30) | // 31:30
201  (0 << 26) | // 27:26
202  (0 << 24) | // 25:24
203  (3 << 22) | // 23:22
204  (2 << 20) | // 21:20
205  (0 << 18) | // 19:18
206  (0 << 16) | // 17:16
207  (1 << 14) | // 15:14
208  (0 << 12) | // 13:12
209  (2 << 10) | // 11:10
210  (0 << 8) | // 9:8
211  (3 << 6) | // 7:6
212  (2 << 4) | // 5:4
213  (0 << 2) | // 3:2
214  0; // 1:0
215 
216  if (FullSystem && system->highestELIs64()) {
217  // Initialize AArch64 state
218  clear64(p);
219  return;
220  }
221 
222  // Initialize AArch32 state...
223  clear32(p, sctlr_rst);
224 }
225 
226 void
227 ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
228 {
229  CPSR cpsr = 0;
230  cpsr.mode = MODE_USER;
231 
232  if (FullSystem) {
233  miscRegs[MISCREG_MVBAR] = system->resetAddr();
234  }
235 
236  miscRegs[MISCREG_CPSR] = cpsr;
237  updateRegMap(cpsr);
238 
239  SCTLR sctlr = 0;
240  sctlr.te = (bool) sctlr_rst.te;
241  sctlr.nmfi = (bool) sctlr_rst.nmfi;
242  sctlr.v = (bool) sctlr_rst.v;
243  sctlr.u = 1;
244  sctlr.xp = 1;
245  sctlr.rao2 = 1;
246  sctlr.rao3 = 1;
247  sctlr.rao4 = 0xf; // SCTLR[6:3]
248  sctlr.uci = 1;
249  sctlr.dze = 1;
250  miscRegs[MISCREG_SCTLR_NS] = sctlr;
251  miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
252  miscRegs[MISCREG_HCPTR] = 0;
253 
254  miscRegs[MISCREG_CPACR] = 0;
255 
256  miscRegs[MISCREG_FPSID] = p.fpsid;
257 
258  if (release->has(ArmExtension::LPAE)) {
259  TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
260  ttbcr.eae = 0;
261  miscRegs[MISCREG_TTBCR_NS] = ttbcr;
262  // Enforce consistency with system-level settings
263  miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
264  }
265 
266  if (release->has(ArmExtension::SECURITY)) {
267  miscRegs[MISCREG_SCTLR_S] = sctlr;
268  miscRegs[MISCREG_SCR] = 0;
269  miscRegs[MISCREG_VBAR_S] = 0;
270  } else {
271  // we're always non-secure
272  miscRegs[MISCREG_SCR] = 1;
273  }
274 
275  //XXX We need to initialize the rest of the state.
276 }
277 
278 void
279 ISA::clear64(const ArmISAParams &p)
280 {
281  CPSR cpsr = 0;
282  Addr rvbar = system->resetAddr();
283  switch (system->highestEL()) {
284  // Set initial EL to highest implemented EL using associated stack
285  // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
286  // value
287  case EL3:
288  cpsr.mode = MODE_EL3H;
289  miscRegs[MISCREG_RVBAR_EL3] = rvbar;
290  break;
291  case EL2:
292  cpsr.mode = MODE_EL2H;
293  miscRegs[MISCREG_RVBAR_EL2] = rvbar;
294  break;
295  case EL1:
296  cpsr.mode = MODE_EL1H;
297  miscRegs[MISCREG_RVBAR_EL1] = rvbar;
298  break;
299  default:
300  panic("Invalid highest implemented exception level");
301  break;
302  }
303 
304  // Initialize rest of CPSR
305  cpsr.daif = 0xf; // Mask all interrupts
306  cpsr.ss = 0;
307  cpsr.il = 0;
308  miscRegs[MISCREG_CPSR] = cpsr;
309  updateRegMap(cpsr);
310 
311  // Initialize other control registers
312  miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
313  if (release->has(ArmExtension::SECURITY)) {
314  miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
315  miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
316  } else if (release->has(ArmExtension::VIRTUALIZATION)) {
317  // also MISCREG_SCTLR_EL2 (by mapping)
318  miscRegs[MISCREG_HSCTLR] = 0x30c50830;
319  } else {
320  // also MISCREG_SCTLR_EL1 (by mapping)
321  miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
322  // Always non-secure
323  miscRegs[MISCREG_SCR_EL3] = 1;
324  }
325 }
326 
327 void
328 ISA::initID32(const ArmISAParams &p)
329 {
330  // Initialize configurable default values
331 
332  uint32_t midr;
333  if (p.midr != 0x0)
334  midr = p.midr;
335  else if (highestELIs64)
336  // Cortex-A57 TRM r0p0 MIDR
337  midr = 0x410fd070;
338  else
339  // Cortex-A15 TRM r0p0 MIDR
340  midr = 0x410fc0f0;
341 
342  miscRegs[MISCREG_MIDR] = midr;
343  miscRegs[MISCREG_MIDR_EL1] = midr;
344  miscRegs[MISCREG_VPIDR] = midr;
345 
346  miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
347  miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
348  miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
349  miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
350  miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
351  miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
352  miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
353 
354  miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
355  miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
356  miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
357  miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
358  miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
359 
361  // Crypto
362  miscRegs[MISCREG_ID_ISAR5] = insertBits(
363  miscRegs[MISCREG_ID_ISAR5], 19, 4,
364  release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
365  // RDM
366  miscRegs[MISCREG_ID_ISAR5] = insertBits(
367  miscRegs[MISCREG_ID_ISAR5], 27, 24,
368  release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
369  // FCMA
370  miscRegs[MISCREG_ID_ISAR5] = insertBits(
371  miscRegs[MISCREG_ID_ISAR5], 31, 28,
372  release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
373 
375  miscRegs[MISCREG_ID_ISAR6] = insertBits(
376  miscRegs[MISCREG_ID_ISAR6], 3, 0,
377  release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
378 }
379 
380 void
381 ISA::initID64(const ArmISAParams &p)
382 {
383  // Initialize configurable id registers
384  miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
385  miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
386  miscRegs[MISCREG_ID_AA64DFR0_EL1] =
387  (p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
388  (p.pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
389 
390  miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
391  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1;
392  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1;
393  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1;
394  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
395  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
396 
397  miscRegs[MISCREG_ID_DFR0_EL1] =
398  (p.pmu ? 0x03000000ULL : 0); // Enable PMUv3
399 
400  miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
401 
402  // SVE
403  miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
404  if (release->has(ArmExtension::SECURITY)) {
405  miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
406  } else if (release->has(ArmExtension::VIRTUALIZATION)) {
407  miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
408  } else {
409  miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
410  }
411 
412  // Enforce consistency with system-level settings...
413 
414  // EL3
415  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
416  miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
417  release->has(ArmExtension::SECURITY) ? 0x2 : 0x0);
418  // EL2
419  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
420  miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
421  release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0);
422  // SVE
423  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
424  miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
425  release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0);
426  // SecEL2
427  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
428  miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
429  release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0);
430 
431  // Large ASID support
432  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
433  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
434  haveLargeAsid64 ? 0x2 : 0x0);
435  // Physical address size
436  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
437  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
438  encodePhysAddrRange64(physAddrRange));
439 
441  // Crypto
442  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
443  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
444  release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
445  // LSE
446  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
447  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
448  release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0);
449  // RDM
450  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
451  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 31, 28,
452  release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
453 
455  // PAuth, APA
456  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
457  miscRegs[MISCREG_ID_AA64ISAR1_EL1], 7, 4,
458  release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
459  // JSCVT
460  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
461  miscRegs[MISCREG_ID_AA64ISAR1_EL1], 15, 12,
462  release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
463  // FCMA
464  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
465  miscRegs[MISCREG_ID_AA64ISAR1_EL1], 19, 16,
466  release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
467  // PAuth, GPA
468  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
469  miscRegs[MISCREG_ID_AA64ISAR1_EL1], 27, 24,
470  release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
471 
473  // VMID16
474  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
475  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 7, 4,
476  release->has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0);
477  // VHE
478  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
479  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
480  release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0);
481  // HPDS
482  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
483  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 15, 12,
484  release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0);
485  // PAN
486  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
487  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
488  release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);
489 
491  // UAO
492  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
493  miscRegs[MISCREG_ID_AA64MMFR2_EL1], 7, 4,
494  release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0);
495  // LVA
496  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
497  miscRegs[MISCREG_ID_AA64MMFR2_EL1], 19, 16,
498  release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0);
499 
500 
501  // TME
502  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
503  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,
504  release->has(ArmExtension::TME) ? 0x1 : 0x0);
505 }
506 
507 void
508 ISA::startup()
509 {
510  BaseISA::startup();
511 
512  if (tc) {
513  setupThreadContext();
514 
515  if (release->has(ArmExtension::TME)) {
516  std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
517  tc->setHtmCheckpointPtr(std::move(cpt));
518  }
519  }
520 
521  afterStartup = true;
522 }
523 
524 void
525 ISA::setupThreadContext()
526 {
527  pmu->setThreadContext(tc);
528 
529  if (!system)
530  return;
531 
532  selfDebug->init(tc);
533 
534  Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
535  if (!gicv3)
536  return;
537 
538  if (!gicv3CpuInterface)
539  gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
540 
541  gicv3CpuInterface->setISA(this);
542  gicv3CpuInterface->setThreadContext(tc);
543 }
544 
545 void
546 ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
547 {
548  tc = new_tc;
549  setupThreadContext();
550 }
551 
552 void
553 ISA::copyRegsFrom(ThreadContext *src)
554 {
555  for (int i = 0; i < NUM_INTREGS; i++)
556  tc->setIntRegFlat(i, src->readIntRegFlat(i));
557 
558  for (int i = 0; i < NUM_CCREGS; i++)
559  tc->setCCReg(i, src->readCCReg(i));
560 
561  for (int i = 0; i < NUM_MISCREGS; i++)
562  tc->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
563 
564  for (int i = 0; i < NumVecRegs; i++)
565  tc->setVecRegFlat(i, src->readVecRegFlat(i));
566 
567  for (int i = 0; i < NumVecRegs; i++) {
568  for (int e = 0; e < NumVecElemPerVecReg; e++) {
569  tc->setVecElemFlat(i, e, src->readVecElemFlat(i, e));
570  }
571  }
572 
573  // setMiscReg "with effect" will set the misc register mapping correctly.
574  // e.g. updateRegMap(val)
575  tc->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
576 
577  // Copy over the PC State
578  tc->pcState(src->pcState());
579 
580  // Invalidate the tlb misc register cache
581  static_cast<MMU *>(tc->getMMUPtr())->invalidateMiscReg();
582 }
583 
584 RegVal
585 ISA::readMiscRegNoEffect(int misc_reg) const
586 {
587  assert(misc_reg < NUM_MISCREGS);
588 
589  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
590  const auto &map = getMiscIndices(misc_reg);
591  int lower = map.first, upper = map.second;
592  // NB!: apply architectural masks according to desired register,
593  // despite possibly getting value from different (mapped) register.
594  auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
595  |(miscRegs[upper] << 32));
596  if (val & reg.res0()) {
597  DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
598  miscRegName[misc_reg], val & reg.res0());
599  }
600  if ((val & reg.res1()) != reg.res1()) {
601  DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
602  miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
603  }
604  return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
605 }
606 
607 
608 RegVal
609 ISA::readMiscReg(int misc_reg)
610 {
611  CPSR cpsr = 0;
612  SCR scr = 0;
613 
614  if (misc_reg == MISCREG_CPSR) {
615  cpsr = miscRegs[misc_reg];
616  auto pc = tc->pcState().as<PCState>();
617  cpsr.j = pc.jazelle() ? 1 : 0;
618  cpsr.t = pc.thumb() ? 1 : 0;
619  return cpsr;
620  }
621 
622 #ifndef NDEBUG
623  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
624  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
625  warn("Unimplemented system register %s read.\n",
626  miscRegName[misc_reg]);
627  else
628  panic("Unimplemented system register %s read.\n",
629  miscRegName[misc_reg]);
630  }
631 #endif
632  misc_reg = redirectRegVHE(misc_reg);
633 
634  switch (unflattenMiscReg(misc_reg)) {
635  case MISCREG_HCR:
636  case MISCREG_HCR2:
637  if (!release->has(ArmExtension::VIRTUALIZATION))
638  return 0;
639  break;
640  case MISCREG_CPACR:
641  {
642  const uint32_t ones = (uint32_t)(-1);
643  CPACR cpacrMask = 0;
644  // Only cp10, cp11, and ase are implemented, nothing else should
645  // be readable? (straight copy from the write code)
646  cpacrMask.cp10 = ones;
647  cpacrMask.cp11 = ones;
648  cpacrMask.asedis = ones;
649 
650  // Security Extensions may limit the readability of CPACR
651  if (release->has(ArmExtension::SECURITY)) {
652  scr = readMiscRegNoEffect(MISCREG_SCR);
653  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
654  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
655  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
656  // NB: Skipping the full loop, here
657  if (!nsacr.cp10) cpacrMask.cp10 = 0;
658  if (!nsacr.cp11) cpacrMask.cp11 = 0;
659  }
660  }
661  RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
662  val &= cpacrMask;
663  DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
664  miscRegName[misc_reg], val);
665  return val;
666  }
667  case MISCREG_MPIDR:
668  case MISCREG_MPIDR_EL1:
669  return readMPIDR(system, tc);
670  case MISCREG_VMPIDR:
671  case MISCREG_VMPIDR_EL2:
672  // top bit defined as RES1
673  return readMiscRegNoEffect(misc_reg) | 0x80000000;
674  case MISCREG_ID_AFR0: // not implemented, so alias MIDR
675  case MISCREG_REVIDR: // not implemented, so alias MIDR
676  case MISCREG_MIDR:
677  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
678  scr = readMiscRegNoEffect(MISCREG_SCR);
679  if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
680  return readMiscRegNoEffect(misc_reg);
681  } else {
682  return readMiscRegNoEffect(MISCREG_VPIDR);
683  }
684  break;
685  case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
686  case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
687  case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
688  case MISCREG_AIDR: // AUX ID set to 0
689  case MISCREG_TCMTR: // No TCM's
690  return 0;
691 
692  case MISCREG_CLIDR:
693  warn_once("The clidr register always reports 0 caches.\n");
694  warn_once("clidr LoUIS field of 0b001 to match current "
695  "ARM implementations.\n");
696  return 0x00200000;
697  case MISCREG_CCSIDR:
698  warn_once("The ccsidr register isn't implemented and "
699  "always reads as 0.\n");
700  break;
701  case MISCREG_CTR: // AArch32, ARMv7, top bit set
702  case MISCREG_CTR_EL0: // AArch64
703  {
704  //all caches have the same line size in gem5
705  //4 byte words in ARM
706  unsigned lineSizeWords =
707  tc->getSystemPtr()->cacheLineSize() / 4;
708  unsigned log2LineSizeWords = 0;
709 
710  while (lineSizeWords >>= 1) {
711  ++log2LineSizeWords;
712  }
713 
714  CTR ctr = 0;
715  //log2 of minimun i-cache line size (words)
716  ctr.iCacheLineSize = log2LineSizeWords;
717  //b11 - gem5 uses pipt
718  ctr.l1IndexPolicy = 0x3;
719  //log2 of minimum d-cache line size (words)
720  ctr.dCacheLineSize = log2LineSizeWords;
721  //log2 of max reservation size (words)
722  ctr.erg = log2LineSizeWords;
723  //log2 of max writeback size (words)
724  ctr.cwg = log2LineSizeWords;
725  //b100 - gem5 format is ARMv7
726  ctr.format = 0x4;
727 
728  return ctr;
729  }
730  case MISCREG_ACTLR:
731  warn("Not doing anything for miscreg ACTLR\n");
732  break;
733 
734  case MISCREG_PMXEVTYPER_PMCCFILTR:
735  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
736  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
737  case MISCREG_PMCR ... MISCREG_PMOVSSET:
738  return pmu->readMiscReg(misc_reg);
739 
740  case MISCREG_CPSR_Q:
741  panic("shouldn't be reading this register seperately\n");
742  case MISCREG_FPSCR_QC:
743  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
744  case MISCREG_FPSCR_EXC:
745  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
746  case MISCREG_FPSR:
747  {
748  const uint32_t ones = (uint32_t)(-1);
749  FPSCR fpscrMask = 0;
750  fpscrMask.ioc = ones;
751  fpscrMask.dzc = ones;
752  fpscrMask.ofc = ones;
753  fpscrMask.ufc = ones;
754  fpscrMask.ixc = ones;
755  fpscrMask.idc = ones;
756  fpscrMask.qc = ones;
757  fpscrMask.v = ones;
758  fpscrMask.c = ones;
759  fpscrMask.z = ones;
760  fpscrMask.n = ones;
761  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
762  }
763  case MISCREG_FPCR:
764  {
765  const uint32_t ones = (uint32_t)(-1);
766  FPSCR fpscrMask = 0;
767  fpscrMask.len = ones;
768  fpscrMask.fz16 = ones;
769  fpscrMask.stride = ones;
770  fpscrMask.rMode = ones;
771  fpscrMask.fz = ones;
772  fpscrMask.dn = ones;
773  fpscrMask.ahp = ones;
774  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
775  }
776  case MISCREG_NZCV:
777  {
778  CPSR cpsr = 0;
779  cpsr.nz = tc->readCCReg(CCREG_NZ);
780  cpsr.c = tc->readCCReg(CCREG_C);
781  cpsr.v = tc->readCCReg(CCREG_V);
782  return cpsr;
783  }
784  case MISCREG_DAIF:
785  {
786  CPSR cpsr = 0;
787  cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
788  return cpsr;
789  }
790  case MISCREG_SP_EL0:
791  {
792  return tc->readIntReg(INTREG_SP0);
793  }
794  case MISCREG_SP_EL1:
795  {
796  return tc->readIntReg(INTREG_SP1);
797  }
798  case MISCREG_SP_EL2:
799  {
800  return tc->readIntReg(INTREG_SP2);
801  }
802  case MISCREG_SPSEL:
803  {
804  return miscRegs[MISCREG_CPSR] & 0x1;
805  }
806  case MISCREG_CURRENTEL:
807  {
808  return miscRegs[MISCREG_CPSR] & 0xc;
809  }
810  case MISCREG_PAN:
811  {
812  return miscRegs[MISCREG_CPSR] & 0x400000;
813  }
814  case MISCREG_UAO:
815  {
816  return miscRegs[MISCREG_CPSR] & 0x800000;
817  }
818  case MISCREG_L2CTLR:
819  {
820  // mostly unimplemented, just set NumCPUs field from sim and return
821  L2CTLR l2ctlr = 0;
822  // b00:1CPU to b11:4CPUs
823  l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
824  return l2ctlr;
825  }
826  case MISCREG_DBGDIDR:
827  /* For now just implement the version number.
828  * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
829  */
830  return 0x5 << 16;
831  case MISCREG_DBGDSCRint:
832  return readMiscRegNoEffect(MISCREG_DBGDSCRint);
833  case MISCREG_ISR:
834  {
835  auto ic = dynamic_cast<ArmISA::Interrupts *>(
836  tc->getCpuPtr()->getInterruptController(tc->threadId()));
837  return ic->getISR(
838  readMiscRegNoEffect(MISCREG_HCR),
839  readMiscRegNoEffect(MISCREG_CPSR),
840  readMiscRegNoEffect(MISCREG_SCR));
841  }
842  case MISCREG_ISR_EL1:
843  {
844  auto ic = dynamic_cast<ArmISA::Interrupts *>(
845  tc->getCpuPtr()->getInterruptController(tc->threadId()));
846  return ic->getISR(
847  readMiscRegNoEffect(MISCREG_HCR_EL2),
848  readMiscRegNoEffect(MISCREG_CPSR),
849  readMiscRegNoEffect(MISCREG_SCR_EL3));
850  }
851  case MISCREG_DCZID_EL0:
852  return 0x04; // DC ZVA clear 64-byte chunks
853  case MISCREG_HCPTR:
854  {
855  RegVal val = readMiscRegNoEffect(misc_reg);
856  // The trap bit associated with CP14 is defined as RAZ
857  val &= ~(1 << 14);
858  // If a CP bit in NSACR is 0 then the corresponding bit in
859  // HCPTR is RAO/WI
860  bool secure_lookup = release->has(ArmExtension::SECURITY) &&
861  isSecure(tc);
862  if (!secure_lookup) {
863  RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
864  val |= (mask ^ 0x7FFF) & 0xBFFF;
865  }
866  // Set the bits for unimplemented coprocessors to RAO/WI
867  val |= 0x33FF;
868  return (val);
869  }
870  case MISCREG_HDFAR: // alias for secure DFAR
871  return readMiscRegNoEffect(MISCREG_DFAR_S);
872  case MISCREG_HIFAR: // alias for secure IFAR
873  return readMiscRegNoEffect(MISCREG_IFAR_S);
874 
875  case MISCREG_ID_PFR0:
876  // !ThumbEE | !Jazelle | Thumb | ARM
877  return 0x00000031;
878  case MISCREG_ID_PFR1:
879  { // Timer | Virti | !M Profile | TrustZone | ARMv4
880  bool have_timer = (system->getGenericTimer() != nullptr);
881  return 0x00000001 |
882  (release->has(ArmExtension::SECURITY) ?
883  0x00000010 : 0x0) |
884  (release->has(ArmExtension::VIRTUALIZATION) ?
885  0x00001000 : 0x0) |
886  (have_timer ? 0x00010000 : 0x0);
887  }
888  case MISCREG_ID_AA64PFR0_EL1:
889  return 0x0000000000000002 | // AArch{64,32} supported at EL0
890  0x0000000000000020 | // EL1
891  (release->has(ArmExtension::VIRTUALIZATION) ?
892  0x0000000000000200 : 0) | // EL2
893  (release->has(ArmExtension::SECURITY) ?
894  0x0000000000002000 : 0) | // EL3
895  (release->has(ArmExtension::FEAT_SVE) ?
896  0x0000000100000000 : 0) | // SVE
897  (release->has(ArmExtension::FEAT_SEL2) ?
898  0x0000001000000000 : 0) | // SecEL2
899  (gicv3CpuInterface ? 0x0000000001000000 : 0);
900  case MISCREG_ID_AA64PFR1_EL1:
901  return 0; // bits [63:0] RES0 (reserved for future use)
902 
903  // Generic Timer registers
904  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
905  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
906  return getGenericTimer().readMiscReg(misc_reg);
907 
908  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
909  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
910  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
911  return getGICv3CPUInterface().readMiscReg(misc_reg);
912 
913  default:
914  break;
915 
916  }
917  return readMiscRegNoEffect(misc_reg);
918 }
919 
920 void
921 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
922 {
923  assert(misc_reg < NUM_MISCREGS);
924 
925  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
926  const auto &map = getMiscIndices(misc_reg);
927  int lower = map.first, upper = map.second;
928 
929  auto v = (val & ~reg.wi()) | reg.rao();
930  if (upper > 0) {
931  miscRegs[lower] = bits(v, 31, 0);
932  miscRegs[upper] = bits(v, 63, 32);
933  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
934  miscRegName[misc_reg], misc_reg, lower, upper, v);
935  } else {
936  miscRegs[lower] = v;
937  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
938  miscRegName[misc_reg], misc_reg, lower, v);
939  }
940 }
941 
942 void
943 ISA::setMiscReg(int misc_reg, RegVal val)
944 {
945 
946  RegVal newVal = val;
947  bool secure_lookup;
948  SCR scr;
949 
950  if (misc_reg == MISCREG_CPSR) {
951  updateRegMap(val);
952 
953 
954  CPSR old_cpsr = miscRegs[MISCREG_CPSR];
955  int old_mode = old_cpsr.mode;
956  CPSR cpsr = val;
957  if (cpsr.pan != old_cpsr.pan || cpsr.il != old_cpsr.il) {
958  getMMUPtr(tc)->invalidateMiscReg();
959  }
960 
961  DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
962  miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
963  PCState pc = tc->pcState().as<PCState>();
964  pc.nextThumb(cpsr.t);
965  pc.nextJazelle(cpsr.j);
966  pc.illegalExec(cpsr.il == 1);
967  selfDebug->setDebugMask(cpsr.d == 1);
968 
969  tc->getDecoderPtr()->as<Decoder>().setSveLen(
970  (getCurSveVecLenInBits() >> 7) - 1);
971 
972  // Follow slightly different semantics if a CheckerCPU object
973  // is connected
974  CheckerCPU *checker = tc->getCheckerCpuPtr();
975  if (checker) {
976  tc->pcStateNoRecord(pc);
977  } else {
978  tc->pcState(pc);
979  }
980 
981  setMiscRegNoEffect(misc_reg, newVal);
982 
983  if (old_mode != cpsr.mode) {
984  getMMUPtr(tc)->invalidateMiscReg();
985  if (gicv3CpuInterface) {
986  // The assertion and de-assertion of IRQs and FIQs are
987  // affected by the current Exception level and Security
988  // state of the PE. As part of the Context
989  // Synchronization that occurs as the result of taking
990  // or returning from an exception, the CPU interface
991  // ensures that IRQ and FIQ are both appropriately
992  // asserted or deasserted for the Exception level and
993  // Security state that the PE is entering.
994  static_cast<Gicv3CPUInterface&>(
995  getGICv3CPUInterface()).update();
996  }
997  }
998  } else {
999 #ifndef NDEBUG
1000  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
1001  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
1002  warn("Unimplemented system register %s write with %#x.\n",
1003  miscRegName[misc_reg], val);
1004  else
1005  panic("Unimplemented system register %s write with %#x.\n",
1006  miscRegName[misc_reg], val);
1007  }
1008 #endif
1009  misc_reg = redirectRegVHE(misc_reg);
1010 
1011  switch (unflattenMiscReg(misc_reg)) {
1012  case MISCREG_CPACR:
1013  {
1014 
1015  const uint32_t ones = (uint32_t)(-1);
1016  CPACR cpacrMask = 0;
1017  // Only cp10, cp11, and ase are implemented, nothing else should
1018  // be writable
1019  cpacrMask.cp10 = ones;
1020  cpacrMask.cp11 = ones;
1021  cpacrMask.asedis = ones;
1022 
1023  // Security Extensions may limit the writability of CPACR
1024  if (release->has(ArmExtension::SECURITY)) {
1025  scr = readMiscRegNoEffect(MISCREG_SCR);
1026  CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
1027  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
1028  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
1029  // NB: Skipping the full loop, here
1030  if (!nsacr.cp10) cpacrMask.cp10 = 0;
1031  if (!nsacr.cp11) cpacrMask.cp11 = 0;
1032  }
1033  }
1034 
1035  RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
1036  newVal &= cpacrMask;
1037  newVal |= old_val & ~cpacrMask;
1038  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1039  miscRegName[misc_reg], newVal);
1040  }
1041  break;
1042  case MISCREG_CPACR_EL1:
1043  {
1044  const uint32_t ones = (uint32_t)(-1);
1045  CPACR cpacrMask = 0;
1046  cpacrMask.tta = ones;
1047  cpacrMask.fpen = ones;
1048  if (release->has(ArmExtension::FEAT_SVE)) {
1049  cpacrMask.zen = ones;
1050  }
1051  newVal &= cpacrMask;
1052  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1053  miscRegName[misc_reg], newVal);
1054  }
1055  break;
1056  case MISCREG_CPTR_EL2:
1057  {
1058  const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
1059  const uint32_t ones = (uint32_t)(-1);
1060  CPTR cptrMask = 0;
1061  cptrMask.tcpac = ones;
1062  cptrMask.tta = ones;
1063  cptrMask.tfp = ones;
1064  if (release->has(ArmExtension::FEAT_SVE)) {
1065  cptrMask.tz = ones;
1066  cptrMask.zen = hcr.e2h ? ones : 0;
1067  }
1068  cptrMask.fpen = hcr.e2h ? ones : 0;
1069  newVal &= cptrMask;
1070  cptrMask = 0;
1071  cptrMask.res1_13_12_el2 = ones;
1072  cptrMask.res1_7_0_el2 = ones;
1073  if (!release->has(ArmExtension::FEAT_SVE)) {
1074  cptrMask.res1_8_el2 = ones;
1075  }
1076  cptrMask.res1_9_el2 = ones;
1077  newVal |= cptrMask;
1078  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1079  miscRegName[misc_reg], newVal);
1080  }
1081  break;
1082  case MISCREG_CPTR_EL3:
1083  {
1084  const uint32_t ones = (uint32_t)(-1);
1085  CPTR cptrMask = 0;
1086  cptrMask.tcpac = ones;
1087  cptrMask.tta = ones;
1088  cptrMask.tfp = ones;
1089  if (release->has(ArmExtension::FEAT_SVE)) {
1090  cptrMask.ez = ones;
1091  }
1092  newVal &= cptrMask;
1093  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1094  miscRegName[misc_reg], newVal);
1095  }
1096  break;
1097  case MISCREG_CSSELR:
1098  warn_once("The csselr register isn't implemented.\n");
1099  return;
1100 
1101  case MISCREG_DC_ZVA_Xt:
1102  warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
1103  return;
1104 
1105  case MISCREG_FPSCR:
1106  {
1107  const uint32_t ones = (uint32_t)(-1);
1108  FPSCR fpscrMask = 0;
1109  fpscrMask.ioc = ones;
1110  fpscrMask.dzc = ones;
1111  fpscrMask.ofc = ones;
1112  fpscrMask.ufc = ones;
1113  fpscrMask.ixc = ones;
1114  fpscrMask.idc = ones;
1115  fpscrMask.ioe = ones;
1116  fpscrMask.dze = ones;
1117  fpscrMask.ofe = ones;
1118  fpscrMask.ufe = ones;
1119  fpscrMask.ixe = ones;
1120  fpscrMask.ide = ones;
1121  fpscrMask.len = ones;
1122  fpscrMask.fz16 = ones;
1123  fpscrMask.stride = ones;
1124  fpscrMask.rMode = ones;
1125  fpscrMask.fz = ones;
1126  fpscrMask.dn = ones;
1127  fpscrMask.ahp = ones;
1128  fpscrMask.qc = ones;
1129  fpscrMask.v = ones;
1130  fpscrMask.c = ones;
1131  fpscrMask.z = ones;
1132  fpscrMask.n = ones;
1133  newVal = (newVal & (uint32_t)fpscrMask) |
1134  (readMiscRegNoEffect(MISCREG_FPSCR) &
1135  ~(uint32_t)fpscrMask);
1136  tc->getDecoderPtr()->as<Decoder>().setContext(newVal);
1137  }
1138  break;
1139  case MISCREG_FPSR:
1140  {
1141  const uint32_t ones = (uint32_t)(-1);
1142  FPSCR fpscrMask = 0;
1143  fpscrMask.ioc = ones;
1144  fpscrMask.dzc = ones;
1145  fpscrMask.ofc = ones;
1146  fpscrMask.ufc = ones;
1147  fpscrMask.ixc = ones;
1148  fpscrMask.idc = ones;
1149  fpscrMask.qc = ones;
1150  fpscrMask.v = ones;
1151  fpscrMask.c = ones;
1152  fpscrMask.z = ones;
1153  fpscrMask.n = ones;
1154  newVal = (newVal & (uint32_t)fpscrMask) |
1155  (readMiscRegNoEffect(MISCREG_FPSCR) &
1156  ~(uint32_t)fpscrMask);
1157  misc_reg = MISCREG_FPSCR;
1158  }
1159  break;
1160  case MISCREG_FPCR:
1161  {
1162  const uint32_t ones = (uint32_t)(-1);
1163  FPSCR fpscrMask = 0;
1164  fpscrMask.len = ones;
1165  fpscrMask.fz16 = ones;
1166  fpscrMask.stride = ones;
1167  fpscrMask.rMode = ones;
1168  fpscrMask.fz = ones;
1169  fpscrMask.dn = ones;
1170  fpscrMask.ahp = ones;
1171  newVal = (newVal & (uint32_t)fpscrMask) |
1172  (readMiscRegNoEffect(MISCREG_FPSCR) &
1173  ~(uint32_t)fpscrMask);
1174  misc_reg = MISCREG_FPSCR;
1175  }
1176  break;
1177  case MISCREG_CPSR_Q:
1178  {
1179  assert(!(newVal & ~CpsrMaskQ));
1180  newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1181  misc_reg = MISCREG_CPSR;
1182  }
1183  break;
1184  case MISCREG_FPSCR_QC:
1185  {
1186  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1187  (newVal & FpscrQcMask);
1188  misc_reg = MISCREG_FPSCR;
1189  }
1190  break;
1191  case MISCREG_FPSCR_EXC:
1192  {
1193  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1194  (newVal & FpscrExcMask);
1195  misc_reg = MISCREG_FPSCR;
1196  }
1197  break;
1198  case MISCREG_FPEXC:
1199  {
1200  // vfpv3 architecture, section B.6.1 of DDI04068
1201  // bit 29 - valid only if fpexc[31] is 0
1202  const uint32_t fpexcMask = 0x60000000;
1203  newVal = (newVal & fpexcMask) |
1204  (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1205  }
1206  break;
1207  case MISCREG_HCR2:
1208  if (!release->has(ArmExtension::VIRTUALIZATION))
1209  return;
1210  break;
1211  case MISCREG_HCR:
1212  {
1213  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1214  selfDebug->setenableTDETGE((HCR)val, mdcr);
1215  if (!release->has(ArmExtension::VIRTUALIZATION))
1216  return;
1217  }
1218  break;
1219 
1220  case MISCREG_HDCR:
1221  {
1222  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1223  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1224  }
1225  break;
1226  case MISCREG_DBGOSLAR:
1227  {
1228  OSL r = tc->readMiscReg(MISCREG_DBGOSLSR);
1229  const uint32_t temp = (val == 0xC5ACCE55)? 0x1 : 0x0;
1230  selfDebug->updateOSLock((RegVal) temp);
1231  r.oslk = bits(temp,0);
1232  tc->setMiscReg(MISCREG_DBGOSLSR, r);
1233  }
1234  break;
1235  case MISCREG_DBGBCR0:
1236  selfDebug->updateDBGBCR(0, val);
1237  break;
1238  case MISCREG_DBGBCR1:
1239  selfDebug->updateDBGBCR(1, val);
1240  break;
1241  case MISCREG_DBGBCR2:
1242  selfDebug->updateDBGBCR(2, val);
1243  break;
1244  case MISCREG_DBGBCR3:
1245  selfDebug->updateDBGBCR(3, val);
1246  break;
1247  case MISCREG_DBGBCR4:
1248  selfDebug->updateDBGBCR(4, val);
1249  break;
1250  case MISCREG_DBGBCR5:
1251  selfDebug->updateDBGBCR(5, val);
1252  break;
1253  case MISCREG_DBGBCR6:
1254  selfDebug->updateDBGBCR(6, val);
1255  break;
1256  case MISCREG_DBGBCR7:
1257  selfDebug->updateDBGBCR(7, val);
1258  break;
1259  case MISCREG_DBGBCR8:
1260  selfDebug->updateDBGBCR(8, val);
1261  break;
1262  case MISCREG_DBGBCR9:
1263  selfDebug->updateDBGBCR(9, val);
1264  break;
1265  case MISCREG_DBGBCR10:
1266  selfDebug->updateDBGBCR(10, val);
1267  break;
1268  case MISCREG_DBGBCR11:
1269  selfDebug->updateDBGBCR(11, val);
1270  break;
1271  case MISCREG_DBGBCR12:
1272  selfDebug->updateDBGBCR(12, val);
1273  break;
1274  case MISCREG_DBGBCR13:
1275  selfDebug->updateDBGBCR(13, val);
1276  break;
1277  case MISCREG_DBGBCR14:
1278  selfDebug->updateDBGBCR(14, val);
1279  break;
1280  case MISCREG_DBGBCR15:
1281  selfDebug->updateDBGBCR(15, val);
1282  break;
1283  case MISCREG_DBGWCR0:
1284  selfDebug->updateDBGWCR(0, val);
1285  break;
1286  case MISCREG_DBGWCR1:
1287  selfDebug->updateDBGWCR(1, val);
1288  break;
1289  case MISCREG_DBGWCR2:
1290  selfDebug->updateDBGWCR(2, val);
1291  break;
1292  case MISCREG_DBGWCR3:
1293  selfDebug->updateDBGWCR(3, val);
1294  break;
1295  case MISCREG_DBGWCR4:
1296  selfDebug->updateDBGWCR(4, val);
1297  break;
1298  case MISCREG_DBGWCR5:
1299  selfDebug->updateDBGWCR(5, val);
1300  break;
1301  case MISCREG_DBGWCR6:
1302  selfDebug->updateDBGWCR(6, val);
1303  break;
1304  case MISCREG_DBGWCR7:
1305  selfDebug->updateDBGWCR(7, val);
1306  break;
1307  case MISCREG_DBGWCR8:
1308  selfDebug->updateDBGWCR(8, val);
1309  break;
1310  case MISCREG_DBGWCR9:
1311  selfDebug->updateDBGWCR(9, val);
1312  break;
1313  case MISCREG_DBGWCR10:
1314  selfDebug->updateDBGWCR(10, val);
1315  break;
1316  case MISCREG_DBGWCR11:
1317  selfDebug->updateDBGWCR(11, val);
1318  break;
1319  case MISCREG_DBGWCR12:
1320  selfDebug->updateDBGWCR(12, val);
1321  break;
1322  case MISCREG_DBGWCR13:
1323  selfDebug->updateDBGWCR(13, val);
1324  break;
1325  case MISCREG_DBGWCR14:
1326  selfDebug->updateDBGWCR(14, val);
1327  break;
1328  case MISCREG_DBGWCR15:
1329  selfDebug->updateDBGWCR(15, val);
1330  break;
1331 
1332  case MISCREG_MDCR_EL2:
1333  {
1334  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1335  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1336  }
1337  break;
1338  case MISCREG_SDCR:
1339  case MISCREG_MDCR_EL3:
1340  {
1341  selfDebug->setbSDD(val);
1342  }
1343  break;
1344  case MISCREG_DBGDSCRext:
1345  {
1346  selfDebug->setMDBGen(val);
1347  DBGDS32 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1348  DBGDS32 v = val;
1349  r.moe = v.moe;
1350  r.udccdis = v.udccdis;
1351  r.mdbgen = v.mdbgen;
1352  tc->setMiscReg(MISCREG_DBGDSCRint, r);
1353  r = tc->readMiscReg(MISCREG_DBGDSCRint);
1354  }
1355 
1356  break;
1357  case MISCREG_MDSCR_EL1:
1358  {
1359  selfDebug->setMDSCRvals(val);
1360  }
1361  break;
1362 
1363  case MISCREG_OSLAR_EL1:
1364  {
1365  selfDebug->updateOSLock(val);
1366  OSL r = tc->readMiscReg(MISCREG_OSLSR_EL1);
1367  r.oslk = bits(val, 0);
1368  r.oslm_3 = 1;
1369  tc->setMiscReg(MISCREG_OSLSR_EL1, r);
1370  }
1371  break;
1372 
1373  case MISCREG_DBGBCR0_EL1:
1374  selfDebug->updateDBGBCR(0, val);
1375  break;
1376  case MISCREG_DBGBCR1_EL1:
1377  selfDebug->updateDBGBCR(1, val);
1378  break;
1379  case MISCREG_DBGBCR2_EL1:
1380  selfDebug->updateDBGBCR(2, val);
1381  break;
1382  case MISCREG_DBGBCR3_EL1:
1383  selfDebug->updateDBGBCR(3, val);
1384  break;
1385  case MISCREG_DBGBCR4_EL1:
1386  selfDebug->updateDBGBCR(4, val);
1387  break;
1388  case MISCREG_DBGBCR5_EL1:
1389  selfDebug->updateDBGBCR(5, val);
1390  break;
1391  case MISCREG_DBGBCR6_EL1:
1392  selfDebug->updateDBGBCR(6, val);
1393  break;
1394  case MISCREG_DBGBCR7_EL1:
1395  selfDebug->updateDBGBCR(7, val);
1396  break;
1397  case MISCREG_DBGBCR8_EL1:
1398  selfDebug->updateDBGBCR(8, val);
1399  break;
1400  case MISCREG_DBGBCR9_EL1:
1401  selfDebug->updateDBGBCR(9, val);
1402  break;
1403  case MISCREG_DBGBCR10_EL1:
1404  selfDebug->updateDBGBCR(10, val);
1405  break;
1406  case MISCREG_DBGBCR11_EL1:
1407  selfDebug->updateDBGBCR(11, val);
1408  break;
1409  case MISCREG_DBGBCR12_EL1:
1410  selfDebug->updateDBGBCR(12, val);
1411  break;
1412  case MISCREG_DBGBCR13_EL1:
1413  selfDebug->updateDBGBCR(13, val);
1414  break;
1415  case MISCREG_DBGBCR14_EL1:
1416  selfDebug->updateDBGBCR(14, val);
1417  break;
1418  case MISCREG_DBGBCR15_EL1:
1419  selfDebug->updateDBGBCR(15, val);
1420  break;
1421  case MISCREG_DBGWCR0_EL1:
1422  selfDebug->updateDBGWCR(0, val);
1423  break;
1424  case MISCREG_DBGWCR1_EL1:
1425  selfDebug->updateDBGWCR(1, val);
1426  break;
1427  case MISCREG_DBGWCR2_EL1:
1428  selfDebug->updateDBGWCR(2, val);
1429  break;
1430  case MISCREG_DBGWCR3_EL1:
1431  selfDebug->updateDBGWCR(3, val);
1432  break;
1433  case MISCREG_DBGWCR4_EL1:
1434  selfDebug->updateDBGWCR(4, val);
1435  break;
1436  case MISCREG_DBGWCR5_EL1:
1437  selfDebug->updateDBGWCR(5, val);
1438  break;
1439  case MISCREG_DBGWCR6_EL1:
1440  selfDebug->updateDBGWCR(6, val);
1441  break;
1442  case MISCREG_DBGWCR7_EL1:
1443  selfDebug->updateDBGWCR(7, val);
1444  break;
1445  case MISCREG_DBGWCR8_EL1:
1446  selfDebug->updateDBGWCR(8, val);
1447  break;
1448  case MISCREG_DBGWCR9_EL1:
1449  selfDebug->updateDBGWCR(9, val);
1450  break;
1451  case MISCREG_DBGWCR10_EL1:
1452  selfDebug->updateDBGWCR(10, val);
1453  break;
1454  case MISCREG_DBGWCR11_EL1:
1455  selfDebug->updateDBGWCR(11, val);
1456  break;
1457  case MISCREG_DBGWCR12_EL1:
1458  selfDebug->updateDBGWCR(12, val);
1459  break;
1460  case MISCREG_DBGWCR13_EL1:
1461  selfDebug->updateDBGWCR(13, val);
1462  break;
1463  case MISCREG_DBGWCR14_EL1:
1464  selfDebug->updateDBGWCR(14, val);
1465  break;
1466  case MISCREG_DBGWCR15_EL1:
1467  selfDebug->updateDBGWCR(15, val);
1468  break;
1469  case MISCREG_IFSR:
1470  {
1471  // ARM ARM (ARM DDI 0406C.b) B4.1.96
1472  const uint32_t ifsrMask =
1473  mask(31, 13) | mask(11, 11) | mask(8, 6);
1474  newVal = newVal & ~ifsrMask;
1475  }
1476  break;
1477  case MISCREG_DFSR:
1478  {
1479  // ARM ARM (ARM DDI 0406C.b) B4.1.52
1480  const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1481  newVal = newVal & ~dfsrMask;
1482  }
1483  break;
1484  case MISCREG_AMAIR0:
1485  case MISCREG_AMAIR1:
1486  {
1487  // ARM ARM (ARM DDI 0406C.b) B4.1.5
1488  // Valid only with LPAE
1489  if (!release->has(ArmExtension::LPAE))
1490  return;
1491  DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1492  }
1493  break;
1494  case MISCREG_SCR:
1495  getMMUPtr(tc)->invalidateMiscReg();
1496  break;
1497  case MISCREG_SCTLR:
1498  {
1499  DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1500  scr = readMiscRegNoEffect(MISCREG_SCR);
1501 
1502  MiscRegIndex sctlr_idx;
1503  if (release->has(ArmExtension::SECURITY) &&
1504  !highestELIs64 && !scr.ns) {
1505  sctlr_idx = MISCREG_SCTLR_S;
1506  } else {
1507  sctlr_idx = MISCREG_SCTLR_NS;
1508  }
1509 
1510  SCTLR sctlr = miscRegs[sctlr_idx];
1511  SCTLR new_sctlr = newVal;
1512  new_sctlr.nmfi = ((bool)sctlr.nmfi) &&
1513  !release->has(ArmExtension::VIRTUALIZATION);
1514  miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1515  getMMUPtr(tc)->invalidateMiscReg();
1516  }
1517  case MISCREG_MIDR:
1518  case MISCREG_ID_PFR0:
1519  case MISCREG_ID_PFR1:
1520  case MISCREG_ID_DFR0:
1521  case MISCREG_ID_MMFR0:
1522  case MISCREG_ID_MMFR1:
1523  case MISCREG_ID_MMFR2:
1524  case MISCREG_ID_MMFR3:
1525  case MISCREG_ID_MMFR4:
1526  case MISCREG_ID_ISAR0:
1527  case MISCREG_ID_ISAR1:
1528  case MISCREG_ID_ISAR2:
1529  case MISCREG_ID_ISAR3:
1530  case MISCREG_ID_ISAR4:
1531  case MISCREG_ID_ISAR5:
1532 
1533  case MISCREG_MPIDR:
1534  case MISCREG_FPSID:
1535  case MISCREG_TLBTR:
1536  case MISCREG_MVFR0:
1537  case MISCREG_MVFR1:
1538 
1539  case MISCREG_ID_AA64AFR0_EL1:
1540  case MISCREG_ID_AA64AFR1_EL1:
1541  case MISCREG_ID_AA64DFR0_EL1:
1542  case MISCREG_ID_AA64DFR1_EL1:
1543  case MISCREG_ID_AA64ISAR0_EL1:
1544  case MISCREG_ID_AA64ISAR1_EL1:
1545  case MISCREG_ID_AA64MMFR0_EL1:
1546  case MISCREG_ID_AA64MMFR1_EL1:
1547  case MISCREG_ID_AA64MMFR2_EL1:
1548  case MISCREG_ID_AA64PFR0_EL1:
1549  case MISCREG_ID_AA64PFR1_EL1:
1550  // ID registers are constants.
1551  return;
1552 
1553  // TLB Invalidate All
1554  case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1555  {
1556  assert32();
1557  scr = readMiscReg(MISCREG_SCR);
1558 
1559  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1560  TLBIALL tlbiOp(EL1, secure);
1561  tlbiOp(tc);
1562  return;
1563  }
1564  // TLB Invalidate All, Inner Shareable
1565  case MISCREG_TLBIALLIS:
1566  {
1567  assert32();
1568  scr = readMiscReg(MISCREG_SCR);
1569 
1570  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1571  TLBIALL tlbiOp(EL1, secure);
1572  tlbiOp.broadcast(tc);
1573  return;
1574  }
1575  // Instruction TLB Invalidate All
1576  case MISCREG_ITLBIALL:
1577  {
1578  assert32();
1579  scr = readMiscReg(MISCREG_SCR);
1580 
1581  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1582  ITLBIALL tlbiOp(EL1, secure);
1583  tlbiOp(tc);
1584  return;
1585  }
1586  // Data TLB Invalidate All
1587  case MISCREG_DTLBIALL:
1588  {
1589  assert32();
1590  scr = readMiscReg(MISCREG_SCR);
1591 
1592  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1593  DTLBIALL tlbiOp(EL1, secure);
1594  tlbiOp(tc);
1595  return;
1596  }
1597  // TLB Invalidate by VA
1598  // mcr tlbimval(is) is invalidating all matching entries
1599  // regardless of the level of lookup, since in gem5 we cache
1600  // in the tlb the last level of lookup only.
1601  case MISCREG_TLBIMVA:
1602  case MISCREG_TLBIMVAL:
1603  {
1604  assert32();
1605  scr = readMiscReg(MISCREG_SCR);
1606 
1607  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1608  TLBIMVA tlbiOp(EL1,
1609  secure,
1610  mbits(newVal, 31, 12),
1611  bits(newVal, 7,0));
1612 
1613  tlbiOp(tc);
1614  return;
1615  }
1616  // TLB Invalidate by VA, Inner Shareable
1617  case MISCREG_TLBIMVAIS:
1618  case MISCREG_TLBIMVALIS:
1619  {
1620  assert32();
1621  scr = readMiscReg(MISCREG_SCR);
1622 
1623  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1624  TLBIMVA tlbiOp(EL1,
1625  secure,
1626  mbits(newVal, 31, 12),
1627  bits(newVal, 7,0));
1628 
1629  tlbiOp.broadcast(tc);
1630  return;
1631  }
1632  // TLB Invalidate by ASID match
1633  case MISCREG_TLBIASID:
1634  {
1635  assert32();
1636  scr = readMiscReg(MISCREG_SCR);
1637 
1638  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1639  TLBIASID tlbiOp(EL1,
1640  secure,
1641  bits(newVal, 7,0));
1642 
1643  tlbiOp(tc);
1644  return;
1645  }
1646  // TLB Invalidate by ASID match, Inner Shareable
1647  case MISCREG_TLBIASIDIS:
1648  {
1649  assert32();
1650  scr = readMiscReg(MISCREG_SCR);
1651 
1652  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1653  TLBIASID tlbiOp(EL1,
1654  secure,
1655  bits(newVal, 7,0));
1656 
1657  tlbiOp.broadcast(tc);
1658  return;
1659  }
1660  // mcr tlbimvaal(is) is invalidating all matching entries
1661  // regardless of the level of lookup, since in gem5 we cache
1662  // in the tlb the last level of lookup only.
1663  // TLB Invalidate by VA, All ASID
1664  case MISCREG_TLBIMVAA:
1665  case MISCREG_TLBIMVAAL:
1666  {
1667  assert32();
1668  scr = readMiscReg(MISCREG_SCR);
1669 
1670  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1671  TLBIMVAA tlbiOp(EL1, secure,
1672  mbits(newVal, 31,12));
1673 
1674  tlbiOp(tc);
1675  return;
1676  }
1677  // TLB Invalidate by VA, All ASID, Inner Shareable
1678  case MISCREG_TLBIMVAAIS:
1679  case MISCREG_TLBIMVAALIS:
1680  {
1681  assert32();
1682  scr = readMiscReg(MISCREG_SCR);
1683 
1684  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1685  TLBIMVAA tlbiOp(EL1, secure,
1686  mbits(newVal, 31,12));
1687 
1688  tlbiOp.broadcast(tc);
1689  return;
1690  }
1691  // mcr tlbimvalh(is) is invalidating all matching entries
1692  // regardless of the level of lookup, since in gem5 we cache
1693  // in the tlb the last level of lookup only.
1694  // TLB Invalidate by VA, Hyp mode
1695  case MISCREG_TLBIMVAH:
1696  case MISCREG_TLBIMVALH:
1697  {
1698  assert32();
1699  scr = readMiscReg(MISCREG_SCR);
1700 
1701  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1702  TLBIMVAA tlbiOp(EL2, secure,
1703  mbits(newVal, 31,12));
1704 
1705  tlbiOp(tc);
1706  return;
1707  }
1708  // TLB Invalidate by VA, Hyp mode, Inner Shareable
1709  case MISCREG_TLBIMVAHIS:
1710  case MISCREG_TLBIMVALHIS:
1711  {
1712  assert32();
1713  scr = readMiscReg(MISCREG_SCR);
1714 
1715  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1716  TLBIMVAA tlbiOp(EL2, secure,
1717  mbits(newVal, 31,12));
1718 
1719  tlbiOp.broadcast(tc);
1720  return;
1721  }
1722  // mcr tlbiipas2l(is) is invalidating all matching entries
1723  // regardless of the level of lookup, since in gem5 we cache
1724  // in the tlb the last level of lookup only.
1725  // TLB Invalidate by Intermediate Physical Address, Stage 2
1726  case MISCREG_TLBIIPAS2:
1727  case MISCREG_TLBIIPAS2L:
1728  {
1729  assert32();
1730  scr = readMiscReg(MISCREG_SCR);
1731 
1732  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1733  TLBIIPA tlbiOp(EL1,
1734  secure,
1735  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1736 
1737  tlbiOp(tc);
1738  return;
1739  }
1740  // TLB Invalidate by Intermediate Physical Address, Stage 2,
1741  // Inner Shareable
1742  case MISCREG_TLBIIPAS2IS:
1743  case MISCREG_TLBIIPAS2LIS:
1744  {
1745  assert32();
1746  scr = readMiscReg(MISCREG_SCR);
1747 
1748  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1749  TLBIIPA tlbiOp(EL1,
1750  secure,
1751  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1752 
1753  tlbiOp.broadcast(tc);
1754  return;
1755  }
1756  // Instruction TLB Invalidate by VA
1757  case MISCREG_ITLBIMVA:
1758  {
1759  assert32();
1760  scr = readMiscReg(MISCREG_SCR);
1761 
1762  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1763  ITLBIMVA tlbiOp(EL1,
1764  secure,
1765  mbits(newVal, 31, 12),
1766  bits(newVal, 7,0));
1767 
1768  tlbiOp(tc);
1769  return;
1770  }
1771  // Data TLB Invalidate by VA
1772  case MISCREG_DTLBIMVA:
1773  {
1774  assert32();
1775  scr = readMiscReg(MISCREG_SCR);
1776 
1777  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1778  DTLBIMVA tlbiOp(EL1,
1779  secure,
1780  mbits(newVal, 31, 12),
1781  bits(newVal, 7,0));
1782 
1783  tlbiOp(tc);
1784  return;
1785  }
1786  // Instruction TLB Invalidate by ASID match
1787  case MISCREG_ITLBIASID:
1788  {
1789  assert32();
1790  scr = readMiscReg(MISCREG_SCR);
1791 
1792  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1793  ITLBIASID tlbiOp(EL1,
1794  secure,
1795  bits(newVal, 7,0));
1796 
1797  tlbiOp(tc);
1798  return;
1799  }
1800  // Data TLB Invalidate by ASID match
1801  case MISCREG_DTLBIASID:
1802  {
1803  assert32();
1804  scr = readMiscReg(MISCREG_SCR);
1805 
1806  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1807  DTLBIASID tlbiOp(EL1,
1808  secure,
1809  bits(newVal, 7,0));
1810 
1811  tlbiOp(tc);
1812  return;
1813  }
1814  // TLB Invalidate All, Non-Secure Non-Hyp
1815  case MISCREG_TLBIALLNSNH:
1816  {
1817  assert32();
1818 
1819  TLBIALLN tlbiOp(EL1);
1820  tlbiOp(tc);
1821  return;
1822  }
1823  // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1824  case MISCREG_TLBIALLNSNHIS:
1825  {
1826  assert32();
1827 
1828  TLBIALLN tlbiOp(EL1);
1829  tlbiOp.broadcast(tc);
1830  return;
1831  }
1832  // TLB Invalidate All, Hyp mode
1833  case MISCREG_TLBIALLH:
1834  {
1835  assert32();
1836 
1837  TLBIALLN tlbiOp(EL2);
1838  tlbiOp(tc);
1839  return;
1840  }
1841  // TLB Invalidate All, Hyp mode, Inner Shareable
1842  case MISCREG_TLBIALLHIS:
1843  {
1844  assert32();
1845 
1846  TLBIALLN tlbiOp(EL2);
1847  tlbiOp.broadcast(tc);
1848  return;
1849  }
1850  // AArch64 TLB Invalidate All, EL3
1851  case MISCREG_TLBI_ALLE3:
1852  {
1853  assert64();
1854 
1855  TLBIALLEL tlbiOp(EL3, true);
1856  tlbiOp(tc);
1857  return;
1858  }
1859  // AArch64 TLB Invalidate All, EL3, Inner Shareable
1860  case MISCREG_TLBI_ALLE3IS:
1861  {
1862  assert64();
1863 
1864  TLBIALLEL tlbiOp(EL3, true);
1865  tlbiOp.broadcast(tc);
1866  return;
1867  }
1868  // AArch64 TLB Invalidate All, EL2
1869  case MISCREG_TLBI_ALLE2:
1870  {
1871  assert64();
1872  scr = readMiscReg(MISCREG_SCR);
1873 
1874  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1875  TLBIALLEL tlbiOp(EL2, secure);
1876  tlbiOp(tc);
1877  return;
1878  }
1879  // AArch64 TLB Invalidate All, EL2, Inner Shareable
1880  case MISCREG_TLBI_ALLE2IS:
1881  {
1882  assert64();
1883  scr = readMiscReg(MISCREG_SCR);
1884 
1885  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1886  TLBIALLEL tlbiOp(EL2, secure);
1887  tlbiOp.broadcast(tc);
1888  return;
1889  }
1890  // AArch64 TLB Invalidate All, EL1
1891  case MISCREG_TLBI_ALLE1:
1892  {
1893  assert64();
1894  scr = readMiscReg(MISCREG_SCR);
1895 
1896  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1897  TLBIALLEL tlbiOp(EL1, secure);
1898  tlbiOp(tc);
1899  return;
1900  }
1901  // AArch64 TLB Invalidate All, EL1, Inner Shareable
1902  case MISCREG_TLBI_ALLE1IS:
1903  {
1904  assert64();
1905  scr = readMiscReg(MISCREG_SCR);
1906 
1907  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1908  TLBIALLEL tlbiOp(EL1, secure);
1909  tlbiOp.broadcast(tc);
1910  return;
1911  }
1912  case MISCREG_TLBI_VMALLS12E1:
1913  {
1914  assert64();
1915  scr = readMiscReg(MISCREG_SCR);
1916 
1917  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1918  TLBIVMALL tlbiOp(EL1, secure, true);
1919  tlbiOp(tc);
1920  return;
1921  }
1922  case MISCREG_TLBI_VMALLE1:
1923  {
1924  assert64();
1925  scr = readMiscReg(MISCREG_SCR);
1926 
1927  ExceptionLevel target_el = EL1;
1928  if (EL2Enabled(tc)) {
1929  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1930  if (hcr.tge && hcr.e2h) {
1931  target_el = EL2;
1932  }
1933  }
1934 
1935  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1936  TLBIVMALL tlbiOp(target_el, secure, false);
1937  tlbiOp(tc);
1938  return;
1939  }
1940  case MISCREG_TLBI_VMALLS12E1IS:
1941  {
1942  assert64();
1943  scr = readMiscReg(MISCREG_SCR);
1944 
1945  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1946  TLBIVMALL tlbiOp(EL1, secure, true);
1947  tlbiOp.broadcast(tc);
1948  return;
1949  }
1950  case MISCREG_TLBI_VMALLE1IS:
1951  {
1952  assert64();
1953  scr = readMiscReg(MISCREG_SCR);
1954 
1955  ExceptionLevel target_el = EL1;
1956  if (EL2Enabled(tc)) {
1957  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1958  if (hcr.tge && hcr.e2h) {
1959  target_el = EL2;
1960  }
1961  }
1962 
1963  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
1964  TLBIVMALL tlbiOp(target_el, secure, false);
1965  tlbiOp.broadcast(tc);
1966  return;
1967  }
1968  // VAEx(IS) and VALEx(IS) are the same because TLBs
1969  // only store entries
1970  // from the last level of translation table walks
1971  // AArch64 TLB Invalidate by VA, EL3
1972  case MISCREG_TLBI_VAE3_Xt:
1973  case MISCREG_TLBI_VALE3_Xt:
1974  {
1975  assert64();
1976 
1977  TLBIMVAA tlbiOp(EL3, true,
1978  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1979  tlbiOp(tc);
1980  return;
1981  }
1982  // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1983  case MISCREG_TLBI_VAE3IS_Xt:
1984  case MISCREG_TLBI_VALE3IS_Xt:
1985  {
1986  assert64();
1987 
1988  TLBIMVAA tlbiOp(EL3, true,
1989  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1990 
1991  tlbiOp.broadcast(tc);
1992  return;
1993  }
1994  // AArch64 TLB Invalidate by VA, EL2
1995  case MISCREG_TLBI_VAE2_Xt:
1996  case MISCREG_TLBI_VALE2_Xt:
1997  {
1998  assert64();
1999  scr = readMiscReg(MISCREG_SCR);
2000  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
2001 
2002  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2003 
2004  if (hcr.e2h) {
2005  // The asid will only be used when e2h == 1
2006  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
2007  bits(newVal, 55, 48);
2008 
2009  TLBIMVA tlbiOp(EL2, secure,
2010  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
2011  asid);
2012  tlbiOp(tc);
2013  } else {
2014  TLBIMVAA tlbiOp(EL2, secure,
2015  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
2016  tlbiOp(tc);
2017  }
2018  return;
2019  }
2020  // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
2021  case MISCREG_TLBI_VAE2IS_Xt:
2022  case MISCREG_TLBI_VALE2IS_Xt:
2023  {
2024  assert64();
2025  scr = readMiscReg(MISCREG_SCR);
2026  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
2027 
2028  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2029 
2030  if (hcr.e2h) {
2031  // The asid will only be used when e2h == 1
2032  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
2033  bits(newVal, 55, 48);
2034 
2035  TLBIMVA tlbiOp(EL2, secure,
2036  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
2037  asid);
2038  tlbiOp.broadcast(tc);
2039  } else {
2040  TLBIMVAA tlbiOp(EL2, secure,
2041  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
2042  tlbiOp.broadcast(tc);
2043  }
2044  return;
2045  }
2046  // AArch64 TLB Invalidate by VA, EL1
2047  case MISCREG_TLBI_VAE1_Xt:
2048  case MISCREG_TLBI_VALE1_Xt:
2049  {
2050  assert64();
2051  scr = readMiscReg(MISCREG_SCR);
2052  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
2053  bits(newVal, 55, 48);
2054 
2055  ExceptionLevel target_el = EL1;
2056  if (EL2Enabled(tc)) {
2057  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
2058  if (hcr.tge && hcr.e2h) {
2059  target_el = EL2;
2060  }
2061  }
2062 
2063  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2064  TLBIMVA tlbiOp(target_el, secure,
2065  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
2066  asid);
2067 
2068  tlbiOp(tc);
2069  return;
2070  }
2071  // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
2072  case MISCREG_TLBI_VAE1IS_Xt:
2073  case MISCREG_TLBI_VALE1IS_Xt:
2074  {
2075  assert64();
2076  scr = readMiscReg(MISCREG_SCR);
2077  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
2078  bits(newVal, 55, 48);
2079 
2080  ExceptionLevel target_el = EL1;
2081  if (EL2Enabled(tc)) {
2082  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
2083  if (hcr.tge && hcr.e2h) {
2084  target_el = EL2;
2085  }
2086  }
2087 
2088  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2089  TLBIMVA tlbiOp(target_el, secure,
2090  static_cast<Addr>(bits(newVal, 43, 0)) << 12,
2091  asid);
2092 
2093  tlbiOp.broadcast(tc);
2094  return;
2095  }
2096  // AArch64 TLB Invalidate by ASID, EL1
2097  case MISCREG_TLBI_ASIDE1_Xt:
2098  {
2099  assert64();
2100  scr = readMiscReg(MISCREG_SCR);
2101  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
2102  bits(newVal, 55, 48);
2103 
2104  ExceptionLevel target_el = EL1;
2105  if (EL2Enabled(tc)) {
2106  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
2107  if (hcr.tge && hcr.e2h) {
2108  target_el = EL2;
2109  }
2110  }
2111 
2112  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2113  TLBIASID tlbiOp(target_el, secure, asid);
2114  tlbiOp(tc);
2115  return;
2116  }
2117  // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
2118  case MISCREG_TLBI_ASIDE1IS_Xt:
2119  {
2120  assert64();
2121  scr = readMiscReg(MISCREG_SCR);
2122  auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
2123  bits(newVal, 55, 48);
2124 
2125  ExceptionLevel target_el = EL1;
2126  if (EL2Enabled(tc)) {
2127  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
2128  if (hcr.tge && hcr.e2h) {
2129  target_el = EL2;
2130  }
2131  }
2132 
2133  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2134  TLBIASID tlbiOp(target_el, secure, asid);
2135  tlbiOp.broadcast(tc);
2136  return;
2137  }
2138  // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
2139  // entries from the last level of translation table walks
2140  // AArch64 TLB Invalidate by VA, All ASID, EL1
2141  case MISCREG_TLBI_VAAE1_Xt:
2142  case MISCREG_TLBI_VAALE1_Xt:
2143  {
2144  assert64();
2145  scr = readMiscReg(MISCREG_SCR);
2146 
2147  ExceptionLevel target_el = EL1;
2148  if (EL2Enabled(tc)) {
2149  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
2150  if (hcr.tge && hcr.e2h) {
2151  target_el = EL2;
2152  }
2153  }
2154 
2155  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2156  TLBIMVAA tlbiOp(target_el, secure,
2157  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
2158 
2159  tlbiOp(tc);
2160  return;
2161  }
2162  // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
2163  case MISCREG_TLBI_VAAE1IS_Xt:
2164  case MISCREG_TLBI_VAALE1IS_Xt:
2165  {
2166  assert64();
2167  scr = readMiscReg(MISCREG_SCR);
2168 
2169  ExceptionLevel target_el = EL1;
2170  if (EL2Enabled(tc)) {
2171  HCR hcr = readMiscReg(MISCREG_HCR_EL2);
2172  if (hcr.tge && hcr.e2h) {
2173  target_el = EL2;
2174  }
2175  }
2176 
2177  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2178  TLBIMVAA tlbiOp(target_el, secure,
2179  static_cast<Addr>(bits(newVal, 43, 0)) << 12);
2180 
2181  tlbiOp.broadcast(tc);
2182  return;
2183  }
2184  // AArch64 TLB Invalidate by Intermediate Physical Address,
2185  // Stage 2, EL1
2186  case MISCREG_TLBI_IPAS2E1_Xt:
2187  case MISCREG_TLBI_IPAS2LE1_Xt:
2188  {
2189  assert64();
2190  scr = readMiscReg(MISCREG_SCR);
2191 
2192  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2193  TLBIIPA tlbiOp(EL1, secure,
2194  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
2195 
2196  tlbiOp(tc);
2197  return;
2198  }
2199  // AArch64 TLB Invalidate by Intermediate Physical Address,
2200  // Stage 2, EL1, Inner Shareable
2201  case MISCREG_TLBI_IPAS2E1IS_Xt:
2202  case MISCREG_TLBI_IPAS2LE1IS_Xt:
2203  {
2204  assert64();
2205  scr = readMiscReg(MISCREG_SCR);
2206 
2207  bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
2208  TLBIIPA tlbiOp(EL1, secure,
2209  static_cast<Addr>(bits(newVal, 35, 0)) << 12);
2210 
2211  tlbiOp.broadcast(tc);
2212  return;
2213  }
2214  case MISCREG_ACTLR:
2215  warn("Not doing anything for write of miscreg ACTLR\n");
2216  break;
2217 
2218  case MISCREG_PMXEVTYPER_PMCCFILTR:
2219  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
2220  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
2221  case MISCREG_PMCR ... MISCREG_PMOVSSET:
2222  pmu->setMiscReg(misc_reg, newVal);
2223  break;
2224 
2225 
2226  case MISCREG_HSTR: // TJDBX, now redifined to be RES0
2227  {
2228  HSTR hstrMask = 0;
2229  hstrMask.tjdbx = 1;
2230  newVal &= ~((uint32_t) hstrMask);
2231  break;
2232  }
2233  case MISCREG_HCPTR:
2234  {
2235  // If a CP bit in NSACR is 0 then the corresponding bit in
2236  // HCPTR is RAO/WI. Same applies to NSASEDIS
2237  secure_lookup = release->has(ArmExtension::SECURITY) &&
2238  isSecure(tc);
2239  if (!secure_lookup) {
2240  RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
2241  RegVal mask =
2242  (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
2243  newVal = (newVal & ~mask) | (oldValue & mask);
2244  }
2245  break;
2246  }
2247  case MISCREG_HDFAR: // alias for secure DFAR
2248  misc_reg = MISCREG_DFAR_S;
2249  break;
2250  case MISCREG_HIFAR: // alias for secure IFAR
2251  misc_reg = MISCREG_IFAR_S;
2252  break;
2253  case MISCREG_ATS1CPR:
2254  addressTranslation(MMU::S1CTran, BaseMMU::Read, 0, val);
2255  return;
2256  case MISCREG_ATS1CPW:
2257  addressTranslation(MMU::S1CTran, BaseMMU::Write, 0, val);
2258  return;
2259  case MISCREG_ATS1CUR:
2260  addressTranslation(MMU::S1CTran, BaseMMU::Read,
2261  MMU::UserMode, val);
2262  return;
2263  case MISCREG_ATS1CUW:
2264  addressTranslation(MMU::S1CTran, BaseMMU::Write,
2265  MMU::UserMode, val);
2266  return;
2267  case MISCREG_ATS12NSOPR:
2268  if (!release->has(ArmExtension::SECURITY))
2269  panic("Security Extensions required for ATS12NSOPR");
2270  addressTranslation(MMU::S1S2NsTran, BaseMMU::Read, 0, val);
2271  return;
2272  case MISCREG_ATS12NSOPW:
2273  if (!release->has(ArmExtension::SECURITY))
2274  panic("Security Extensions required for ATS12NSOPW");
2275  addressTranslation(MMU::S1S2NsTran, BaseMMU::Write, 0, val);
2276  return;
2277  case MISCREG_ATS12NSOUR:
2278  if (!release->has(ArmExtension::SECURITY))
2279  panic("Security Extensions required for ATS12NSOUR");
2280  addressTranslation(MMU::S1S2NsTran, BaseMMU::Read,
2281  MMU::UserMode, val);
2282  return;
2283  case MISCREG_ATS12NSOUW:
2284  if (!release->has(ArmExtension::SECURITY))
2285  panic("Security Extensions required for ATS12NSOUW");
2286  addressTranslation(MMU::S1S2NsTran, BaseMMU::Write,
2287  MMU::UserMode, val);
2288  return;
2289  case MISCREG_ATS1HR:
2290  addressTranslation(MMU::HypMode, BaseMMU::Read, 0, val);
2291  return;
2292  case MISCREG_ATS1HW:
2293  addressTranslation(MMU::HypMode, BaseMMU::Write, 0, val);
2294  return;
2295  case MISCREG_TTBCR:
2296  {
2297  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2298  const uint32_t ones = (uint32_t)(-1);
2299  TTBCR ttbcrMask = 0;
2300  TTBCR ttbcrNew = newVal;
2301 
2302  // ARM DDI 0406C.b, ARMv7-32
2303  ttbcrMask.n = ones; // T0SZ
2304  if (release->has(ArmExtension::SECURITY)) {
2305  ttbcrMask.pd0 = ones;
2306  ttbcrMask.pd1 = ones;
2307  }
2308  ttbcrMask.epd0 = ones;
2309  ttbcrMask.irgn0 = ones;
2310  ttbcrMask.orgn0 = ones;
2311  ttbcrMask.sh0 = ones;
2312  ttbcrMask.ps = ones; // T1SZ
2313  ttbcrMask.a1 = ones;
2314  ttbcrMask.epd1 = ones;
2315  ttbcrMask.irgn1 = ones;
2316  ttbcrMask.orgn1 = ones;
2317  ttbcrMask.sh1 = ones;
2318  if (release->has(ArmExtension::LPAE))
2319  ttbcrMask.eae = ones;
2320 
2321  if (release->has(ArmExtension::LPAE) && ttbcrNew.eae) {
2322  newVal = newVal & ttbcrMask;
2323  } else {
2324  newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
2325  }
2326  // Invalidate TLB MiscReg
2327  getMMUPtr(tc)->invalidateMiscReg();
2328  break;
2329  }
2330  case MISCREG_TTBR0:
2331  case MISCREG_TTBR1:
2332  {
2333  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2334  if (release->has(ArmExtension::LPAE)) {
2335  if (ttbcr.eae) {
2336  // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
2337  // ARMv8 AArch32 bit 63-56 only
2338  uint64_t ttbrMask = mask(63,56) | mask(47,40);
2339  newVal = (newVal & (~ttbrMask));
2340  }
2341  }
2342  // Invalidate TLB MiscReg
2343  getMMUPtr(tc)->invalidateMiscReg();
2344  break;
2345  }
2346  case MISCREG_SCTLR_EL1:
2347  case MISCREG_CONTEXTIDR:
2348  case MISCREG_PRRR:
2349  case MISCREG_NMRR:
2350  case MISCREG_MAIR0:
2351  case MISCREG_MAIR1:
2352  case MISCREG_DACR:
2353  case MISCREG_VTTBR:
2354  case MISCREG_SCR_EL3:
2355  case MISCREG_TCR_EL1:
2356  case MISCREG_TCR_EL2:
2357  case MISCREG_TCR_EL3:
2358  case MISCREG_VTCR_EL2:
2359  case MISCREG_SCTLR_EL2:
2360  case MISCREG_SCTLR_EL3:
2361  case MISCREG_HSCTLR:
2362  case MISCREG_TTBR0_EL1:
2363  case MISCREG_TTBR1_EL1:
2364  case MISCREG_TTBR0_EL2:
2365  case MISCREG_TTBR1_EL2:
2366  case MISCREG_TTBR0_EL3:
2367  getMMUPtr(tc)->invalidateMiscReg();
2368  break;
2369  case MISCREG_HCR_EL2:
2370  {
2371  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
2372  selfDebug->setenableTDETGE((HCR)val, mdcr);
2373  getMMUPtr(tc)->invalidateMiscReg();
2374  }
2375  break;
2376  case MISCREG_NZCV:
2377  {
2378  CPSR cpsr = val;
2379 
2380  tc->setCCReg(CCREG_NZ, cpsr.nz);
2381  tc->setCCReg(CCREG_C, cpsr.c);
2382  tc->setCCReg(CCREG_V, cpsr.v);
2383  }
2384  break;
2385  case MISCREG_DAIF:
2386  {
2387  CPSR cpsr = miscRegs[MISCREG_CPSR];
2388  cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
2389  newVal = cpsr;
2390  misc_reg = MISCREG_CPSR;
2391  }
2392  break;
2393  case MISCREG_SP_EL0:
2394  tc->setIntReg(INTREG_SP0, newVal);
2395  break;
2396  case MISCREG_SP_EL1:
2397  tc->setIntReg(INTREG_SP1, newVal);
2398  break;
2399  case MISCREG_SP_EL2:
2400  tc->setIntReg(INTREG_SP2, newVal);
2401  break;
2402  case MISCREG_SPSEL:
2403  {
2404  CPSR cpsr = miscRegs[MISCREG_CPSR];
2405  cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
2406  newVal = cpsr;
2407  misc_reg = MISCREG_CPSR;
2408  }
2409  break;
2410  case MISCREG_CURRENTEL:
2411  {
2412  CPSR cpsr = miscRegs[MISCREG_CPSR];
2413  cpsr.el = (uint8_t) ((CPSR) newVal).el;
2414  newVal = cpsr;
2415  misc_reg = MISCREG_CPSR;
2416  }
2417  break;
2418  case MISCREG_PAN:
2419  {
2420  // PAN is affecting data accesses
2421  getMMUPtr(tc)->invalidateMiscReg();
2422 
2423  CPSR cpsr = miscRegs[MISCREG_CPSR];
2424  cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
2425  newVal = cpsr;
2426  misc_reg = MISCREG_CPSR;
2427  }
2428  break;
2429  case MISCREG_UAO:
2430  {
2431  // UAO is affecting data accesses
2432  getMMUPtr(tc)->invalidateMiscReg();
2433 
2434  CPSR cpsr = miscRegs[MISCREG_CPSR];
2435  cpsr.uao = (uint8_t) ((CPSR) newVal).uao;
2436  newVal = cpsr;
2437  misc_reg = MISCREG_CPSR;
2438  }
2439  break;
2440  case MISCREG_AT_S1E1R_Xt:
2441  addressTranslation64(MMU::S1E1Tran, BaseMMU::Read, 0, val);
2442  return;
2443  case MISCREG_AT_S1E1W_Xt:
2444  addressTranslation64(MMU::S1E1Tran, BaseMMU::Write, 0, val);
2445  return;
2446  case MISCREG_AT_S1E0R_Xt:
2447  addressTranslation64(MMU::S1E0Tran, BaseMMU::Read,
2448  MMU::UserMode, val);
2449  return;
2450  case MISCREG_AT_S1E0W_Xt:
2451  addressTranslation64(MMU::S1E0Tran, BaseMMU::Write,
2452  MMU::UserMode, val);
2453  return;
2454  case MISCREG_AT_S1E2R_Xt:
2455  addressTranslation64(MMU::S1E2Tran, BaseMMU::Read, 0, val);
2456  return;
2457  case MISCREG_AT_S1E2W_Xt:
2458  addressTranslation64(MMU::S1E2Tran, BaseMMU::Write, 0, val);
2459  return;
2460  case MISCREG_AT_S12E1R_Xt:
2461  addressTranslation64(MMU::S12E1Tran, BaseMMU::Read, 0, val);
2462  return;
2463  case MISCREG_AT_S12E1W_Xt:
2464  addressTranslation64(MMU::S12E1Tran, BaseMMU::Write, 0, val);
2465  return;
2466  case MISCREG_AT_S12E0R_Xt:
2467  addressTranslation64(MMU::S12E0Tran, BaseMMU::Read,
2468  MMU::UserMode, val);
2469  return;
2470  case MISCREG_AT_S12E0W_Xt:
2471  addressTranslation64(MMU::S12E0Tran, BaseMMU::Write,
2472  MMU::UserMode, val);
2473  return;
2474  case MISCREG_AT_S1E3R_Xt:
2475  addressTranslation64(MMU::S1E3Tran, BaseMMU::Read, 0, val);
2476  return;
2477  case MISCREG_AT_S1E3W_Xt:
2478  addressTranslation64(MMU::S1E3Tran, BaseMMU::Write, 0, val);
2479  return;
2480  case MISCREG_L2CTLR:
2481  warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2482  miscRegName[misc_reg], uint32_t(val));
2483  break;
2484 
2485  // Generic Timer registers
2486  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
2487  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
2488  getGenericTimer().setMiscReg(misc_reg, newVal);
2489  break;
2490  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
2491  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
2492  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2493  getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
2494  return;
2495  case MISCREG_ZCR_EL3:
2496  case MISCREG_ZCR_EL2:
2497  case MISCREG_ZCR_EL1:
2498  tc->getDecoderPtr()->as<Decoder>().setSveLen(
2499  (getCurSveVecLenInBits() >> 7) - 1);
2500  break;
2501  }
2502  setMiscRegNoEffect(misc_reg, newVal);
2503  }
2504 }
2505 
2506 BaseISADevice &
2507 ISA::getGenericTimer()
2508 {
2509  // We only need to create an ISA interface the first time we try
2510  // to access the timer.
2511  if (timer)
2512  return *timer.get();
2513 
2514  assert(system);
2515  GenericTimer *generic_timer(system->getGenericTimer());
2516  if (!generic_timer) {
2517  panic("Trying to get a generic timer from a system that hasn't "
2518  "been configured to use a generic timer.\n");
2519  }
2520 
2521  timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2522  timer->setThreadContext(tc);
2523 
2524  return *timer.get();
2525 }
2526 
2527 BaseISADevice &
2528 ISA::getGICv3CPUInterface()
2529 {
2530  panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2531  return *gicv3CpuInterface.get();
2532 }
2533 
2534 bool
2535 ISA::inSecureState() const
2536 {
2537  if (!release->has(ArmExtension::SECURITY)) {
2538  return false;
2539  }
2540 
2541  SCR scr = miscRegs[MISCREG_SCR];
2542  CPSR cpsr = miscRegs[MISCREG_CPSR];
2543 
2544  switch ((OperatingMode) (uint8_t) cpsr.mode) {
2545  case MODE_MON:
2546  case MODE_EL3T:
2547  case MODE_EL3H:
2548  return true;
2549  case MODE_HYP:
2550  case MODE_EL2T:
2551  case MODE_EL2H:
2552  return false;
2553  default:
2554  return !scr.ns;
2555  }
2556 }
2557 
2558 ExceptionLevel
2559 ISA::currEL() const
2560 {
2561  CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
2562 
2563  return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
2564 }
2565 
2566 unsigned
2567 ISA::getCurSveVecLenInBits() const
2568 {
2569  if (!FullSystem) {
2570  return sveVL * 128;
2571  }
2572 
2573  panic_if(!tc,
2574  "A ThreadContext is needed to determine the SVE vector length "
2575  "in full-system mode");
2576 
2577  CPSR cpsr = miscRegs[MISCREG_CPSR];
2578  ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2579 
2580  unsigned len = 0;
2581 
2582  if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2583  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2584  }
2585 
2586  if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2587  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2588  } else if (release->has(ArmExtension::VIRTUALIZATION) && !isSecure(tc) &&
2589  (el == EL0 || el == EL1)) {
2590  len = std::min(
2591  len,
2592  static_cast<unsigned>(
2593  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2594  }
2595 
2596  if (el == EL3) {
2597  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2598  } else if (release->has(ArmExtension::SECURITY)) {
2599  len = std::min(
2600  len,
2601  static_cast<unsigned>(
2602  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2603  }
2604 
2605  len = std::min(len, sveVL - 1);
2606 
2607  return (len + 1) * 128;
2608 }
2609 
2610 void
2611 ISA::serialize(CheckpointOut &cp) const
2612 {
2613  DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
2614  SERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2615 }
2616 
2617 void
2618 ISA::unserialize(CheckpointIn &cp)
2619 {
2620  DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
2621  UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2622  CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
2623  updateRegMap(tmp_cpsr);
2624 }
2625 
2626 void
2627 ISA::addressTranslation64(MMU::ArmTranslationType tran_type,
2628  BaseMMU::Mode mode, Request::Flags flags, RegVal val)
2629 {
2630  // If we're in timing mode then doing the translation in
2631  // functional mode then we're slightly distorting performance
2632  // results obtained from simulations. The translation should be
2633  // done in the same mode the core is running in. NOTE: This
2634  // can't be an atomic translation because that causes problems
2635  // with unexpected atomic snoop requests.
2636  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2637 
2638  auto req = std::make_shared<Request>(
2639  val, 0, flags, Request::funcRequestorId,
2640  tc->pcState().instAddr(), tc->contextId());
2641 
2642  Fault fault = getMMUPtr(tc)->translateFunctional(
2643  req, tc, mode, tran_type);
2644 
2645  PAR par = 0;
2646  if (fault == NoFault) {
2647  Addr paddr = req->getPaddr();
2648  uint64_t attr = getMMUPtr(tc)->getAttr();
2649  uint64_t attr1 = attr >> 56;
2650  if (!attr1 || attr1 ==0x44) {
2651  attr |= 0x100;
2652  attr &= ~ uint64_t(0x80);
2653  }
2654  par = (paddr & mask(47, 12)) | attr;
2655  DPRINTF(MiscRegs,
2656  "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2657  val, par);
2658  } else {
2659  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2660  arm_fault->update(tc);
2661  // Set fault bit and FSR
2662  FSR fsr = arm_fault->getFsr(tc);
2663 
2664  par.f = 1; // F bit
2665  par.fst = fsr.status; // FST
2666  par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
2667  par.s = arm_fault->isStage2() ? 1 : 0; // S
2668 
2669  DPRINTF(MiscRegs,
2670  "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2671  val, fsr, par);
2672  }
2673  setMiscRegNoEffect(MISCREG_PAR_EL1, par);
2674  return;
2675 }
2676 
2677 void
2678 ISA::addressTranslation(MMU::ArmTranslationType tran_type,
2679  BaseMMU::Mode mode, Request::Flags flags, RegVal val)
2680 {
2681  // If we're in timing mode then doing the translation in
2682  // functional mode then we're slightly distorting performance
2683  // results obtained from simulations. The translation should be
2684  // done in the same mode the core is running in. NOTE: This
2685  // can't be an atomic translation because that causes problems
2686  // with unexpected atomic snoop requests.
2687  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2688 
2689  auto req = std::make_shared<Request>(
2690  val, 0, flags, Request::funcRequestorId,
2691  tc->pcState().instAddr(), tc->contextId());
2692 
2693  Fault fault = getMMUPtr(tc)->translateFunctional(
2694  req, tc, mode, tran_type);
2695 
2696  PAR par = 0;
2697  if (fault == NoFault) {
2698  Addr paddr = req->getPaddr();
2699  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2700  HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
2701 
2702  uint8_t max_paddr_bit = 0;
2703  if (release->has(ArmExtension::LPAE) &&
2704  (ttbcr.eae || tran_type & MMU::HypMode ||
2705  ((tran_type & MMU::S1S2NsTran) && hcr.vm) )) {
2706 
2707  max_paddr_bit = 39;
2708  } else {
2709  max_paddr_bit = 31;
2710  }
2711 
2712  par = (paddr & mask(max_paddr_bit, 12)) |
2713  (getMMUPtr(tc)->getAttr());
2714 
2715  DPRINTF(MiscRegs,
2716  "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2717  val, par);
2718  } else {
2719  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2720  arm_fault->update(tc);
2721  // Set fault bit and FSR
2722  FSR fsr = arm_fault->getFsr(tc);
2723 
2724  par.f = 0x1; // F bit
2725  par.lpae = fsr.lpae;
2726  par.ptw = (arm_fault->iss() >> 7) & 0x1;
2727  par.s = arm_fault->isStage2() ? 1 : 0;
2728 
2729  if (par.lpae) {
2730  // LPAE - rearange fault status
2731  par.fst = fsr.status;
2732  } else {
2733  // VMSA - rearange fault status
2734  par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
2735  par.fs5 = fsr.ext;
2736  }
2737  DPRINTF(MiscRegs,
2738  "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2739  val, fsr, par);
2740  }
2741  setMiscRegNoEffect(MISCREG_PAR, par);
2742  return;
2743 }
2744 
2745 ISA::MiscRegLUTEntryInitializer::chain
2746 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2747 {
2748  switch (FullSystem ? sys->highestEL() : EL1) {
2749  case EL0:
2750  case EL1: priv(); break;
2751  case EL2: hyp(); break;
2752  case EL3: mon(); break;
2753  }
2754  return *this;
2755 }
2756 
2757 template <class XC>
2758 static inline void
2759 lockedSnoopHandler(ThreadContext *tc, XC *xc, PacketPtr pkt,
2760  Addr cacheBlockMask)
2761 {
2762  // Should only every see invalidations / direct writes
2763  assert(pkt->isInvalidate() || pkt->isWrite());
2764 
2765  DPRINTF(LLSC, "%s: handling snoop for address: %#x locked: %d\n",
2766  tc->getCpuPtr()->name(), pkt->getAddr(),
2767  xc->readMiscReg(MISCREG_LOCKFLAG));
2768  if (!xc->readMiscReg(MISCREG_LOCKFLAG))
2769  return;
2770 
2771  Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
2772  // If no caches are attached, the snoop address always needs to be masked
2773  Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
2774 
2775  DPRINTF(LLSC, "%s: handling snoop for address: %#x locked addr: %#x\n",
2776  tc->getCpuPtr()->name(), snoop_addr, locked_addr);
2777  if (locked_addr == snoop_addr) {
2778  DPRINTF(LLSC, "%s: address match, clearing lock and signaling sev\n",
2779  tc->getCpuPtr()->name());
2780  xc->setMiscReg(MISCREG_LOCKFLAG, false);
2781  // Implement ARMv8 WFE/SEV semantics
2782  sendEvent(tc);
2783  xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2784  }
2785 }
2786 
2787 void
2788 ISA::handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
2789 {
2790  lockedSnoopHandler(tc, tc, pkt, cacheBlockMask);
2791 }
2792 
2793 void
2794 ISA::handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)
2795 {
2796  lockedSnoopHandler(xc->tcBase(), xc, pkt, cacheBlockMask);
2797 }
2798 
2799 void
2800 ISA::handleLockedRead(const RequestPtr &req)
2801 {
2802  tc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
2803  tc->setMiscReg(MISCREG_LOCKFLAG, true);
2804  DPRINTF(LLSC, "%s: Placing address %#x in monitor\n",
2805  tc->getCpuPtr()->name(), req->getPaddr());
2806 }
2807 
2808 void
2809 ISA::handleLockedRead(ExecContext *xc, const RequestPtr &req)
2810 {
2811  xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
2812  xc->setMiscReg(MISCREG_LOCKFLAG, true);
2813  DPRINTF(LLSC, "%s: Placing address %#x in monitor\n",
2814  xc->tcBase()->getCpuPtr()->name(), req->getPaddr());
2815 }
2816 
2817 void
2818 ISA::handleLockedSnoopHit()
2819 {
2820  DPRINTF(LLSC, "%s: handling snoop lock hit address: %#x\n",
2821  tc->getCpuPtr()->name(), tc->readMiscReg(MISCREG_LOCKADDR));
2822  tc->setMiscReg(MISCREG_LOCKFLAG, false);
2823  tc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2824 }
2825 
2826 void
2827 ISA::handleLockedSnoopHit(ExecContext *xc)
2828 {
2829  DPRINTF(LLSC, "%s: handling snoop lock hit address: %#x\n",
2830  xc->tcBase()->getCpuPtr()->name(),
2831  xc->readMiscReg(MISCREG_LOCKADDR));
2832  xc->setMiscReg(MISCREG_LOCKFLAG, false);
2833  xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2834 }
2835 
2836 template <class XC>
2837 static inline bool
2838 lockedWriteHandler(ThreadContext *tc, XC *xc, const RequestPtr &req,
2839  Addr cacheBlockMask)
2840 {
2841  if (req->isSwap())
2842  return true;
2843 
2844  DPRINTF(LLSC, "Handling locked write for address %#x in monitor.\n",
2845  req->getPaddr());
2846  // Verify that the lock flag is still set and the address
2847  // is correct
2848  bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
2849  Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
2850  if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
2851  // Lock flag not set or addr mismatch in CPU;
2852  // don't even bother sending to memory system
2853  req->setExtraData(0);
2854  xc->setMiscReg(MISCREG_LOCKFLAG, false);
2855  DPRINTF(LLSC, "clearing lock flag in handle locked write\n",
2856  tc->getCpuPtr()->name());
2857  // the rest of this code is not architectural;
2858  // it's just a debugging aid to help detect
2859  // livelock by warning on long sequences of failed
2860  // store conditionals
2861  int stCondFailures = xc->readStCondFailures();
2862  stCondFailures++;
2863  xc->setStCondFailures(stCondFailures);
2864  if (stCondFailures % 100000 == 0) {
2865  warn("context %d: %d consecutive "
2866  "store conditional failures\n",
2867  tc->contextId(), stCondFailures);
2868  }
2869 
2870  // store conditional failed already, so don't issue it to mem
2871  return false;
2872  }
2873  return true;
2874 }
2875 
2876 bool
2877 ISA::handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
2878 {
2879  return lockedWriteHandler(tc, tc, req, cacheBlockMask);
2880 }
2881 
2882 bool
2883 ISA::handleLockedWrite(ExecContext *xc, const RequestPtr &req,
2884  Addr cacheBlockMask)
2885 {
2886  return lockedWriteHandler(xc->tcBase(), xc, req, cacheBlockMask);
2887 }
2888 
2889 void
2890 ISA::globalClearExclusive()
2891 {
2892  // A spinlock would typically include a Wait For Event (WFE) to
2893  // conserve energy. The ARMv8 architecture specifies that an event
2894  // is automatically generated when clearing the exclusive monitor
2895  // to wake up the processor in WFE.
2896  DPRINTF(LLSC, "Clearing lock and signaling sev\n");
2897  tc->setMiscReg(MISCREG_LOCKFLAG, false);
2898  // Implement ARMv8 WFE/SEV semantics
2899  sendEvent(tc);
2900  tc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2901 }
2902 
2903 void
2904 ISA::globalClearExclusive(ExecContext *xc)
2905 {
2906  // A spinlock would typically include a Wait For Event (WFE) to
2907  // conserve energy. The ARMv8 architecture specifies that an event
2908  // is automatically generated when clearing the exclusive monitor
2909  // to wake up the processor in WFE.
2910  DPRINTF(LLSC, "Clearing lock and signaling sev\n");
2911  xc->setMiscReg(MISCREG_LOCKFLAG, false);
2912  // Implement ARMv8 WFE/SEV semantics
2913  sendEvent(xc->tcBase());
2914  xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2915 }
2916 
2917 } // namespace ArmISA
2918 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:575
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: misc.hh:616
gem5::ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:278
gem5::ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: misc.hh:165
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: misc.hh:245
gic_v3_cpu_interface.hh
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::BaseISADevice::setISA
virtual void setISA(ISA *isa)
Definition: isa_device.cc:55
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:219
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:588
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:483
gem5::ArmISA::MMU::S12E0Tran
@ S12E0Tran
Definition: mmu.hh:129
gem5::ArmISA::ITLBIALL
Instruction TLB Invalidate All.
Definition: tlbi_op.hh:136
gem5::ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:213
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: misc.hh:325
gem5::ArmISA::CCREG_C
@ CCREG_C
Definition: cc.hh:50
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: misc.hh:448
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:351
gem5::ArmISA::ISA::addressTranslation64
void addressTranslation64(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2627
gem5::ArmISA::SelfDebug::setenableTDETGE
void setenableTDETGE(HCR hcr, HDCR mdcr)
Definition: self_debug.hh:397
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:230
gem5::ArmISA::SelfDebug::init
void init(ThreadContext *tc)
Definition: self_debug.cc:327
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: misc.hh:95
gem5::ArmISA::MMU::S12E1Tran
@ S12E1Tran
Definition: mmu.hh:130
gem5::ArmISA::ISA::dummyDevice
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
Definition: isa.hh:78
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:603
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:674
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: misc.hh:131
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ArmISA::ISA::currEL
ExceptionLevel currEL() const
Returns the current Exception Level (EL) of the ISA object.
Definition: isa.cc:2559
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::TLBIALLEL
Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions.
Definition: tlbi_op.hh:162
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:445
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: misc.hh:333
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:252
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:596
gem5::ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: misc.hh:367
gem5::ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:704
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: misc.hh:609
warn
#define warn(...)
Definition: logging.hh:246
gem5::System::Threads::size
int size() const
Definition: system.hh:214
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:225
gem5::ArmISA::ISA::selfDebug
SelfDebug * selfDebug
Definition: isa.hh:108
gem5::ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: misc.hh:384
gem5::ArmISA::BaseISADevice::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ExecContext::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:681
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:591
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:520
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: misc.hh:346
gem5::ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: misc.hh:381
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: misc.hh:677
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:801
system.hh
gem5::ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2567
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:183
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:509
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: misc.hh:618
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: misc.hh:254
gem5::ArmISA::TLBIASID
TLB Invalidate by ASID match.
Definition: tlbi_op.hh:216
gem5::ArmISA::ISA::gicv3CpuInterface
std::unique_ptr< BaseISADevice > gicv3CpuInterface
Definition: isa.hh:87
gem5::ArmISA::TLBIALL
TLB Invalidate All.
Definition: tlbi_op.hh:106
gem5::ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:701
gem5::igbreg::txd_op::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:304
gem5::Gicv3::getCPUInterface
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
Definition: gic_v3.hh:138
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:675
gem5::ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: misc.hh:169
gem5::ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:585
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:80
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: misc.hh:164
gem5::ArmISA::ISA::clear
void clear()
Definition: isa.cc:135
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: misc.hh:209
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:413
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:399
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: misc.hh:307
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:489
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: misc.hh:328
gem5::ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: misc.hh:242
gem5::ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: misc.hh:71
gem5::ArmISA::MMU::getAttr
uint64_t getAttr() const
Definition: mmu.hh:332
gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:690
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: misc.hh:233
gem5::ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: misc.hh:236
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: misc.hh:162
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: misc.hh:127
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:475
gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:687
gem5::ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: misc.hh:163
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: misc.hh:338
gem5::ArmISA::ISA::haveLargeAsid64
bool haveLargeAsid64
Definition: isa.hh:91
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: misc.hh:73
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: isa.hh:292
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: misc.hh:310
gem5::ArmISA::MODE_EL2T
@ MODE_EL2T
Definition: types.hh:277
gem5::ArmISA::ISA::takeOverFrom
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
Definition: isa.cc:546
gem5::ArmISA::ISA::handleLockedSnoop
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
Definition: isa.cc:2788
gem5::ArmISA::ISA::initID32
void initID32(const ArmISAParams &p)
Definition: isa.cc:328
gem5::ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: misc.hh:344
gem5::ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: misc.hh:347
gem5::InstDecoder::as
Type & as()
Definition: decoder.hh:71
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::ArmISA::attr
attr
Definition: misc_types.hh:656
gem5::ArmISA::lockedWriteHandler
static bool lockedWriteHandler(ThreadContext *tc, XC *xc, const RequestPtr &req, Addr cacheBlockMask)
Definition: isa.cc:2838
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: misc.hh:619
gem5::ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:276
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ArmISA::asid
asid
Definition: misc_types.hh:618
gem5::ArmISA::ISA::updateRegMap
void updateRegMap(CPSR cpsr)
Definition: isa.hh:573
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:56
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::ISA::release
const ArmRelease * release
This could be either a FS or a SE release.
Definition: isa.hh:98
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::CCREG_NZ
@ CCREG_NZ
Definition: cc.hh:49
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:518
gem5::ArmISA::ISA::timer
std::unique_ptr< BaseISADevice > timer
Definition: isa.hh:84
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: misc.hh:122
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1322
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: misc.hh:345
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:691
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:620
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:599
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:260
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:696
gem5::ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:702
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: misc.hh:337
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:201
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:246
gem5::ArmISA::SelfDebug::updateOSLock
void updateOSLock(RegVal val)
Definition: self_debug.hh:403
gem5::ArmISA::MMU::S1E0Tran
@ S1E0Tran
Definition: mmu.hh:125
gem5::ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:202
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:662
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:515
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: misc.hh:695
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:516
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: misc.hh:321
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: misc.hh:529
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:482
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: misc.hh:341
gem5::ArmISA::MMU::S1CTran
@ S1CTran
Definition: mmu.hh:116
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:710
gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: misc.hh:682
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:208
gem5::ArmISA::daif
Bitfield< 9, 6 > daif
Definition: misc_types.hh:70
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:566
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: misc.hh:329
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1173
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:610
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:290
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: misc.hh:83
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: misc.hh:158
gem5::ArmISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:553
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:223
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:487
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: misc.hh:350
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:486
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:218
gem5::ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: misc.hh:167
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:304
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:187
gem5::ArmISA::CpsrMaskQ
static const uint32_t CpsrMaskQ
Definition: misc.hh:2194
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: misc.hh:366
gem5::ArmISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:2611
gem5::ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
gem5::ArmISA::MMU::S1E3Tran
@ S1E3Tran
Definition: mmu.hh:128
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: misc.hh:370
gem5::ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: misc.hh:688
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:221
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: misc.hh:309
SERIALIZE_MAPPING
#define SERIALIZE_MAPPING(member, names, size)
Definition: serialize.hh:660
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::ExecContext::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
gem5::ArmISA::FpscrQcMask
static const uint32_t FpscrQcMask
Definition: misc.hh:2211
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: misc.hh:914
gem5::ArmISA::ISA::sveVL
unsigned sveVL
SVE vector length in quadwords.
Definition: isa.hh:95
gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:679
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::chain
const typedef MiscRegLUTEntryInitializer & chain
Definition: isa.hh:140
system.hh
gem5::ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: misc.hh:1102
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:564
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:235
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: misc.hh:655
gem5::ArmISA::DTLBIASID
Data TLB Invalidate by ASID match.
Definition: tlbi_op.hh:245
gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: misc.hh:706
faults.hh
gem5::ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: misc.hh:959
gem5::ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:280
gem5::ArmISA::ITLBIASID
Instruction TLB Invalidate by ASID match.
Definition: tlbi_op.hh:232
gem5::ArmISA::FpscrExcMask
static const uint32_t FpscrExcMask
Definition: misc.hh:2215
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:511
gem5::ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: misc.hh:161
gem5::ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:703
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:199
gem5::ArmISA::SelfDebug::updateDBGBCR
void updateDBGBCR(int index, DBGBCR val)
Definition: self_debug.hh:409
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:216
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:262
gem5::ArmSystem::getGIC
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition: system.hh:176
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: misc.hh:137
gem5::ArmISA::MMU::S1E2Tran
@ S1E2Tran
Definition: mmu.hh:127
gem5::ArmISA::ITLBIMVA
Instruction TLB Invalidate by VA.
Definition: tlbi_op.hh:313
gem5::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
gem5::ArmISA::getMMUPtr
MMU * getMMUPtr(T *tc)
Definition: mmu.hh:470
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:544
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:202
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:606
gem5::ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: misc.hh:128
gem5::ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:700
gem5::ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: misc.cc:3399
gem5::System::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: system.hh:312
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:512
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: misc.hh:265
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: misc.hh:157
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:220
gem5::ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:921
gem5::ArmISA::ISA::initID64
void initID64(const ArmISAParams &p)
Definition: isa.cc:381
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:103
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:217
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:271
gem5::ArmISA::SelfDebug::setbSDD
void setbSDD(RegVal val)
Definition: self_debug.hh:377
gem5::ArmISA::TLBIALLN
TLB Invalidate All, Non-Secure.
Definition: tlbi_op.hh:258
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: misc.hh:332
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
mmu.hh
gem5::ArmISA::ISA::handleLockedRead
void handleLockedRead(const RequestPtr &req) override
Definition: isa.cc:2800
gem5::ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: misc.hh:237
gem5::ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:521
gem5::ArmISA::MMU::UserMode
@ UserMode
Definition: mmu.hh:110
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition: system.hh:75
gem5::ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: misc.hh:249
htm.hh
gem5::ArmISA::Interrupts
Definition: interrupts.hh:70
gem5::Flags< FlagsType >
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:433
gem5::ArmISA::MODE_EL3T
@ MODE_EL3T
Definition: types.hh:279
gem5::ArmISA::SelfDebug::setMDBGen
void setMDBGen(RegVal val)
Definition: self_debug.hh:391
gem5::ArmISA::ISA::pmu
BaseISADevice * pmu
Definition: isa.hh:81
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: misc.hh:331
gem5::ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: misc.hh:339
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: misc.hh:123
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:369
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:67
gem5::ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: vec.hh:81
decoder.hh
gem5::ThreadContext::setHtmCheckpointPtr
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
gem5::ThreadContext::setVecElemFlat
virtual void setVecElemFlat(RegIndex idx, const ElemIndex &elem_idx, RegVal val)=0
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:187
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:154
gem5::ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: misc.hh:738
gem5::ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: misc.hh:130
interrupts.hh
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: misc.hh:132
gem5::ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: misc.hh:168
gem5::ArmISA::ISA::handleLockedSnoopHit
void handleLockedSnoopHit() override
Definition: isa.cc:2818
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: misc.hh:306
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:562
gem5::ArmISA::SelfDebug::setMDSCRvals
void setMDSCRvals(RegVal val)
Definition: self_debug.hh:383
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:508
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: misc.hh:125
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:822
gem5::ArmISA::ISA::clear64
void clear64(const ArmISAParams &p)
Definition: isa.cc:279
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:222
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: misc.hh:1051
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:250
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:595
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:224
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: misc.hh:136
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:394
gem5::ThreadContext::readVecElemFlat
virtual RegVal readVecElemFlat(RegIndex idx, const ElemIndex &elem_idx) const =0
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:725
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: misc.hh:159
gem5::ThreadContext::getDecoderPtr
virtual InstDecoder * getDecoderPtr()=0
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:378
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: misc.hh:75
gem5::ArmISA::ISA::globalClearExclusive
void globalClearExclusive() override
Definition: isa.cc:2890
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: misc.hh:539
gem5::ArmISA::TLBIMVAA
TLB Invalidate by VA, All ASID.
Definition: tlbi_op.hh:281
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:660
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:584
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:565
gem5::ArmISA::ISA::getMiscIndices
std::pair< int, int > getMiscIndices(int misc_reg) const
Definition: isa.hh:941
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1097
isa.hh
gem5::ArmISA::uao
Bitfield< 23 > uao
Definition: misc_types.hh:58
gem5::ArmISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:2618
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:296
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:439
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:227
gem5::ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:510
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:83
gem5::ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: misc.hh:74
cpu.hh
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:454
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:234
gem5::ArmISA::ISA::addressTranslation
void addressTranslation(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2678
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:90
gem5::ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: misc.hh:343
gem5::ArmISA::Decoder
Definition: decoder.hh:63
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:507
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::GenericTimer
Definition: generic_timer.hh:288
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: misc.hh:882
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:582
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: misc.hh:319
gem5::ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: misc.hh:133
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:282
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: misc.hh:617
tlbi_op.hh
gem5::ArmISA::pan
Bitfield< 22 > pan
Definition: misc_types.hh:59
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:540
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: misc.hh:238
gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:680
gem5::ArmISA::ISA::assert32
void assert32()
Definition: isa.hh:614
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:665
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:627
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:661
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: misc.hh:396
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: misc.hh:741
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:214
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: misc.hh:205
cprintf.hh
gem5::insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:166
gem5::ArmISA::ISA::handleLockedWrite
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
Definition: isa.cc:2877
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:478
gem5::ArmISA::miscRegClassOps
gem5::ArmISA::MiscRegClassOps miscRegClassOps
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::ISA::getGICv3CPUInterface
BaseISADevice & getGICv3CPUInterface()
Definition: isa.cc:2528
gem5::ArmISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:609
gem5::ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: misc.hh:294
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::ISA::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: isa.cc:508
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:212
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:563
faults.hh
generic_timer.hh
gem5::ArmISA::ISA::getGenericTimer
BaseISADevice & getGenericTimer()
Definition: isa.cc:2507
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:289
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:570
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: misc.hh:743
gem5::ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: misc.hh:393
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:207
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: misc.hh:134
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: misc.hh:334
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: misc.hh:376
gem5::ArmISA::MISCREG_LOCKADDR
@ MISCREG_LOCKADDR
Definition: misc.hh:82
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:268
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:375
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:474
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: misc.hh:257
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::ArmISA::MMU::HypMode
@ HypMode
Definition: mmu.hh:117
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: misc.cc:3402
gem5::ArmISA::TLBIIPA
TLB Invalidate by Intermediate Physical Address.
Definition: tlbi_op.hh:341
gem5::ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: misc.hh:288
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: misc.hh:634
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: misc.hh:1054
gem5::ArmISA::ArmFault::getFsr
virtual FSR getFsr(ThreadContext *tc) const
Definition: faults.hh:254
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: misc.hh:155
utility.hh
gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: misc.hh:698
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:481
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:90
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:479
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:372
gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: misc.hh:683
gem5::ArmISA::HTMCheckpoint
Definition: htm.hh:58
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:484
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: misc.hh:126
gem5::ArmISA::ISA::setupThreadContext
void setupThreadContext()
Definition: isa.cc:525
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: misc.hh:323
gem5::ArmISA::ISA::lookUpMiscReg
static std::vector< struct MiscRegLUTEntry > lookUpMiscReg
Metadata table accessible via the value of the register.
Definition: isa.hh:134
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:788
gem5::ThreadContext::pcStateNoRecord
virtual void pcStateNoRecord(const PCStateBase &val)=0
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:506
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: misc.hh:308
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:229
gem5::ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: misc.hh:160
stat_control.hh
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:517
gem5::ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: misc.hh:81
gem5::ArmISA::MMU::ArmTranslationType
ArmTranslationType
Definition: mmu.hh:113
gem5::Gicv3
Definition: gic_v3.hh:56
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: misc.hh:305
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::ArmISA::MMU::S1S2NsTran
@ S1S2NsTran
Definition: mmu.hh:120
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:206
gem5::ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: misc.hh:1093
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::BaseISADevice::setThreadContext
virtual void setThreadContext(ThreadContext *tc)
Definition: isa_device.hh:68
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: misc.hh:330
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:248
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: misc.hh:285
gem5::ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: misc.hh:342
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: misc.hh:320
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: isa.cc:2746
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:261
gem5::Gicv3CPUInterface
Definition: gic_v3_cpu_interface.hh:58
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: misc.hh:311
gem5::ArmSystem::sveVL
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
Definition: system.hh:205
gem5::ArmISA::MiscRegClassOps
Definition: isa.cc:73
base.hh
gem5::ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: misc.hh:80
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:676
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: misc.hh:1058
gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: misc.hh:686
gem5::SimObject::startup
virtual void startup()
startup() is the final initialization call before simulation.
Definition: sim_object.cc:99
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:228
gem5::ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: misc.hh:885
gem5::ArmISA::MMU::translateFunctional
TranslationGenPtr translateFunctional(Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
Returns a translation generator for a region of virtual addresses, instead of directly translating a ...
Definition: mmu.hh:90
gem5::ArmISA::DTLBIALL
Data TLB Invalidate All.
Definition: tlbi_op.hh:149
gem5::ArmISA::TLBIOp::broadcast
void broadcast(ThreadContext *tc)
Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
Definition: tlbi_op.hh:73
gem5::ArmISA::ISA::miscRegs
RegVal miscRegs[NUM_MISCREGS]
Definition: isa.hh:569
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:326
gem5::ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: misc.hh:348
gem5::ArmISA::lockedSnoopHandler
static void lockedSnoopHandler(ThreadContext *tc, XC *xc, PacketPtr pkt, Addr cacheBlockMask)
Definition: isa.cc:2759
gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:689
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: misc.hh:124
misc.hh
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:64
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:476
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:513
gem5::ArmISA::TLBIMVA
TLB Invalidate by VA.
Definition: tlbi_op.hh:296
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:72
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:188
gem5::ArmISA::NUM_CCREGS
@ NUM_CCREGS
Definition: cc.hh:55
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::TLBIVMALL
Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions.
Definition: tlbi_op.hh:188
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: misc.hh:837
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:243
reg_class.hh
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:211
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:198
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:578
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmSystem::releaseFS
const ArmRelease * releaseFS() const
Definition: system.hh:152
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:790
gem5::ArmSystem::getGenericTimer
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
Definition: system.hh:173
gem5::ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:707
gem5::ArmISA::MMU::invalidateMiscReg
void invalidateMiscReg()
Definition: mmu.cc:197
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:210
gem5::ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)=0
pmu.hh
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:480
gem5::ArmISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:943
gem5::ArmISA::BaseISADevice::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:622
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: misc.hh:1055
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmISA::NUM_PHYS_MISCREGS
@ NUM_PHYS_MISCREGS
Definition: misc.hh:1065
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ArmISA::MMU::S1E1Tran
@ S1E1Tran
Definition: mmu.hh:126
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:226
gem5::ArmISA::ISA::physAddrRange
uint8_t physAddrRange
Definition: isa.hh:92
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: misc.hh:576
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:621
gem5::ArmISA::ISA::redirectRegVHE
int redirectRegVHE(int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
Definition: isa.hh:862
gem5::ArmISA::DTLBIMVA
Data TLB Invalidate by VA.
Definition: tlbi_op.hh:327
gem5::ThreadContext::setVecRegFlat
virtual void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val)=0
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:753
gem5::ArmISA::SelfDebug::updateDBGWCR
void updateDBGWCR(int index, DBGWCR val)
Definition: self_debug.hh:415
self_debug.hh
gem5::BaseISA
Definition: isa.hh:57
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:400
gem5::ArmISA::sp
Bitfield< 0 > sp
Definition: misc_types.hh:75
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: misc.hh:156
gem5::ArmISA::ISA::afterStartup
bool afterStartup
Definition: isa.hh:106
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: misc.hh:322
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:673
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:694
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: misc.hh:335
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: misc.hh:304
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:597
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:485
gem5::ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: misc.hh:709
gem5::ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: misc.hh:699
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: misc.hh:336
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: misc.hh:1056
gem5::ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: misc.hh:91
decoder.hh
gem5::ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:684
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:514
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:561
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: misc.hh:96
gem5::ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: misc.hh:166
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:324
gem5::ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: misc.hh:685
gem5::ArmISA::SelfDebug::setDebugMask
void setDebugMask(bool mask)
Definition: self_debug.hh:421
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: misc.hh:349
gem5::ArmISA::ArmFault::isStage2
virtual bool isStage2() const
Definition: faults.hh:253
gem5::GenericTimerISA
Definition: generic_timer.hh:390
gem5::ArmISA::CCREG_V
@ CCREG_V
Definition: cc.hh:51
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:215
gem5::ArmISA::MMU
Definition: mmu.hh:59
gem5::ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: misc.hh:678
UNSERIALIZE_MAPPING
#define UNSERIALIZE_MAPPING(member, names, size)
Definition: serialize.hh:666
gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:705
gem5::ThreadContext::readVecRegFlat
virtual const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const =0
gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:697
gem5::loader::Arm
@ Arm
Definition: object_file.hh:59
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:241
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:455
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:488
gem5::ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
gic_v3.hh
gem5::ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: misc.cc:1349
gem5::ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: misc.hh:129
gem5::ArmISA::ISA::clear32
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
Definition: isa.cc:227
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: misc.hh:739
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:567
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:528
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:659
gem5::RegClassOps
Definition: reg_class.hh:71
gem5::ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:142
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:820
gem5::ArmISA::MISCREG_UAO
@ MISCREG_UAO
Definition: misc.hh:1094
gem5::ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: misc.hh:135
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:213
gem5::ArmISA::MiscRegClassOps::regName
std::string regName(const RegId &id) const override
Definition: isa.cc:77
gem5::ArmISA::ISA::inSecureState
bool inSecureState() const
Return true if the PE is in Secure state.
Definition: isa.cc:2535
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: misc.hh:340
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: misc.hh:327
gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:693
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:1365
gem5::ArmISA::ISA::assert64
void assert64()
Definition: isa.hh:615
gem5::Packet::isInvalidate
bool isInvalidate() const
Definition: packet.hh:598
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:601
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:692
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
gem5::ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: misc.hh:708
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: misc.hh:1105
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:670
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:519
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: misc.hh:79
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