This is an implementation of a KVM-based ARMv8-compatible CPU. More...

#include <armv8_cpu.hh>

Inheritance diagram for gem5::ArmV8KvmCPU:

Classes
struct	IntRegInfo
	Mapping between integer registers in gem5 and KVM. More...

struct	MiscRegInfo
	Mapping between misc registers in gem5 and registers in KVM. More...

Public Member Functions
	ArmV8KvmCPU (const ArmV8KvmCPUParams &params)

virtual	~ArmV8KvmCPU ()

void	startup () override

void	dump () const override
	Dump the internal state to the terminal. More...

Public Member Functions inherited from gem5::BaseArmKvmCPU
	BaseArmKvmCPU (const BaseArmKvmCPUParams &params)

virtual	~BaseArmKvmCPU ()

void	startup () override

Public Member Functions inherited from gem5::BaseKvmCPU
	BaseKvmCPU (const BaseKvmCPUParams &params)

virtual	~BaseKvmCPU ()

void	init () override

void	startup () override

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override

DrainState	drain () override

void	drainResume () override

void	notifyFork () override

void	switchOut () override

void	takeOverFrom (BaseCPU *cpu) override

void	verifyMemoryMode () const override

Port &	getDataPort () override

Port &	getInstPort () override

void	wakeup (ThreadID tid=0) override

void	activateContext (ThreadID thread_num) override

void	suspendContext (ThreadID thread_num) override

void	deallocateContext (ThreadID thread_num)

void	haltContext (ThreadID thread_num) override

long	getVCpuID () const

ThreadContext *	getContext (int tn) override

Counter	totalInsts () const override

Counter	totalOps () const override

void	finishMMIOPending ()
	Callback from KvmCPUPort to transition the CPU out of RunningMMIOPending when all timing requests have completed. More...

void	kick () const
	Force an exit from KVM. More...

Protected Member Functions
void	updateKvmState () override
	Update the KVM state from the current thread context. More...

void	updateThreadContext () override
	Update the current thread context with the KVM state. More...

const std::vector< ArmV8KvmCPU::MiscRegInfo > &	getSysRegMap () const
	Get a map between system registers in kvm and gem5 registers. More...

Protected Member Functions inherited from gem5::BaseArmKvmCPU
Tick	kvmRun (Tick ticks) override
	Request KVM to run the guest for a given number of ticks. More...

void	stutterPC (PCStateBase &pc) const override
	Modify a PCStatePtr's value so that its next PC is the current PC. More...

void	ioctlRun () override
	Override for synchronizing state in kvm_run. More...

const RegIndexVector &	getRegList () const
	Get a list of registers supported by getOneReg() and setOneReg(). More...

void	kvmArmVCpuInit (const kvm_vcpu_init &init)
	Tell the kernel to initialize this CPU. More...

Protected Member Functions inherited from gem5::BaseKvmCPU
void	tick ()
	Execute the CPU until the next event in the main event queue or until the guest needs service from gem5. More...

virtual uint64_t	getHostCycles () const
	Get the value of the hardware cycle counter in the guest. More...

virtual Tick	kvmRunDrain ()
	Request the CPU to run until draining completes. More...

struct kvm_run *	getKvmRunState ()
	Get a pointer to the kvm_run structure containing all the input and output parameters from kvmRun(). More...

uint8_t *	getGuestData (uint64_t offset) const
	Retrieve a pointer to guest data stored at the end of the kvm_run structure. More...

void	kvmNonMaskableInterrupt ()
	Send a non-maskable interrupt to the guest. More...

void	kvmInterrupt (const struct kvm_interrupt &interrupt)
	Send a normal interrupt to the guest. More...

std::string	getAndFormatOneReg (uint64_t id) const
	Get and format one register for printout. More...

virtual bool	archIsDrained () const
	Is the architecture specific code in a state that prevents draining? More...

Tick	doMMIOAccess (Addr paddr, void *data, int size, bool write)
	Inject a memory mapped IO request into gem5. More...

int	ioctl (int request, long p1) const
	vCPU ioctl interface. More...

int	ioctl (int request, void *p1) const

int	ioctl (int request) const

void	getRegisters (struct kvm_regs &regs) const
	Get/Set the register state of the guest vCPU. More...

void	setRegisters (const struct kvm_regs &regs)

void	getSpecialRegisters (struct kvm_sregs &regs) const

void	setSpecialRegisters (const struct kvm_sregs &regs)

void	getFPUState (struct kvm_fpu &state) const
	Get/Set the guest FPU/vector state. More...

void	setFPUState (const struct kvm_fpu &state)

void	setOneReg (uint64_t id, const void *addr)
	Get/Set single register using the KVM_(SET\|GET)_ONE_REG API. More...

void	setOneReg (uint64_t id, uint64_t value)

void	setOneReg (uint64_t id, uint32_t value)

void	getOneReg (uint64_t id, void *addr) const

uint64_t	getOneRegU64 (uint64_t id) const

uint32_t	getOneRegU32 (uint64_t id) const

void	syncThreadContext ()
	Update a thread context if the KVM state is dirty with respect to the cached thread context. More...

EventQueue *	deviceEventQueue ()
	Get a pointer to the event queue owning devices. More...

void	syncKvmState ()
	Update the KVM if the thread context is dirty. More...

virtual Tick	handleKvmExit ()
	Main kvmRun exit handler, calls the relevant handleKvmExit* depending on exit type. More...

virtual Tick	handleKvmExitIO ()
	The guest performed a legacy IO request (out/inp on x86) More...

virtual Tick	handleKvmExitHypercall ()
	The guest requested a monitor service using a hypercall. More...

virtual Tick	handleKvmExitIRQWindowOpen ()
	The guest exited because an interrupt window was requested. More...

virtual Tick	handleKvmExitUnknown ()
	An unknown architecture dependent error occurred when starting the vCPU. More...

virtual Tick	handleKvmExitException ()
	An unhandled virtualization exception occured. More...

virtual Tick	handleKvmExitFailEntry ()
	KVM failed to start the virtualized CPU. More...

void	setSignalMask (const sigset_t *mask)
	Set the signal mask used in kvmRun() More...

Protected Attributes
std::vector< ArmV8KvmCPU::MiscRegInfo >	sysRegMap
	Cached mapping between system registers in kvm and misc regs in gem5. More...

Protected Attributes inherited from gem5::BaseArmKvmCPU
bool	irqAsserted
	Cached state of the IRQ line. More...

bool	fiqAsserted
	Cached state of the FIQ line. More...

ArmInterruptPin *	virtTimerPin
	If the user-space GIC and the kernel-space timer are used simultaneously, set up this interrupt pin to forward interrupt from the timer to the GIC when timer IRQ level change is intercepted. More...

uint64_t	prevDeviceIRQLevel
	KVM records whether each in-kernel device IRQ is asserted or disasserted in the kvmRunState->s.regs.device_irq_level bit map, and guarantees at least one KVM exit when the level changes. More...

Protected Attributes inherited from gem5::BaseKvmCPU
Status	_status
	CPU run state. More...

KVMCpuPort	dataPort
	Port for data requests. More...

KVMCpuPort	instPort
	Unused dummy port for the instruction interface. More...

const bool	alwaysSyncTC
	Be conservative and always synchronize the thread context on KVM entry/exit. More...

bool	threadContextDirty
	Is the gem5 context dirty? Set to true to force an update of the KVM vCPU state upon the next call to kvmRun(). More...

bool	kvmStateDirty
	Is the KVM state dirty? Set to true to force an update of the KVM vCPU state upon the next call to kvmRun(). More...

const long	vcpuID
	KVM internal ID of the vCPU. More...

pthread_t	vcpuThread
	ID of the vCPU thread. More...

Static Protected Attributes
static const std::vector< ArmV8KvmCPU::IntRegInfo >	intRegMap
	Mapping between gem5 integer registers and integer registers in kvm. More...

static const std::vector< ArmV8KvmCPU::MiscRegInfo >	miscRegMap
	Mapping between gem5 misc registers and registers in kvm. More...

static const std::set< ArmISA::MiscRegIndex >	deviceRegSet
	Device registers (needing "effectful" MiscReg writes) More...

static const std::vector< ArmV8KvmCPU::MiscRegInfo >	miscRegIdMap
	Mapping between gem5 ID misc registers and registers in kvm. More...

Additional Inherited Members
Public Attributes inherited from gem5::BaseKvmCPU
SimpleThread *	thread
	A cached copy of a thread's state in the form of a SimpleThread object. More...

ThreadContext *	tc
	ThreadContext object, provides an interface for external objects to modify this thread's state. More...

KvmVM &	vm

gem5::BaseKvmCPU::StatGroup	stats

Counter	ctrInsts
	Number of instructions executed by the CPU. More...

Protected Types inherited from gem5::BaseArmKvmCPU
typedef std::vector< uint64_t >	RegIndexVector

Protected Types inherited from gem5::BaseKvmCPU
enum	Status { Idle, Running, RunningService, RunningMMIOPending, RunningServiceCompletion }

Detailed Description

This is an implementation of a KVM-based ARMv8-compatible CPU.

Known limitations:

The system-register-based generic timer can only be simulated by the host kernel. Workaround: Use a memory mapped timer instead to simulate the timer in gem5.
Simulating devices (e.g., the generic timer) in the host kernel requires that the host kernel also simulates the GIC.
ID registers in the host and in gem5 must match for switching between simulated CPUs and KVM. This is particularly important for ID registers describing memory system capabilities (e.g., ASID size, physical address size).
Switching between a virtualized CPU and a simulated CPU is currently not supported if in-kernel device emulation is used. This could be worked around by adding support for switching to the gem5 (e.g., the KvmGic) side of the device models. A simpler workaround is to avoid in-kernel device models altogether.

Definition at line 82 of file armv8_cpu.hh.

Constructor & Destructor Documentation

◆ ArmV8KvmCPU()

gem5::ArmV8KvmCPU::ArmV8KvmCPU ( const ArmV8KvmCPUParams & params )

Definition at line 132 of file armv8_cpu.cc.

◆ ~ArmV8KvmCPU()

gem5::ArmV8KvmCPU::~ArmV8KvmCPU ( )

virtual

Definition at line 137 of file armv8_cpu.cc.

Member Function Documentation

◆ dump()

void gem5::ArmV8KvmCPU::dump ( ) const

overridevirtual

Dump the internal state to the terminal.

Reimplemented from gem5::BaseKvmCPU.

Definition at line 155 of file armv8_cpu.cc.

References gem5::ArmISA::decodeAArch64SysReg(), EXTRACT_FIELD, gem5::BaseKvmCPU::getAndFormatOneReg(), gem5::BaseArmKvmCPU::getRegList(), gem5::ArmISA::i, gem5::ArmISA::id, inform, INT_REG, intRegMap, gem5::kvmFPReg(), gem5::kvmXReg(), miscRegIdMap, miscRegMap, gem5::ArmISA::miscRegName, gem5::NUM_QREGS, gem5::NUM_XREGS, gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::X86ISA::type, and gem5::X86ISA::val.

◆ getSysRegMap()

const std::vector< ArmV8KvmCPU::MiscRegInfo > & gem5::ArmV8KvmCPU::getSysRegMap ( ) const

protected

Get a map between system registers in kvm and gem5 registers.

This method returns a mapping between system registers in kvm and misc regs in gem5. The actual mapping is only created the first time the method is called and stored in a cache (ArmV8KvmCPU::sysRegMap).

Returns: Vector of kvm<->misc reg mappings.

Definition at line 369 of file armv8_cpu.cc.

References gem5::ArmISA::decodeAArch64SysReg(), deviceRegSet, EXTRACT_FIELD, gem5::BaseArmKvmCPU::getRegList(), gem5::ArmISA::MISCREG_HYP_NS_WR, gem5::ArmISA::MISCREG_IMPLEMENTED, gem5::ArmISA::MISCREG_MON_NS0_WR, gem5::ArmISA::MISCREG_MON_NS1_WR, gem5::ArmISA::MISCREG_PRI_NS_WR, gem5::ArmISA::MISCREG_PRI_S_WR, gem5::ArmISA::MISCREG_USR_NS_WR, gem5::ArmISA::MISCREG_USR_S_WR, gem5::ArmISA::MISCREG_WARN_NOT_FAIL, gem5::ArmISA::miscRegInfo, gem5::ArmISA::miscRegName, gem5::X86ISA::reg, sysRegMap, and gem5::X86ISA::type.

Referenced by updateKvmState(), and updateThreadContext().

◆ startup()

void gem5::ArmV8KvmCPU::startup ( )

override

Definition at line 142 of file armv8_cpu.cc.

References DPRINTF, miscRegIdMap, gem5::ThreadContext::readMiscReg(), gem5::PowerISA::ri, gem5::BaseKvmCPU::setOneReg(), gem5::BaseArmKvmCPU::startup(), and gem5::BaseKvmCPU::tc.

◆ updateKvmState()

void gem5::ArmV8KvmCPU::updateKvmState ( )

overrideprotectedvirtual

Update the KVM state from the current thread context.

The base CPU calls this method before starting the guest CPU when the contextDirty flag is set. The architecture dependent CPU implementation is expected to update all guest state (registers, special registers, and FPU state).

Implements gem5::BaseKvmCPU.

Definition at line 222 of file armv8_cpu.cc.

References gem5::ArmISA::CCREG_C, gem5::ArmISA::CCREG_GE, gem5::ArmISA::CCREG_NZ, gem5::ArmISA::CCREG_V, gem5::BaseKvmCPU::deviceEventQueue(), DPRINTF, FP_REGS_PER_VFP_REG, gem5::BaseKvmCPU::getAndFormatOneReg(), getSysRegMap(), gem5::ArmISA::i, gem5::ArmISA::inAArch64(), gem5::PCStateBase::instAddr(), INT_REG, intRegMap, gem5::ArmISA::j, gem5::kvmFPReg(), gem5::kvmXReg(), gem5::ArmISA::MISCREG_CPSR, miscRegMap, gem5::NUM_QREGS, gem5::NUM_XREGS, gem5::ThreadContext::pcState(), gem5::ThreadContext::readCCReg(), gem5::ThreadContext::readIntReg(), gem5::ThreadContext::readMiscReg(), gem5::ThreadContext::readVecReg(), gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::BaseKvmCPU::setOneReg(), gem5::ArmISA::syncVecElemsToRegs(), gem5::BaseKvmCPU::tc, gem5::ArmISA::v, and gem5::VecRegClass.

◆ updateThreadContext()

void gem5::ArmV8KvmCPU::updateThreadContext ( )

overrideprotectedvirtual

Update the current thread context with the KVM state.

The base CPU after the guest updates any of the KVM state. In practice, this happens after kvmRun is called. The architecture dependent code is expected to read the state of the guest CPU and update gem5's thread state.

Implements gem5::BaseKvmCPU.

Definition at line 290 of file armv8_cpu.cc.

References gem5::ArmISA::CCREG_C, gem5::ArmISA::CCREG_GE, gem5::ArmISA::CCREG_NZ, gem5::ArmISA::CCREG_V, gem5::BaseKvmCPU::deviceEventQueue(), DPRINTF, FP_REGS_PER_VFP_REG, gem5::BaseKvmCPU::getAndFormatOneReg(), gem5::BaseKvmCPU::getOneReg(), gem5::BaseKvmCPU::getOneRegU64(), getSysRegMap(), gem5::ThreadContext::getWritableVecReg(), gem5::ArmISA::i, gem5::ArmISA::inAArch64(), INT_REG, gem5::ArmISA::IntReg64Map, intRegMap, gem5::ArmISA::j, gem5::kvmFPReg(), gem5::kvmXReg(), gem5::ArmISA::MISCREG_CPSR, miscRegMap, gem5::NUM_QREGS, gem5::NUM_XREGS, gem5::MipsISA::pc, gem5::ThreadContext::pcState(), gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::ThreadContext::setCCReg(), gem5::ThreadContext::setIntReg(), gem5::ThreadContext::setIntRegFlat(), gem5::ThreadContext::setMiscReg(), gem5::ThreadContext::setMiscRegNoEffect(), gem5::ArmISA::syncVecRegsToElems(), gem5::BaseKvmCPU::tc, gem5::ArmISA::v, and gem5::VecRegClass.

Member Data Documentation

◆ deviceRegSet

const std::set< MiscRegIndex > gem5::ArmV8KvmCPU::deviceRegSet

staticprotected

Initial value:

= {
    MISCREG_CNTV_CTL_EL0,
    MISCREG_CNTV_CVAL_EL0,
    MISCREG_CNTKCTL_EL1,
}

Device registers (needing "effectful" MiscReg writes)

Definition at line 145 of file armv8_cpu.hh.

Referenced by getSysRegMap().

◆ intRegMap

const std::vector< ArmV8KvmCPU::IntRegInfo > gem5::ArmV8KvmCPU::intRegMap

staticprotected

Initial value:

= {
    { INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" },
    { INT_REG(sp_el1), INTREG_SP1, "SP(EL1)" },
}

Mapping between gem5 integer registers and integer registers in kvm.

Definition at line 141 of file armv8_cpu.hh.

Referenced by dump(), updateKvmState(), and updateThreadContext().

◆ miscRegIdMap

const std::vector< ArmV8KvmCPU::MiscRegInfo > gem5::ArmV8KvmCPU::miscRegIdMap

staticprotected

Initial value:

= {
    MiscRegInfo(SYS_MPIDR_EL1, MISCREG_MPIDR_EL1, "MPIDR(EL1)"),
}

Mapping between gem5 ID misc registers and registers in kvm.

Definition at line 147 of file armv8_cpu.hh.

Referenced by dump(), and startup().

◆ miscRegMap

const std::vector< ArmV8KvmCPU::MiscRegInfo > gem5::ArmV8KvmCPU::miscRegMap

staticprotected

Initial value:

= {
    MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]), MISCREG_SPSR_EL1, "SPSR(EL1)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]), MISCREG_SPSR_ABT, "SPSR(ABT)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"),
    MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"),
    MiscRegInfo(CORE_REG(fp_regs.fpsr, U32), MISCREG_FPSR, "FPSR"),
    MiscRegInfo(CORE_REG(fp_regs.fpcr, U32), MISCREG_FPCR, "FPCR"),
}

Mapping between gem5 misc registers and registers in kvm.

Definition at line 143 of file armv8_cpu.hh.

Referenced by dump(), updateKvmState(), and updateThreadContext().

◆ sysRegMap

std::vector<ArmV8KvmCPU::MiscRegInfo> gem5::ArmV8KvmCPU::sysRegMap

mutableprotected

Cached mapping between system registers in kvm and misc regs in gem5.

Definition at line 150 of file armv8_cpu.hh.

Referenced by getSysRegMap().

The documentation for this class was generated from the following files:

arch/arm/kvm/armv8_cpu.hh
arch/arm/kvm/armv8_cpu.cc

Classes

Public Member Functions

Protected Member Functions

Protected Attributes

Static Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ ArmV8KvmCPU()

◆ ~ArmV8KvmCPU()

Member Function Documentation

◆ dump()

◆ getSysRegMap()

◆ startup()

◆ updateKvmState()

◆ updateThreadContext()

Member Data Documentation

◆ deviceRegSet

◆ intRegMap

◆ miscRegIdMap

◆ miscRegMap

◆ sysRegMap