The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface. More...

#include <simple_thread.hh>

Inheritance diagram for gem5::SimpleThread:

Public Types
typedef ThreadContext::Status	Status

Public Types inherited from gem5::ThreadState
typedef ThreadContext::Status	Status

Public Types inherited from gem5::ThreadContext
enum	Status { Active, Suspended, Halting, Halted }

Public Member Functions
std::string	name () const

	SimpleThread (BaseCPU _cpu, int _thread_num, System _system, BaseMMU _mmu, BaseISA _isa, InstDecoder *_decoder)

	SimpleThread (BaseCPU _cpu, int _thread_num, System _system, Process _process, BaseMMU _mmu, BaseISA _isa, InstDecoder _decoder)

virtual	~SimpleThread ()

void	takeOverFrom (ThreadContext *oldContext) override

void	copyState (ThreadContext *oldContext)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

ThreadContext *	getTC ()
	Returns the pointer to this SimpleThread's ThreadContext. More...

void	demapPage (Addr vaddr, uint64_t asn)

bool	schedule (PCEvent *e) override

bool	remove (PCEvent *e) override

void	scheduleInstCountEvent (Event *event, Tick count) override

void	descheduleInstCountEvent (Event *event) override

Tick	getCurrentInstCount () override

BaseCPU *	getCpuPtr () override

int	cpuId () const override

uint32_t	socketId () const override

int	threadId () const override

void	setThreadId (int id) override

ContextID	contextId () const override

void	setContextId (ContextID id) override

BaseMMU *	getMMUPtr () override

CheckerCPU *	getCheckerCpuPtr () override

BaseISA *	getIsaPtr () const override

InstDecoder *	getDecoderPtr () override

System *	getSystemPtr () override

Process *	getProcessPtr () override

void	setProcessPtr (Process *p) override

Status	status () const override

void	setStatus (Status newStatus) override

void	activate () override
	Set the status to Active. More...

void	suspend () override
	Set the status to Suspended. More...

void	halt () override
	Set the status to Halted. More...

Tick	readLastActivate () override

Tick	readLastSuspend () override

void	copyArchRegs (ThreadContext *tc) override

void	clearArchRegs () override

const PCStateBase &	pcState () const override

void	pcState (const PCStateBase &val) override

void	pcStateNoRecord (const PCStateBase &val) override

bool	readPredicate () const

void	setPredicate (bool val)

RegVal	readMiscRegNoEffect (RegIndex misc_reg) const override

RegVal	readMiscReg (RegIndex misc_reg) override

void	setMiscRegNoEffect (RegIndex misc_reg, RegVal val) override

void	setMiscReg (RegIndex misc_reg, RegVal val) override

RegId	flattenRegId (const RegId &regId) const override

unsigned	readStCondFailures () const override

bool	readMemAccPredicate ()

void	setMemAccPredicate (bool val)

void	setStCondFailures (unsigned sc_failures) override

RegVal	getReg (const RegId &arch_reg) const override

RegVal	getRegFlat (const RegId &reg) const override
	Flat register interfaces. More...

void	getReg (const RegId &arch_reg, void *val) const override

void	getRegFlat (const RegId &reg, void *val) const override

void *	getWritableReg (const RegId &arch_reg) override

void *	getWritableRegFlat (const RegId &reg) override

void	setReg (const RegId &arch_reg, RegVal val) override

void	setRegFlat (const RegId &reg, RegVal val) override

void	setReg (const RegId &arch_reg, const void *val) override

void	setRegFlat (const RegId &reg, const void *val) override

void	htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override

BaseHTMCheckpointPtr &	getHtmCheckpointPtr () override

void	setHtmCheckpointPtr (BaseHTMCheckpointPtr new_cpt) override

Public Member Functions inherited from gem5::ThreadState
	ThreadState (BaseCPU cpu, ThreadID _tid, Process _process)

virtual	~ThreadState ()=default

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

int	cpuId () const

uint32_t	socketId () const

ContextID	contextId () const

void	setContextId (ContextID id)

void	setThreadId (ThreadID id)

ThreadID	threadId () const

Tick	readLastActivate () const

Tick	readLastSuspend () const

Process *	getProcessPtr ()

void	setProcessPtr (Process *p)

Status	status () const
	Returns the status of this thread. More...

void	setStatus (Status new_status)
	Sets the status of this thread. More...

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::ThreadContext
bool	getUseForClone ()

void	setUseForClone (bool new_val)

virtual	~ThreadContext ()

virtual void	sendFunctional (PacketPtr pkt)

void	quiesce ()
	Quiesce thread context. More...

void	quiesceTick (Tick resume)
	Quiesce, suspend, and schedule activate at resume. More...

virtual void	regStats (const std::string &name)

RegVal	readIntReg (RegIndex reg_idx) const

RegVal	readFloatReg (RegIndex reg_idx) const

TheISA::VecRegContainer	readVecReg (const RegId &reg) const

TheISA::VecRegContainer &	getWritableVecReg (const RegId &reg)

RegVal	readVecElem (const RegId &reg) const

RegVal	readCCReg (RegIndex reg_idx) const

void	setIntReg (RegIndex reg_idx, RegVal val)

void	setFloatReg (RegIndex reg_idx, RegVal val)

void	setVecReg (const RegId &reg, const TheISA::VecRegContainer &val)

void	setVecElem (const RegId &reg, RegVal val)

void	setCCReg (RegIndex reg_idx, RegVal val)

void	pcState (Addr addr)

virtual int	exit ()

RegVal	readIntRegFlat (RegIndex idx) const

void	setIntRegFlat (RegIndex idx, RegVal val)

RegVal	readFloatRegFlat (RegIndex idx) const

void	setFloatRegFlat (RegIndex idx, RegVal val)

TheISA::VecRegContainer	readVecRegFlat (RegIndex idx) const

TheISA::VecRegContainer &	getWritableVecRegFlat (RegIndex idx)

void	setVecRegFlat (RegIndex idx, const TheISA::VecRegContainer &val)

RegVal	readVecElemFlat (RegIndex idx) const

void	setVecElemFlat (RegIndex idx, RegVal val)

RegVal	readCCRegFlat (RegIndex idx) const

void	setCCRegFlat (RegIndex idx, RegVal val)

Public Attributes
PCEventQueue	pcEventQueue

EventQueue	comInstEventQueue
	An instruction-based event queue. More...

System *	system

BaseMMU *	mmu

InstDecoder *	decoder

int64_t	htmTransactionStarts

int64_t	htmTransactionStops

Public Attributes inherited from gem5::ThreadState
Counter	numInst
	Number of instructions committed. More...

Counter	numOp
	Number of ops (including micro ops) committed. More...

gem5::ThreadState::ThreadStateStats	threadStats

Counter	numLoad
	Number of simulated loads, used for tracking events based on the number of loads committed. More...

Counter	startNumLoad
	The number of simulated loads committed prior to this run. More...

Tick	lastActivate
	Last time activate was called on this thread. More...

Tick	lastSuspend
	Last time suspend was called on this thread. More...

unsigned	storeCondFailures

Public Attributes inherited from gem5::ThreadContext
int	intResult = DefaultIntResult

double	floatResult = DefaultFloatResult

int	intOffset = 0

Protected Attributes
std::array< RegFile, CCRegClass+1 >	regFiles

TheISA::ISA *const	isa

std::unique_ptr< PCStateBase >	_pcState

std::unique_ptr< BaseHTMCheckpoint >	_htmCheckpoint

bool	predicate
	Did this instruction execute or is it predicated false. More...

bool	memAccPredicate
	True if the memory access should be skipped for this instruction. More...

Protected Attributes inherited from gem5::ThreadState
ThreadContext::Status	_status

BaseCPU *	baseCpu

ContextID	_contextId

ThreadID	_threadId

Process *	process

Protected Attributes inherited from gem5::ThreadContext
bool	useForClone = false

Additional Inherited Members
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Static Public Member Functions inherited from gem5::ThreadContext
static void	compare (ThreadContext one, ThreadContext two)
	function to compare two thread contexts (for debugging) More...

Static Public Attributes inherited from gem5::ThreadContext
static const int	ints []

static const double	floats []

static const int	DefaultIntResult = 0

static const double	DefaultFloatResult = 0.0

Detailed Description

The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface.

It implements the ThreadContext interface and adds to the ThreadState object by adding all the objects needed for simple functional execution, including a simple architectural register file, and pointers to the ITB and DTB in full system mode. For CPU models that do not need more advanced ways to hold state (i.e. a separate physical register file, or separate fetch and commit PC's), this SimpleThread class provides all the necessary state for full architecture-level functional simulation. See the AtomicSimpleCPU or TimingSimpleCPU for examples.

Definition at line 95 of file simple_thread.hh.

Member Typedef Documentation

◆ Status

typedef ThreadContext::Status gem5::SimpleThread::Status

Definition at line 98 of file simple_thread.hh.

Constructor & Destructor Documentation

◆ SimpleThread() [1/2]

gem5::SimpleThread::SimpleThread	(	BaseCPU *	_cpu,
		int	_thread_num,
		System *	_system,
		BaseMMU *	_mmu,
		BaseISA *	_isa,
		InstDecoder *	_decoder
	)

Definition at line 90 of file simple_thread.cc.

◆ SimpleThread() [2/2]

gem5::SimpleThread::SimpleThread	(	BaseCPU *	_cpu,
		int	_thread_num,
		System *	_system,
		Process *	_process,
		BaseMMU *	_mmu,
		BaseISA *	_isa,
		InstDecoder *	_decoder
	)

Definition at line 69 of file simple_thread.cc.

References gem5::CCRegClass, gem5::FloatRegClass, gem5::IntRegClass, gem5::BaseISA::regClasses(), gem5::VecElemClass, gem5::VecPredRegClass, and gem5::VecRegClass.

◆ ~SimpleThread()

virtual gem5::SimpleThread::~SimpleThread ( )

inlinevirtual

Definition at line 149 of file simple_thread.hh.

Member Function Documentation

◆ activate()

void gem5::SimpleThread::activate ( )

overridevirtual

Set the status to Active.

Public Types

Public Member Functions

Public Attributes

Protected Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ Status

Constructor & Destructor Documentation

◆ SimpleThread() [1/2]

◆ SimpleThread() [2/2]

◆ ~SimpleThread()

Member Function Documentation

◆ activate()

◆ clearArchRegs()

◆ contextId()

◆ copyArchRegs()

◆ copyState()

◆ cpuId()

◆ demapPage()

◆ descheduleInstCountEvent()

◆ flattenRegId()

◆ getCheckerCpuPtr()

◆ getCpuPtr()

◆ getCurrentInstCount()

◆ getDecoderPtr()

◆ getHtmCheckpointPtr()

◆ getIsaPtr()

◆ getMMUPtr()

◆ getProcessPtr()

◆ getReg() [1/2]

◆ getReg() [2/2]

◆ getRegFlat() [1/2]

◆ getRegFlat() [2/2]

◆ getSystemPtr()

◆ getTC()

◆ getWritableReg()

◆ getWritableRegFlat()

◆ halt()

◆ htmAbortTransaction()

◆ name()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ pcStateNoRecord()

◆ readLastActivate()

◆ readLastSuspend()

◆ readMemAccPredicate()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ readPredicate()

◆ readStCondFailures()

◆ remove()

◆ schedule()

◆ scheduleInstCountEvent()

◆ serialize()

◆ setContextId()

◆ setHtmCheckpointPtr()

◆ setMemAccPredicate()

◆ setMiscReg()

◆ setMiscRegNoEffect()

◆ setPredicate()

◆ setProcessPtr()

◆ setReg() [1/2]

◆ setReg() [2/2]

◆ setRegFlat() [1/2]

◆ setRegFlat() [2/2]

◆ setStatus()

◆ setStCondFailures()

◆ setThreadId()

◆ socketId()

◆ status()

◆ suspend()

◆ takeOverFrom()

◆ threadId()

◆ unserialize()

Member Data Documentation

◆ _htmCheckpoint

◆ _pcState

◆ comInstEventQueue

◆ decoder