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isa.cc
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37 
38 #include "arch/arm/isa.hh"
39 
40 #include "arch/arm/decoder.hh"
41 #include "arch/arm/faults.hh"
42 #include "arch/arm/htm.hh"
43 #include "arch/arm/interrupts.hh"
44 #include "arch/arm/mmu.hh"
45 #include "arch/arm/pmu.hh"
46 #include "arch/arm/regs/misc.hh"
47 #include "arch/arm/self_debug.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/utility.hh"
50 #include "arch/generic/decoder.hh"
51 #include "base/cprintf.hh"
52 #include "cpu/base.hh"
53 #include "cpu/checker/cpu.hh"
54 #include "cpu/reg_class.hh"
55 #include "debug/Arm.hh"
56 #include "debug/CCRegs.hh"
57 #include "debug/FloatRegs.hh"
58 #include "debug/IntRegs.hh"
59 #include "debug/LLSC.hh"
60 #include "debug/MiscRegs.hh"
61 #include "debug/VecPredRegs.hh"
62 #include "debug/VecRegs.hh"
63 #include "dev/arm/generic_timer.hh"
64 #include "dev/arm/gic_v3.hh"
65 #include "dev/arm/gic_v3_cpu_interface.hh"
66 #include "params/ArmISA.hh"
67 #include "sim/faults.hh"
68 #include "sim/stat_control.hh"
69 #include "sim/system.hh"
70 
71 namespace gem5
72 {
73 
74 namespace ArmISA
75 {
76 
77 class MiscRegClassOps : public RegClassOps
78 {
79  public:
80  std::string
81  regName(const RegId &id) const override
82  {
83  return miscRegName[id.index()];
84  }
85 } miscRegClassOps;
86 
87 VecElemRegClassOps<ArmISA::VecElem> vecRegElemClassOps(NumVecElemPerVecReg);
88 TypedRegClassOps<ArmISA::VecRegContainer> vecRegClassOps;
89 TypedRegClassOps<ArmISA::VecPredRegContainer> vecPredRegClassOps;
90 
91 ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
92  _decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
93  afterStartup(false)
94 {
95  _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
96  _regClasses.emplace_back(0, debug::FloatRegs);
97  _regClasses.emplace_back(NumVecRegs, vecRegClassOps, debug::VecRegs,
98  sizeof(VecRegContainer));
99  _regClasses.emplace_back(NumVecRegs * NumVecElemPerVecReg,
100  vecRegElemClassOps, debug::VecRegs);
101  _regClasses.emplace_back(NumVecPredRegs, vecPredRegClassOps,
102  debug::VecPredRegs, sizeof(VecPredRegContainer));
103  _regClasses.emplace_back(cc_reg::NumRegs, debug::CCRegs);
104  _regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps, debug::MiscRegs);
105 
106  miscRegs[MISCREG_SCTLR_RST] = 0;
107 
108  // Hook up a dummy device if we haven't been configured with a
109  // real PMU. By using a dummy device, we don't need to check that
110  // the PMU exist every time we try to access a PMU register.
111  if (!pmu)
112  pmu = &dummyDevice;
113 
114  // Give all ISA devices a pointer to this ISA
115  pmu->setISA(this);
116 
117  system = dynamic_cast<ArmSystem *>(p.system);
118 
119  // Cache system-level properties
120  if (FullSystem && system) {
121  highestELIs64 = system->highestELIs64();
122  haveLargeAsid64 = system->haveLargeAsid64();
123  physAddrRange = system->physAddrRange();
124  sveVL = system->sveVL();
125 
126  release = system->releaseFS();
127  } else {
128  highestELIs64 = true; // ArmSystem::highestELIs64 does the same
129  haveLargeAsid64 = false;
130  physAddrRange = 32; // dummy value
131  sveVL = p.sve_vl_se;
132 
133  release = p.release_se;
134  }
135 
136  selfDebug = new SelfDebug();
137  initializeMiscRegMetadata();
138  preUnflattenMiscReg();
139 
140  clear();
141 }
142 
143 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
144 
145 void
146 ISA::clear()
147 {
148  const Params &p(params());
149 
150  // Invalidate cached copies of miscregs in the TLBs
151  if (tc) {
152  getMMUPtr(tc)->invalidateMiscReg();
153  }
154 
155  SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
156  memset(miscRegs, 0, sizeof(miscRegs));
157 
158  initID32(p);
159 
160  // We always initialize AArch64 ID registers even
161  // if we are in AArch32. This is done since if we
162  // are in SE mode we don't know if our ArmProcess is
163  // AArch32 or AArch64
164  initID64(p);
165 
166  // Start with an event in the mailbox
167  miscRegs[MISCREG_SEV_MAILBOX] = 1;
168 
169  // Separate Instruction and Data TLBs
170  miscRegs[MISCREG_TLBTR] = 1;
171 
172  MVFR0 mvfr0 = 0;
173  mvfr0.advSimdRegisters = 2;
174  mvfr0.singlePrecision = 2;
175  mvfr0.doublePrecision = 2;
176  mvfr0.vfpExceptionTrapping = 0;
177  mvfr0.divide = 1;
178  mvfr0.squareRoot = 1;
179  mvfr0.shortVectors = 1;
180  mvfr0.roundingModes = 1;
181  miscRegs[MISCREG_MVFR0] = mvfr0;
182 
183  MVFR1 mvfr1 = 0;
184  mvfr1.flushToZero = 1;
185  mvfr1.defaultNaN = 1;
186  mvfr1.advSimdLoadStore = 1;
187  mvfr1.advSimdInteger = 1;
188  mvfr1.advSimdSinglePrecision = 1;
189  mvfr1.advSimdHalfPrecision = 1;
190  mvfr1.vfpHalfPrecision = 1;
191  miscRegs[MISCREG_MVFR1] = mvfr1;
192 
193  // Reset values of PRRR and NMRR are implementation dependent
194 
195  // @todo: PRRR and NMRR in secure state?
196  miscRegs[MISCREG_PRRR_NS] =
197  (1 << 19) | // 19
198  (0 << 18) | // 18
199  (0 << 17) | // 17
200  (1 << 16) | // 16
201  (2 << 14) | // 15:14
202  (0 << 12) | // 13:12
203  (2 << 10) | // 11:10
204  (2 << 8) | // 9:8
205  (2 << 6) | // 7:6
206  (2 << 4) | // 5:4
207  (1 << 2) | // 3:2
208  0; // 1:0
209 
210  miscRegs[MISCREG_NMRR_NS] =
211  (1 << 30) | // 31:30
212  (0 << 26) | // 27:26
213  (0 << 24) | // 25:24
214  (3 << 22) | // 23:22
215  (2 << 20) | // 21:20
216  (0 << 18) | // 19:18
217  (0 << 16) | // 17:16
218  (1 << 14) | // 15:14
219  (0 << 12) | // 13:12
220  (2 << 10) | // 11:10
221  (0 << 8) | // 9:8
222  (3 << 6) | // 7:6
223  (2 << 4) | // 5:4
224  (0 << 2) | // 3:2
225  0; // 1:0
226 
227  if (FullSystem && system->highestELIs64()) {
228  // Initialize AArch64 state
229  clear64(p);
230  return;
231  }
232 
233  // Initialize AArch32 state...
234  clear32(p, sctlr_rst);
235 }
236 
237 void
238 ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
239 {
240  CPSR cpsr = 0;
241  cpsr.mode = MODE_USER;
242 
243  if (FullSystem) {
244  miscRegs[MISCREG_MVBAR] = system->resetAddr();
245  }
246 
247  miscRegs[MISCREG_CPSR] = cpsr;
248  updateRegMap(cpsr);
249 
250  SCTLR sctlr = 0;
251  sctlr.te = (bool) sctlr_rst.te;
252  sctlr.nmfi = (bool) sctlr_rst.nmfi;
253  sctlr.v = (bool) sctlr_rst.v;
254  sctlr.u = 1;
255  sctlr.xp = 1;
256  sctlr.rao2 = 1;
257  sctlr.rao3 = 1;
258  sctlr.rao4 = 0xf; // SCTLR[6:3]
259  sctlr.uci = 1;
260  sctlr.dze = 1;
261  miscRegs[MISCREG_SCTLR_NS] = sctlr;
262  miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
263  miscRegs[MISCREG_HCPTR] = 0;
264 
265  miscRegs[MISCREG_CPACR] = 0;
266 
267  miscRegs[MISCREG_FPSID] = p.fpsid;
268 
269  if (release->has(ArmExtension::LPAE)) {
270  TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
271  ttbcr.eae = 0;
272  miscRegs[MISCREG_TTBCR_NS] = ttbcr;
273  // Enforce consistency with system-level settings
274  miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
275  }
276 
277  if (release->has(ArmExtension::SECURITY)) {
278  miscRegs[MISCREG_SCTLR_S] = sctlr;
279  miscRegs[MISCREG_SCR] = 0;
280  miscRegs[MISCREG_VBAR_S] = 0;
281  } else {
282  // we're always non-secure
283  miscRegs[MISCREG_SCR] = 1;
284  }
285 
286  //XXX We need to initialize the rest of the state.
287 }
288 
289 void
290 ISA::clear64(const ArmISAParams &p)
291 {
292  CPSR cpsr = 0;
293  Addr rvbar = system->resetAddr();
294  switch (system->highestEL()) {
295  // Set initial EL to highest implemented EL using associated stack
296  // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
297  // value
298  case EL3:
299  cpsr.mode = MODE_EL3H;
300  miscRegs[MISCREG_RVBAR_EL3] = rvbar;
301  break;
302  case EL2:
303  cpsr.mode = MODE_EL2H;
304  miscRegs[MISCREG_RVBAR_EL2] = rvbar;
305  break;
306  case EL1:
307  cpsr.mode = MODE_EL1H;
308  miscRegs[MISCREG_RVBAR_EL1] = rvbar;
309  break;
310  default:
311  panic("Invalid highest implemented exception level");
312  break;
313  }
314 
315  // Initialize rest of CPSR
316  cpsr.daif = 0xf; // Mask all interrupts
317  cpsr.ss = 0;
318  cpsr.il = 0;
319  miscRegs[MISCREG_CPSR] = cpsr;
320  updateRegMap(cpsr);
321 
322  // Initialize other control registers
323  miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
324  if (release->has(ArmExtension::SECURITY)) {
325  miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
326  miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
327  } else if (release->has(ArmExtension::VIRTUALIZATION)) {
328  // also MISCREG_SCTLR_EL2 (by mapping)
329  miscRegs[MISCREG_HSCTLR] = 0x30c50830;
330  } else {
331  // also MISCREG_SCTLR_EL1 (by mapping)
332  miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
333  // Always non-secure
334  miscRegs[MISCREG_SCR_EL3] = 1;
335  }
336 }
337 
338 void
339 ISA::initID32(const ArmISAParams &p)
340 {
341  // Initialize configurable default values
342 
343  uint32_t midr;
344  if (p.midr != 0x0)
345  midr = p.midr;
346  else if (highestELIs64)
347  // Cortex-A57 TRM r0p0 MIDR
348  midr = 0x410fd070;
349  else
350  // Cortex-A15 TRM r0p0 MIDR
351  midr = 0x410fc0f0;
352 
353  miscRegs[MISCREG_MIDR] = midr;
354  miscRegs[MISCREG_MIDR_EL1] = midr;
355  miscRegs[MISCREG_VPIDR] = midr;
356 
357  miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
358  miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
359  miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
360  miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
361  miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
362  miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
363  miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
364 
365  miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
366  miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
367  miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
368  miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
369  miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
370 
372  // Crypto
373  miscRegs[MISCREG_ID_ISAR5] = insertBits(
374  miscRegs[MISCREG_ID_ISAR5], 19, 4,
375  release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
376  // RDM
377  miscRegs[MISCREG_ID_ISAR5] = insertBits(
378  miscRegs[MISCREG_ID_ISAR5], 27, 24,
379  release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
380  // FCMA
381  miscRegs[MISCREG_ID_ISAR5] = insertBits(
382  miscRegs[MISCREG_ID_ISAR5], 31, 28,
383  release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
384 
386  miscRegs[MISCREG_ID_ISAR6] = insertBits(
387  miscRegs[MISCREG_ID_ISAR6], 3, 0,
388  release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
389 }
390 
391 void
392 ISA::initID64(const ArmISAParams &p)
393 {
394  // Initialize configurable id registers
395  miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
396  miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
397  miscRegs[MISCREG_ID_AA64DFR0_EL1] =
398  (p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
399  (p.pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
400 
401  miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
402  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1;
403  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1;
404  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1;
405  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
406  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
407 
408  miscRegs[MISCREG_ID_DFR0_EL1] =
409  (p.pmu ? 0x03000000ULL : 0); // Enable PMUv3
410 
411  miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
412 
413  // SVE
414  miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
415  if (release->has(ArmExtension::SECURITY)) {
416  miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
417  } else if (release->has(ArmExtension::VIRTUALIZATION)) {
418  miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
419  } else {
420  miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
421  }
422 
423  // Enforce consistency with system-level settings...
424 
425  // EL3
426  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
427  miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
428  release->has(ArmExtension::SECURITY) ? 0x2 : 0x0);
429  // EL2
430  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
431  miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
432  release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0);
433  // SVE
434  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
435  miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
436  release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0);
437  // SecEL2
438  miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
439  miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
440  release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0);
441 
442  // Large ASID support
443  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
444  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
445  haveLargeAsid64 ? 0x2 : 0x0);
446  // Physical address size
447  miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
448  miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
449  encodePhysAddrRange64(physAddrRange));
450 
452  // Crypto
453  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
454  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
455  release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
456  // LSE
457  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
458  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
459  release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0);
460  // RDM
461  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
462  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 31, 28,
463  release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
464 
466  // PAuth, APA
467  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
468  miscRegs[MISCREG_ID_AA64ISAR1_EL1], 7, 4,
469  release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
470  // JSCVT
471  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
472  miscRegs[MISCREG_ID_AA64ISAR1_EL1], 15, 12,
473  release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
474  // FCMA
475  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
476  miscRegs[MISCREG_ID_AA64ISAR1_EL1], 19, 16,
477  release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
478  // PAuth, GPA
479  miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
480  miscRegs[MISCREG_ID_AA64ISAR1_EL1], 27, 24,
481  release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
482 
484  // VMID16
485  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
486  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 7, 4,
487  release->has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0);
488  // VHE
489  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
490  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
491  release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0);
492  // HPDS
493  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
494  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 15, 12,
495  release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0);
496  // PAN
497  miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
498  miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
499  release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);
500 
502  // UAO
503  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
504  miscRegs[MISCREG_ID_AA64MMFR2_EL1], 7, 4,
505  release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0);
506  // LVA
507  miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
508  miscRegs[MISCREG_ID_AA64MMFR2_EL1], 19, 16,
509  release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0);
510 
511 
512  // TME
513  miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
514  miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,
515  release->has(ArmExtension::TME) ? 0x1 : 0x0);
516 }
517 
518 void
519 ISA::startup()
520 {
521  BaseISA::startup();
522 
523  if (tc) {
524  setupThreadContext();
525 
526  if (release->has(ArmExtension::TME)) {
527  std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
528  tc->setHtmCheckpointPtr(std::move(cpt));
529  }
530  }
531 
532  afterStartup = true;
533 }
534 
535 void
536 ISA::setupThreadContext()
537 {
538  pmu->setThreadContext(tc);
539 
540  if (!system)
541  return;
542 
543  selfDebug->init(tc);
544 
545  Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
546  if (!gicv3)
547  return;
548 
549  if (!gicv3CpuInterface)
550  gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
551 
552  gicv3CpuInterface->setISA(this);
553  gicv3CpuInterface->setThreadContext(tc);
554 }
555 
556 void
557 ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
558 {
559  tc = new_tc;
560  setupThreadContext();
561 }
562 
563 void
564 ISA::copyRegsFrom(ThreadContext *src)
565 {
566  for (int i = 0; i < int_reg::NumRegs; i++) {
567  RegId reg(IntRegClass, i);
568  tc->setRegFlat(reg, src->getRegFlat(reg));
569  }
570 
571  for (int i = 0; i < cc_reg::NumRegs; i++) {
572  RegId reg(CCRegClass, i);
573  tc->setReg(reg, src->getReg(reg));
574  }
575 
576  for (int i = 0; i < NUM_MISCREGS; i++)
577  tc->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
578 
579  ArmISA::VecRegContainer vc;
580  for (int i = 0; i < NumVecRegs; i++) {
581  RegId reg(VecRegClass, i);
582  src->getRegFlat(reg, &vc);
583  tc->setRegFlat(reg, &vc);
584  }
585 
586  for (int i = 0; i < NumVecRegs * NumVecElemPerVecReg; i++) {
587  RegId reg(VecElemClass, i);
588  tc->setRegFlat(reg, src->getRegFlat(reg));
589  }
590 
591  // setMiscReg "with effect" will set the misc register mapping correctly.
592  // e.g. updateRegMap(val)
593  tc->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
594 
595  // Copy over the PC State
596  tc->pcState(src->pcState());
597 
598  // Invalidate the tlb misc register cache
599  static_cast<MMU *>(tc->getMMUPtr())->invalidateMiscReg();
600 }
601 
606 int
607 ISA::redirectRegVHE(int misc_reg)
608 {
609  const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
610  if (hcr.e2h == 0x0)
611  return misc_reg;
612  SCR scr = readMiscRegNoEffect(MISCREG_SCR_EL3);
613  bool sec_el2 = scr.eel2 && release->has(ArmExtension::FEAT_SEL2);
614  switch(misc_reg) {
615  case MISCREG_SPSR_EL1:
616  return currEL() == EL2 ? MISCREG_SPSR_EL2 : misc_reg;
617  case MISCREG_ELR_EL1:
618  return currEL() == EL2 ? MISCREG_ELR_EL2 : misc_reg;
619  case MISCREG_SCTLR_EL1:
620  return currEL() == EL2 ? MISCREG_SCTLR_EL2 : misc_reg;
621  case MISCREG_CPACR_EL1:
622  return currEL() == EL2 ? MISCREG_CPTR_EL2 : misc_reg;
623 // case MISCREG_TRFCR_EL1:
624 // return currEL() == EL2 ? MISCREG_TRFCR_EL2 : misc_reg;
625  case MISCREG_TTBR0_EL1:
626  return currEL() == EL2 ? MISCREG_TTBR0_EL2 : misc_reg;
627  case MISCREG_TTBR1_EL1:
628  return currEL() == EL2 ? MISCREG_TTBR1_EL2 : misc_reg;
629  case MISCREG_TCR_EL1:
630  return currEL() == EL2 ? MISCREG_TCR_EL2 : misc_reg;
631  case MISCREG_AFSR0_EL1:
632  return currEL() == EL2 ? MISCREG_AFSR0_EL2 : misc_reg;
633  case MISCREG_AFSR1_EL1:
634  return currEL() == EL2 ? MISCREG_AFSR1_EL2 : misc_reg;
635  case MISCREG_ESR_EL1:
636  return currEL() == EL2 ? MISCREG_ESR_EL2 : misc_reg;
637  case MISCREG_FAR_EL1:
638  return currEL() == EL2 ? MISCREG_FAR_EL2 : misc_reg;
639  case MISCREG_MAIR_EL1:
640  return currEL() == EL2 ? MISCREG_MAIR_EL2 : misc_reg;
641  case MISCREG_AMAIR_EL1:
642  return currEL() == EL2 ? MISCREG_AMAIR_EL2 : misc_reg;
643  case MISCREG_VBAR_EL1:
644  return currEL() == EL2 ? MISCREG_VBAR_EL2 : misc_reg;
645  case MISCREG_CONTEXTIDR_EL1:
646  return currEL() == EL2 ? MISCREG_CONTEXTIDR_EL2 : misc_reg;
647  case MISCREG_CNTKCTL_EL1:
648  return currEL() == EL2 ? MISCREG_CNTHCTL_EL2 : misc_reg;
649  case MISCREG_CNTP_TVAL:
650  case MISCREG_CNTP_TVAL_EL0:
651  if (ELIsInHost(tc, currEL())) {
652  return sec_el2 && !scr.ns ? MISCREG_CNTHPS_TVAL_EL2:
653  MISCREG_CNTHP_TVAL_EL2;
654  } else {
655  return misc_reg;
656  }
657  case MISCREG_CNTP_CTL:
658  case MISCREG_CNTP_CTL_EL0:
659  if (ELIsInHost(tc, currEL())) {
660  return sec_el2 && !scr.ns ? MISCREG_CNTHPS_CTL_EL2:
661  MISCREG_CNTHP_CTL_EL2;
662  } else {
663  return misc_reg;
664  }
665  case MISCREG_CNTP_CVAL:
666  case MISCREG_CNTP_CVAL_EL0:
667  if (ELIsInHost(tc, currEL())) {
668  return sec_el2 && !scr.ns ? MISCREG_CNTHPS_CVAL_EL2:
669  MISCREG_CNTHP_CVAL_EL2;
670  } else {
671  return misc_reg;
672  }
673  case MISCREG_CNTV_TVAL:
674  case MISCREG_CNTV_TVAL_EL0:
675  if (ELIsInHost(tc, currEL())) {
676  return sec_el2 && !scr.ns ? MISCREG_CNTHVS_TVAL_EL2:
677  MISCREG_CNTHV_TVAL_EL2;
678  } else {
679  return misc_reg;
680  }
681  case MISCREG_CNTV_CTL:
682  case MISCREG_CNTV_CTL_EL0:
683  if (ELIsInHost(tc, currEL())) {
684  return sec_el2 && !scr.ns ? MISCREG_CNTHVS_CTL_EL2:
685  MISCREG_CNTHV_CTL_EL2;
686  } else {
687  return misc_reg;
688  }
689  case MISCREG_CNTV_CVAL:
690  case MISCREG_CNTV_CVAL_EL0:
691  if (ELIsInHost(tc, currEL())) {
692  return sec_el2 && !scr.ns ? MISCREG_CNTHVS_CVAL_EL2:
693  MISCREG_CNTHV_CVAL_EL2;
694  } else {
695  return misc_reg;
696  }
697  case MISCREG_CNTVCT:
698  case MISCREG_CNTVCT_EL0:
699  return ELIsInHost(tc, currEL()) ? MISCREG_CNTPCT_EL0 : misc_reg;
700  case MISCREG_SCTLR_EL12:
701  return MISCREG_SCTLR_EL1;
702  case MISCREG_CPACR_EL12:
703  return MISCREG_CPACR_EL1;
704  case MISCREG_ZCR_EL12:
705  return MISCREG_ZCR_EL1;
706  case MISCREG_TTBR0_EL12:
707  return MISCREG_TTBR0_EL1;
708  case MISCREG_TTBR1_EL12:
709  return MISCREG_TTBR1_EL1;
710  case MISCREG_TCR_EL12:
711  return MISCREG_TCR_EL1;
712  case MISCREG_SPSR_EL12:
713  return MISCREG_SPSR_EL1;
714  case MISCREG_ELR_EL12:
715  return MISCREG_ELR_EL1;
716  case MISCREG_AFSR0_EL12:
717  return MISCREG_AFSR0_EL1;
718  case MISCREG_AFSR1_EL12:
719  return MISCREG_AFSR1_EL1;
720  case MISCREG_ESR_EL12:
721  return MISCREG_ESR_EL1;
722  case MISCREG_FAR_EL12:
723  return MISCREG_FAR_EL1;
724  case MISCREG_MAIR_EL12:
725  return MISCREG_MAIR_EL1;
726  case MISCREG_AMAIR_EL12:
727  return MISCREG_AMAIR_EL1;
728  case MISCREG_VBAR_EL12:
729  return MISCREG_VBAR_EL1;
730  case MISCREG_CONTEXTIDR_EL12:
731  return MISCREG_CONTEXTIDR_EL1;
732  case MISCREG_CNTKCTL_EL12:
733  return MISCREG_CNTKCTL_EL1;
734  // _EL02 registers
735  case MISCREG_CNTP_TVAL_EL02:
736  return MISCREG_CNTP_TVAL_EL0;
737  case MISCREG_CNTP_CTL_EL02:
738  return MISCREG_CNTP_CTL_EL0;
739  case MISCREG_CNTP_CVAL_EL02:
740  return MISCREG_CNTP_CVAL_EL0;
741  case MISCREG_CNTV_TVAL_EL02:
742  return MISCREG_CNTV_TVAL_EL0;
743  case MISCREG_CNTV_CTL_EL02:
744  return MISCREG_CNTV_CTL_EL0;
745  case MISCREG_CNTV_CVAL_EL02:
746  return MISCREG_CNTV_CVAL_EL0;
747  default:
748  return misc_reg;
749  }
750 }
751 
752 RegVal
753 ISA::readMiscRegNoEffect(int misc_reg) const
754 {
755  assert(misc_reg < NUM_MISCREGS);
756 
757  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
758  const auto &map = getMiscIndices(misc_reg);
759  int lower = map.first, upper = map.second;
760  // NB!: apply architectural masks according to desired register,
761  // despite possibly getting value from different (mapped) register.
762  auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
763  |(miscRegs[upper] << 32));
764  if (val & reg.res0()) {
765  DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
766  miscRegName[misc_reg], val & reg.res0());
767  }
768  if ((val & reg.res1()) != reg.res1()) {
769  DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
770  miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
771  }
772  return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
773 }
774 
775 
776 RegVal
777 ISA::readMiscReg(int misc_reg)
778 {
779  CPSR cpsr = 0;
780  SCR scr = 0;
781 
782  if (misc_reg == MISCREG_CPSR) {
783  cpsr = miscRegs[misc_reg];
784  auto pc = tc->pcState().as<PCState>();
785  cpsr.j = pc.jazelle() ? 1 : 0;
786  cpsr.t = pc.thumb() ? 1 : 0;
787  return cpsr;
788  }
789 
790 #ifndef NDEBUG
791  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
792  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
793  warn("Unimplemented system register %s read.\n",
794  miscRegName[misc_reg]);
795  else
796  panic("Unimplemented system register %s read.\n",
797  miscRegName[misc_reg]);
798  }
799 #endif
800  misc_reg = redirectRegVHE(misc_reg);
801 
802  switch (unflattenMiscReg(misc_reg)) {
803  case MISCREG_HCR:
804  case MISCREG_HCR2:
805  if (!release->has(ArmExtension::VIRTUALIZATION))
806  return 0;
807  break;
808  case MISCREG_CPACR:
809  {
810  const uint32_t ones = (uint32_t)(-1);
811  CPACR cpacrMask = 0;
812  // Only cp10, cp11, and ase are implemented, nothing else should
813  // be readable? (straight copy from the write code)
814  cpacrMask.cp10 = ones;
815  cpacrMask.cp11 = ones;
816  cpacrMask.asedis = ones;
817 
818  // Security Extensions may limit the readability of CPACR
819  if (release->has(ArmExtension::SECURITY)) {
820  scr = readMiscRegNoEffect(MISCREG_SCR);
821  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
822  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
823  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
824  // NB: Skipping the full loop, here
825  if (!nsacr.cp10) cpacrMask.cp10 = 0;
826  if (!nsacr.cp11) cpacrMask.cp11 = 0;
827  }
828  }
829  RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
830  val &= cpacrMask;
831  DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
832  miscRegName[misc_reg], val);
833  return val;
834  }
835  case MISCREG_MPIDR:
836  case MISCREG_MPIDR_EL1:
837  return readMPIDR(system, tc);
838  case MISCREG_VMPIDR:
839  case MISCREG_VMPIDR_EL2:
840  // top bit defined as RES1
841  return readMiscRegNoEffect(misc_reg) | 0x80000000;
842  case MISCREG_ID_AFR0: // not implemented, so alias MIDR
843  case MISCREG_REVIDR: // not implemented, so alias MIDR
844  case MISCREG_MIDR:
845  cpsr = readMiscRegNoEffect(MISCREG_CPSR);
846  scr = readMiscRegNoEffect(MISCREG_SCR);
847  if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
848  return readMiscRegNoEffect(misc_reg);
849  } else {
850  return readMiscRegNoEffect(MISCREG_VPIDR);
851  }
852  break;
853  case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
854  case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
855  case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
856  case MISCREG_AIDR: // AUX ID set to 0
857  case MISCREG_TCMTR: // No TCM's
858  return 0;
859 
860  case MISCREG_CLIDR:
861  warn_once("The clidr register always reports 0 caches.\n");
862  warn_once("clidr LoUIS field of 0b001 to match current "
863  "ARM implementations.\n");
864  return 0x00200000;
865  case MISCREG_CCSIDR:
866  warn_once("The ccsidr register isn't implemented and "
867  "always reads as 0.\n");
868  break;
869  case MISCREG_CTR: // AArch32, ARMv7, top bit set
870  case MISCREG_CTR_EL0: // AArch64
871  {
872  //all caches have the same line size in gem5
873  //4 byte words in ARM
874  unsigned lineSizeWords =
875  tc->getSystemPtr()->cacheLineSize() / 4;
876  unsigned log2LineSizeWords = 0;
877 
878  while (lineSizeWords >>= 1) {
879  ++log2LineSizeWords;
880  }
881 
882  CTR ctr = 0;
883  //log2 of minimun i-cache line size (words)
884  ctr.iCacheLineSize = log2LineSizeWords;
885  //b11 - gem5 uses pipt
886  ctr.l1IndexPolicy = 0x3;
887  //log2 of minimum d-cache line size (words)
888  ctr.dCacheLineSize = log2LineSizeWords;
889  //log2 of max reservation size (words)
890  ctr.erg = log2LineSizeWords;
891  //log2 of max writeback size (words)
892  ctr.cwg = log2LineSizeWords;
893  //b100 - gem5 format is ARMv7
894  ctr.format = 0x4;
895 
896  return ctr;
897  }
898  case MISCREG_ACTLR:
899  warn("Not doing anything for miscreg ACTLR\n");
900  break;
901 
902  case MISCREG_PMXEVTYPER_PMCCFILTR:
903  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
904  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
905  case MISCREG_PMCR ... MISCREG_PMOVSSET:
906  return pmu->readMiscReg(misc_reg);
907 
908  case MISCREG_CPSR_Q:
909  panic("shouldn't be reading this register seperately\n");
910  case MISCREG_FPSCR_QC:
911  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
912  case MISCREG_FPSCR_EXC:
913  return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
914  case MISCREG_FPSR:
915  {
916  const uint32_t ones = (uint32_t)(-1);
917  FPSCR fpscrMask = 0;
918  fpscrMask.ioc = ones;
919  fpscrMask.dzc = ones;
920  fpscrMask.ofc = ones;
921  fpscrMask.ufc = ones;
922  fpscrMask.ixc = ones;
923  fpscrMask.idc = ones;
924  fpscrMask.qc = ones;
925  fpscrMask.v = ones;
926  fpscrMask.c = ones;
927  fpscrMask.z = ones;
928  fpscrMask.n = ones;
929  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
930  }
931  case MISCREG_FPCR:
932  {
933  const uint32_t ones = (uint32_t)(-1);
934  FPSCR fpscrMask = 0;
935  fpscrMask.len = ones;
936  fpscrMask.fz16 = ones;
937  fpscrMask.stride = ones;
938  fpscrMask.rMode = ones;
939  fpscrMask.fz = ones;
940  fpscrMask.dn = ones;
941  fpscrMask.ahp = ones;
942  return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
943  }
944  case MISCREG_NZCV:
945  {
946  CPSR cpsr = 0;
947  cpsr.nz = tc->getReg(cc_reg::Nz);
948  cpsr.c = tc->getReg(cc_reg::C);
949  cpsr.v = tc->getReg(cc_reg::V);
950  return cpsr;
951  }
952  case MISCREG_DAIF:
953  {
954  CPSR cpsr = 0;
955  cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
956  return cpsr;
957  }
958  case MISCREG_SP_EL0:
959  {
960  return tc->getReg(int_reg::Sp0);
961  }
962  case MISCREG_SP_EL1:
963  {
964  return tc->getReg(int_reg::Sp1);
965  }
966  case MISCREG_SP_EL2:
967  {
968  return tc->getReg(int_reg::Sp2);
969  }
970  case MISCREG_SPSEL:
971  {
972  return miscRegs[MISCREG_CPSR] & 0x1;
973  }
974  case MISCREG_CURRENTEL:
975  {
976  return miscRegs[MISCREG_CPSR] & 0xc;
977  }
978  case MISCREG_PAN:
979  {
980  return miscRegs[MISCREG_CPSR] & 0x400000;
981  }
982  case MISCREG_UAO:
983  {
984  return miscRegs[MISCREG_CPSR] & 0x800000;
985  }
986  case MISCREG_L2CTLR:
987  {
988  // mostly unimplemented, just set NumCPUs field from sim and return
989  L2CTLR l2ctlr = 0;
990  // b00:1CPU to b11:4CPUs
991  l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
992  return l2ctlr;
993  }
994  case MISCREG_DBGDIDR:
995  /* For now just implement the version number.
996  * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
997  */
998  return 0x5 << 16;
999  case MISCREG_DBGDSCRint:
1000  return readMiscRegNoEffect(MISCREG_DBGDSCRint);
1001  case MISCREG_ISR:
1002  {
1003  auto ic = dynamic_cast<ArmISA::Interrupts *>(
1004  tc->getCpuPtr()->getInterruptController(tc->threadId()));
1005  return ic->getISR(
1006  readMiscRegNoEffect(MISCREG_HCR),
1007  readMiscRegNoEffect(MISCREG_CPSR),
1008  readMiscRegNoEffect(MISCREG_SCR));
1009  }
1010  case MISCREG_ISR_EL1:
1011  {
1012  auto ic = dynamic_cast<ArmISA::Interrupts *>(
1013  tc->getCpuPtr()->getInterruptController(tc->threadId()));
1014  return ic->getISR(
1015  readMiscRegNoEffect(MISCREG_HCR_EL2),
1016  readMiscRegNoEffect(MISCREG_CPSR),
1017  readMiscRegNoEffect(MISCREG_SCR_EL3));
1018  }
1019  case MISCREG_DCZID_EL0:
1020  return 0x04; // DC ZVA clear 64-byte chunks
1021  case MISCREG_HCPTR:
1022  {
1023  RegVal val = readMiscRegNoEffect(misc_reg);
1024  // The trap bit associated with CP14 is defined as RAZ
1025  val &= ~(1 << 14);
1026  // If a CP bit in NSACR is 0 then the corresponding bit in
1027  // HCPTR is RAO/WI
1028  bool secure_lookup = release->has(ArmExtension::SECURITY) &&
1029  isSecure(tc);
1030  if (!secure_lookup) {
1031  RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
1032  val |= (mask ^ 0x7FFF) & 0xBFFF;
1033  }
1034  // Set the bits for unimplemented coprocessors to RAO/WI
1035  val |= 0x33FF;
1036  return (val);
1037  }
1038  case MISCREG_HDFAR: // alias for secure DFAR
1039  return readMiscRegNoEffect(MISCREG_DFAR_S);
1040  case MISCREG_HIFAR: // alias for secure IFAR
1041  return readMiscRegNoEffect(MISCREG_IFAR_S);
1042 
1043  case MISCREG_ID_PFR0:
1044  // !ThumbEE | !Jazelle | Thumb | ARM
1045  return 0x00000031;
1046  case MISCREG_ID_PFR1:
1047  { // Timer | Virti | !M Profile | TrustZone | ARMv4
1048  bool have_timer = (system->getGenericTimer() != nullptr);
1049  return 0x00000001 |
1050  (release->has(ArmExtension::SECURITY) ?
1051  0x00000010 : 0x0) |
1052  (release->has(ArmExtension::VIRTUALIZATION) ?
1053  0x00001000 : 0x0) |
1054  (have_timer ? 0x00010000 : 0x0);
1055  }
1056  case MISCREG_ID_AA64PFR0_EL1:
1057  return 0x0000000000000002 | // AArch{64,32} supported at EL0
1058  0x0000000000000020 | // EL1
1059  (release->has(ArmExtension::VIRTUALIZATION) ?
1060  0x0000000000000200 : 0) | // EL2
1061  (release->has(ArmExtension::SECURITY) ?
1062  0x0000000000002000 : 0) | // EL3
1063  (release->has(ArmExtension::FEAT_SVE) ?
1064  0x0000000100000000 : 0) | // SVE
1065  (release->has(ArmExtension::FEAT_SEL2) ?
1066  0x0000001000000000 : 0) | // SecEL2
1067  (gicv3CpuInterface ? 0x0000000001000000 : 0);
1068  case MISCREG_ID_AA64PFR1_EL1:
1069  return 0; // bits [63:0] RES0 (reserved for future use)
1070 
1071  // Generic Timer registers
1072  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
1073  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
1074  return getGenericTimer().readMiscReg(misc_reg);
1075 
1076  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
1077  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
1078  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
1079  return getGICv3CPUInterface().readMiscReg(misc_reg);
1080 
1081  default:
1082  break;
1083 
1084  }
1085  return readMiscRegNoEffect(misc_reg);
1086 }
1087 
1088 void
1089 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
1090 {
1091  assert(misc_reg < NUM_MISCREGS);
1092 
1093  const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
1094  const auto &map = getMiscIndices(misc_reg);
1095  int lower = map.first, upper = map.second;
1096 
1097  auto v = (val & ~reg.wi()) | reg.rao();
1098  if (upper > 0) {
1099  miscRegs[lower] = bits(v, 31, 0);
1100  miscRegs[upper] = bits(v, 63, 32);
1101  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
1102  miscRegName[misc_reg], misc_reg, lower, upper, v);
1103  } else {
1104  miscRegs[lower] = v;
1105  DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
1106  miscRegName[misc_reg], misc_reg, lower, v);
1107  }
1108 }
1109 
1110 void
1111 ISA::setMiscReg(int misc_reg, RegVal val)
1112 {
1113 
1114  RegVal newVal = val;
1115  bool secure_lookup;
1116  SCR scr;
1117 
1118  if (misc_reg == MISCREG_CPSR) {
1119  updateRegMap(val);
1120 
1121 
1122  CPSR old_cpsr = miscRegs[MISCREG_CPSR];
1123  int old_mode = old_cpsr.mode;
1124  CPSR cpsr = val;
1125  if (cpsr.pan != old_cpsr.pan || cpsr.il != old_cpsr.il) {
1126  getMMUPtr(tc)->invalidateMiscReg();
1127  }
1128 
1129  DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
1130  miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
1131  PCState pc = tc->pcState().as<PCState>();
1132  pc.nextThumb(cpsr.t);
1133  pc.nextJazelle(cpsr.j);
1134  pc.illegalExec(cpsr.il == 1);
1135  selfDebug->setDebugMask(cpsr.d == 1);
1136 
1137  tc->getDecoderPtr()->as<Decoder>().setSveLen(
1138  (getCurSveVecLenInBits() >> 7) - 1);
1139 
1140  // Follow slightly different semantics if a CheckerCPU object
1141  // is connected
1142  CheckerCPU *checker = tc->getCheckerCpuPtr();
1143  if (checker) {
1144  tc->pcStateNoRecord(pc);
1145  } else {
1146  tc->pcState(pc);
1147  }
1148 
1149  setMiscRegNoEffect(misc_reg, newVal);
1150 
1151  if (old_mode != cpsr.mode) {
1152  getMMUPtr(tc)->invalidateMiscReg();
1153  if (gicv3CpuInterface) {
1154  // The assertion and de-assertion of IRQs and FIQs are
1155  // affected by the current Exception level and Security
1156  // state of the PE. As part of the Context
1157  // Synchronization that occurs as the result of taking
1158  // or returning from an exception, the CPU interface
1159  // ensures that IRQ and FIQ are both appropriately
1160  // asserted or deasserted for the Exception level and
1161  // Security state that the PE is entering.
1162  static_cast<Gicv3CPUInterface&>(
1163  getGICv3CPUInterface()).update();
1164  }
1165  }
1166  } else {
1167 #ifndef NDEBUG
1168  if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
1169  if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
1170  warn("Unimplemented system register %s write with %#x.\n",
1171  miscRegName[misc_reg], val);
1172  else
1173  panic("Unimplemented system register %s write with %#x.\n",
1174  miscRegName[misc_reg], val);
1175  }
1176 #endif
1177  misc_reg = redirectRegVHE(misc_reg);
1178 
1179  switch (unflattenMiscReg(misc_reg)) {
1180  case MISCREG_CPACR:
1181  {
1182 
1183  const uint32_t ones = (uint32_t)(-1);
1184  CPACR cpacrMask = 0;
1185  // Only cp10, cp11, and ase are implemented, nothing else should
1186  // be writable
1187  cpacrMask.cp10 = ones;
1188  cpacrMask.cp11 = ones;
1189  cpacrMask.asedis = ones;
1190 
1191  // Security Extensions may limit the writability of CPACR
1192  if (release->has(ArmExtension::SECURITY)) {
1193  scr = readMiscRegNoEffect(MISCREG_SCR);
1194  CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
1195  if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
1196  NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
1197  // NB: Skipping the full loop, here
1198  if (!nsacr.cp10) cpacrMask.cp10 = 0;
1199  if (!nsacr.cp11) cpacrMask.cp11 = 0;
1200  }
1201  }
1202 
1203  RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
1204  newVal &= cpacrMask;
1205  newVal |= old_val & ~cpacrMask;
1206  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1207  miscRegName[misc_reg], newVal);
1208  }
1209  break;
1210  case MISCREG_CPACR_EL1:
1211  {
1212  const uint32_t ones = (uint32_t)(-1);
1213  CPACR cpacrMask = 0;
1214  cpacrMask.tta = ones;
1215  cpacrMask.fpen = ones;
1216  if (release->has(ArmExtension::FEAT_SVE)) {
1217  cpacrMask.zen = ones;
1218  }
1219  newVal &= cpacrMask;
1220  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1221  miscRegName[misc_reg], newVal);
1222  }
1223  break;
1224  case MISCREG_CPTR_EL2:
1225  {
1226  const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
1227  const uint32_t ones = (uint32_t)(-1);
1228  CPTR cptrMask = 0;
1229  cptrMask.tcpac = ones;
1230  cptrMask.tta = ones;
1231  cptrMask.tfp = ones;
1232  if (release->has(ArmExtension::FEAT_SVE)) {
1233  cptrMask.tz = ones;
1234  cptrMask.zen = hcr.e2h ? ones : 0;
1235  }
1236  cptrMask.fpen = hcr.e2h ? ones : 0;
1237  newVal &= cptrMask;
1238  cptrMask = 0;
1239  cptrMask.res1_13_12_el2 = ones;
1240  cptrMask.res1_7_0_el2 = ones;
1241  if (!release->has(ArmExtension::FEAT_SVE)) {
1242  cptrMask.res1_8_el2 = ones;
1243  }
1244  cptrMask.res1_9_el2 = ones;
1245  newVal |= cptrMask;
1246  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1247  miscRegName[misc_reg], newVal);
1248  }
1249  break;
1250  case MISCREG_CPTR_EL3:
1251  {
1252  const uint32_t ones = (uint32_t)(-1);
1253  CPTR cptrMask = 0;
1254  cptrMask.tcpac = ones;
1255  cptrMask.tta = ones;
1256  cptrMask.tfp = ones;
1257  if (release->has(ArmExtension::FEAT_SVE)) {
1258  cptrMask.ez = ones;
1259  }
1260  newVal &= cptrMask;
1261  DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
1262  miscRegName[misc_reg], newVal);
1263  }
1264  break;
1265  case MISCREG_CSSELR:
1266  warn_once("The csselr register isn't implemented.\n");
1267  return;
1268 
1269  case MISCREG_DC_ZVA_Xt:
1270  warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
1271  return;
1272 
1273  case MISCREG_FPSCR:
1274  {
1275  const uint32_t ones = (uint32_t)(-1);
1276  FPSCR fpscrMask = 0;
1277  fpscrMask.ioc = ones;
1278  fpscrMask.dzc = ones;
1279  fpscrMask.ofc = ones;
1280  fpscrMask.ufc = ones;
1281  fpscrMask.ixc = ones;
1282  fpscrMask.idc = ones;
1283  fpscrMask.ioe = ones;
1284  fpscrMask.dze = ones;
1285  fpscrMask.ofe = ones;
1286  fpscrMask.ufe = ones;
1287  fpscrMask.ixe = ones;
1288  fpscrMask.ide = ones;
1289  fpscrMask.len = ones;
1290  fpscrMask.fz16 = ones;
1291  fpscrMask.stride = ones;
1292  fpscrMask.rMode = ones;
1293  fpscrMask.fz = ones;
1294  fpscrMask.dn = ones;
1295  fpscrMask.ahp = ones;
1296  fpscrMask.qc = ones;
1297  fpscrMask.v = ones;
1298  fpscrMask.c = ones;
1299  fpscrMask.z = ones;
1300  fpscrMask.n = ones;
1301  newVal = (newVal & (uint32_t)fpscrMask) |
1302  (readMiscRegNoEffect(MISCREG_FPSCR) &
1303  ~(uint32_t)fpscrMask);
1304  tc->getDecoderPtr()->as<Decoder>().setContext(newVal);
1305  }
1306  break;
1307  case MISCREG_FPSR:
1308  {
1309  const uint32_t ones = (uint32_t)(-1);
1310  FPSCR fpscrMask = 0;
1311  fpscrMask.ioc = ones;
1312  fpscrMask.dzc = ones;
1313  fpscrMask.ofc = ones;
1314  fpscrMask.ufc = ones;
1315  fpscrMask.ixc = ones;
1316  fpscrMask.idc = ones;
1317  fpscrMask.qc = ones;
1318  fpscrMask.v = ones;
1319  fpscrMask.c = ones;
1320  fpscrMask.z = ones;
1321  fpscrMask.n = ones;
1322  newVal = (newVal & (uint32_t)fpscrMask) |
1323  (readMiscRegNoEffect(MISCREG_FPSCR) &
1324  ~(uint32_t)fpscrMask);
1325  misc_reg = MISCREG_FPSCR;
1326  }
1327  break;
1328  case MISCREG_FPCR:
1329  {
1330  const uint32_t ones = (uint32_t)(-1);
1331  FPSCR fpscrMask = 0;
1332  fpscrMask.len = ones;
1333  fpscrMask.fz16 = ones;
1334  fpscrMask.stride = ones;
1335  fpscrMask.rMode = ones;
1336  fpscrMask.fz = ones;
1337  fpscrMask.dn = ones;
1338  fpscrMask.ahp = ones;
1339  newVal = (newVal & (uint32_t)fpscrMask) |
1340  (readMiscRegNoEffect(MISCREG_FPSCR) &
1341  ~(uint32_t)fpscrMask);
1342  misc_reg = MISCREG_FPSCR;
1343  }
1344  break;
1345  case MISCREG_CPSR_Q:
1346  {
1347  assert(!(newVal & ~CpsrMaskQ));
1348  newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1349  misc_reg = MISCREG_CPSR;
1350  }
1351  break;
1352  case MISCREG_FPSCR_QC:
1353  {
1354  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1355  (newVal & FpscrQcMask);
1356  misc_reg = MISCREG_FPSCR;
1357  }
1358  break;
1359  case MISCREG_FPSCR_EXC:
1360  {
1361  newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1362  (newVal & FpscrExcMask);
1363  misc_reg = MISCREG_FPSCR;
1364  }
1365  break;
1366  case MISCREG_FPEXC:
1367  {
1368  // vfpv3 architecture, section B.6.1 of DDI04068
1369  // bit 29 - valid only if fpexc[31] is 0
1370  const uint32_t fpexcMask = 0x60000000;
1371  newVal = (newVal & fpexcMask) |
1372  (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1373  }
1374  break;
1375  case MISCREG_HCR2:
1376  if (!release->has(ArmExtension::VIRTUALIZATION))
1377  return;
1378  break;
1379  case MISCREG_HCR:
1380  {
1381  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1382  selfDebug->setenableTDETGE((HCR)val, mdcr);
1383  if (!release->has(ArmExtension::VIRTUALIZATION))
1384  return;
1385  }
1386  break;
1387 
1388  case MISCREG_HDCR:
1389  {
1390  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1391  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1392  }
1393  break;
1394  case MISCREG_DBGOSLAR:
1395  {
1396  OSL r = tc->readMiscReg(MISCREG_DBGOSLSR);
1397  const uint32_t temp = (val == 0xC5ACCE55)? 0x1 : 0x0;
1398  selfDebug->updateOSLock((RegVal) temp);
1399  r.oslk = bits(temp,0);
1400  tc->setMiscReg(MISCREG_DBGOSLSR, r);
1401  }
1402  break;
1403  case MISCREG_DBGBCR0:
1404  selfDebug->updateDBGBCR(0, val);
1405  break;
1406  case MISCREG_DBGBCR1:
1407  selfDebug->updateDBGBCR(1, val);
1408  break;
1409  case MISCREG_DBGBCR2:
1410  selfDebug->updateDBGBCR(2, val);
1411  break;
1412  case MISCREG_DBGBCR3:
1413  selfDebug->updateDBGBCR(3, val);
1414  break;
1415  case MISCREG_DBGBCR4:
1416  selfDebug->updateDBGBCR(4, val);
1417  break;
1418  case MISCREG_DBGBCR5:
1419  selfDebug->updateDBGBCR(5, val);
1420  break;
1421  case MISCREG_DBGBCR6:
1422  selfDebug->updateDBGBCR(6, val);
1423  break;
1424  case MISCREG_DBGBCR7:
1425  selfDebug->updateDBGBCR(7, val);
1426  break;
1427  case MISCREG_DBGBCR8:
1428  selfDebug->updateDBGBCR(8, val);
1429  break;
1430  case MISCREG_DBGBCR9:
1431  selfDebug->updateDBGBCR(9, val);
1432  break;
1433  case MISCREG_DBGBCR10:
1434  selfDebug->updateDBGBCR(10, val);
1435  break;
1436  case MISCREG_DBGBCR11:
1437  selfDebug->updateDBGBCR(11, val);
1438  break;
1439  case MISCREG_DBGBCR12:
1440  selfDebug->updateDBGBCR(12, val);
1441  break;
1442  case MISCREG_DBGBCR13:
1443  selfDebug->updateDBGBCR(13, val);
1444  break;
1445  case MISCREG_DBGBCR14:
1446  selfDebug->updateDBGBCR(14, val);
1447  break;
1448  case MISCREG_DBGBCR15:
1449  selfDebug->updateDBGBCR(15, val);
1450  break;
1451  case MISCREG_DBGWCR0:
1452  selfDebug->updateDBGWCR(0, val);
1453  break;
1454  case MISCREG_DBGWCR1:
1455  selfDebug->updateDBGWCR(1, val);
1456  break;
1457  case MISCREG_DBGWCR2:
1458  selfDebug->updateDBGWCR(2, val);
1459  break;
1460  case MISCREG_DBGWCR3:
1461  selfDebug->updateDBGWCR(3, val);
1462  break;
1463  case MISCREG_DBGWCR4:
1464  selfDebug->updateDBGWCR(4, val);
1465  break;
1466  case MISCREG_DBGWCR5:
1467  selfDebug->updateDBGWCR(5, val);
1468  break;
1469  case MISCREG_DBGWCR6:
1470  selfDebug->updateDBGWCR(6, val);
1471  break;
1472  case MISCREG_DBGWCR7:
1473  selfDebug->updateDBGWCR(7, val);
1474  break;
1475  case MISCREG_DBGWCR8:
1476  selfDebug->updateDBGWCR(8, val);
1477  break;
1478  case MISCREG_DBGWCR9:
1479  selfDebug->updateDBGWCR(9, val);
1480  break;
1481  case MISCREG_DBGWCR10:
1482  selfDebug->updateDBGWCR(10, val);
1483  break;
1484  case MISCREG_DBGWCR11:
1485  selfDebug->updateDBGWCR(11, val);
1486  break;
1487  case MISCREG_DBGWCR12:
1488  selfDebug->updateDBGWCR(12, val);
1489  break;
1490  case MISCREG_DBGWCR13:
1491  selfDebug->updateDBGWCR(13, val);
1492  break;
1493  case MISCREG_DBGWCR14:
1494  selfDebug->updateDBGWCR(14, val);
1495  break;
1496  case MISCREG_DBGWCR15:
1497  selfDebug->updateDBGWCR(15, val);
1498  break;
1499 
1500  case MISCREG_MDCR_EL2:
1501  {
1502  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1503  selfDebug->setenableTDETGE(hcr, (HDCR)val);
1504  }
1505  break;
1506  case MISCREG_SDCR:
1507  case MISCREG_MDCR_EL3:
1508  {
1509  selfDebug->setbSDD(val);
1510  }
1511  break;
1512  case MISCREG_DBGDSCRext:
1513  {
1514  selfDebug->setMDBGen(val);
1515  DBGDS32 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1516  DBGDS32 v = val;
1517  r.moe = v.moe;
1518  r.udccdis = v.udccdis;
1519  r.mdbgen = v.mdbgen;
1520  tc->setMiscReg(MISCREG_DBGDSCRint, r);
1521  r = tc->readMiscReg(MISCREG_DBGDSCRint);
1522  }
1523 
1524  break;
1525  case MISCREG_MDSCR_EL1:
1526  {
1527  selfDebug->setMDSCRvals(val);
1528  }
1529  break;
1530 
1531  case MISCREG_OSLAR_EL1:
1532  {
1533  selfDebug->updateOSLock(val);
1534  OSL r = tc->readMiscReg(MISCREG_OSLSR_EL1);
1535  r.oslk = bits(val, 0);
1536  r.oslm_3 = 1;
1537  tc->setMiscReg(MISCREG_OSLSR_EL1, r);
1538  }
1539  break;
1540 
1541  case MISCREG_DBGBCR0_EL1:
1542  selfDebug->updateDBGBCR(0, val);
1543  break;
1544  case MISCREG_DBGBCR1_EL1:
1545  selfDebug->updateDBGBCR(1, val);
1546  break;
1547  case MISCREG_DBGBCR2_EL1:
1548  selfDebug->updateDBGBCR(2, val);
1549  break;
1550  case MISCREG_DBGBCR3_EL1:
1551  selfDebug->updateDBGBCR(3, val);
1552  break;
1553  case MISCREG_DBGBCR4_EL1:
1554  selfDebug->updateDBGBCR(4, val);
1555  break;
1556  case MISCREG_DBGBCR5_EL1:
1557  selfDebug->updateDBGBCR(5, val);
1558  break;
1559  case MISCREG_DBGBCR6_EL1:
1560  selfDebug->updateDBGBCR(6, val);
1561  break;
1562  case MISCREG_DBGBCR7_EL1:
1563  selfDebug->updateDBGBCR(7, val);
1564  break;
1565  case MISCREG_DBGBCR8_EL1:
1566  selfDebug->updateDBGBCR(8, val);
1567  break;
1568  case MISCREG_DBGBCR9_EL1:
1569  selfDebug->updateDBGBCR(9, val);
1570  break;
1571  case MISCREG_DBGBCR10_EL1:
1572  selfDebug->updateDBGBCR(10, val);
1573  break;
1574  case MISCREG_DBGBCR11_EL1:
1575  selfDebug->updateDBGBCR(11, val);
1576  break;
1577  case MISCREG_DBGBCR12_EL1:
1578  selfDebug->updateDBGBCR(12, val);
1579  break;
1580  case MISCREG_DBGBCR13_EL1:
1581  selfDebug->updateDBGBCR(13, val);
1582  break;
1583  case MISCREG_DBGBCR14_EL1:
1584  selfDebug->updateDBGBCR(14, val);
1585  break;
1586  case MISCREG_DBGBCR15_EL1:
1587  selfDebug->updateDBGBCR(15, val);
1588  break;
1589  case MISCREG_DBGWCR0_EL1:
1590  selfDebug->updateDBGWCR(0, val);
1591  break;
1592  case MISCREG_DBGWCR1_EL1:
1593  selfDebug->updateDBGWCR(1, val);
1594  break;
1595  case MISCREG_DBGWCR2_EL1:
1596  selfDebug->updateDBGWCR(2, val);
1597  break;
1598  case MISCREG_DBGWCR3_EL1:
1599  selfDebug->updateDBGWCR(3, val);
1600  break;
1601  case MISCREG_DBGWCR4_EL1:
1602  selfDebug->updateDBGWCR(4, val);
1603  break;
1604  case MISCREG_DBGWCR5_EL1:
1605  selfDebug->updateDBGWCR(5, val);
1606  break;
1607  case MISCREG_DBGWCR6_EL1:
1608  selfDebug->updateDBGWCR(6, val);
1609  break;
1610  case MISCREG_DBGWCR7_EL1:
1611  selfDebug->updateDBGWCR(7, val);
1612  break;
1613  case MISCREG_DBGWCR8_EL1:
1614  selfDebug->updateDBGWCR(8, val);
1615  break;
1616  case MISCREG_DBGWCR9_EL1:
1617  selfDebug->updateDBGWCR(9, val);
1618  break;
1619  case MISCREG_DBGWCR10_EL1:
1620  selfDebug->updateDBGWCR(10, val);
1621  break;
1622  case MISCREG_DBGWCR11_EL1:
1623  selfDebug->updateDBGWCR(11, val);
1624  break;
1625  case MISCREG_DBGWCR12_EL1:
1626  selfDebug->updateDBGWCR(12, val);
1627  break;
1628  case MISCREG_DBGWCR13_EL1:
1629  selfDebug->updateDBGWCR(13, val);
1630  break;
1631  case MISCREG_DBGWCR14_EL1:
1632  selfDebug->updateDBGWCR(14, val);
1633  break;
1634  case MISCREG_DBGWCR15_EL1:
1635  selfDebug->updateDBGWCR(15, val);
1636  break;
1637  case MISCREG_IFSR:
1638  {
1639  // ARM ARM (ARM DDI 0406C.b) B4.1.96
1640  const uint32_t ifsrMask =
1641  mask(31, 13) | mask(11, 11) | mask(8, 6);
1642  newVal = newVal & ~ifsrMask;
1643  }
1644  break;
1645  case MISCREG_DFSR:
1646  {
1647  // ARM ARM (ARM DDI 0406C.b) B4.1.52
1648  const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1649  newVal = newVal & ~dfsrMask;
1650  }
1651  break;
1652  case MISCREG_AMAIR0:
1653  case MISCREG_AMAIR1:
1654  {
1655  // ARM ARM (ARM DDI 0406C.b) B4.1.5
1656  // Valid only with LPAE
1657  if (!release->has(ArmExtension::LPAE))
1658  return;
1659  DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1660  }
1661  break;
1662  case MISCREG_SCR:
1663  getMMUPtr(tc)->invalidateMiscReg();
1664  break;
1665  case MISCREG_SCTLR:
1666  {
1667  DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1668  scr = readMiscRegNoEffect(MISCREG_SCR);
1669 
1670  MiscRegIndex sctlr_idx;
1671  if (release->has(ArmExtension::SECURITY) &&
1672  !highestELIs64 && !scr.ns) {
1673  sctlr_idx = MISCREG_SCTLR_S;
1674  } else {
1675  sctlr_idx = MISCREG_SCTLR_NS;
1676  }
1677 
1678  SCTLR sctlr = miscRegs[sctlr_idx];
1679  SCTLR new_sctlr = newVal;
1680  new_sctlr.nmfi = ((bool)sctlr.nmfi) &&
1681  !release->has(ArmExtension::VIRTUALIZATION);
1682  miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1683  getMMUPtr(tc)->invalidateMiscReg();
1684  }
1685  case MISCREG_MIDR:
1686  case MISCREG_ID_PFR0:
1687  case MISCREG_ID_PFR1:
1688  case MISCREG_ID_DFR0:
1689  case MISCREG_ID_MMFR0:
1690  case MISCREG_ID_MMFR1:
1691  case MISCREG_ID_MMFR2:
1692  case MISCREG_ID_MMFR3:
1693  case MISCREG_ID_MMFR4:
1694  case MISCREG_ID_ISAR0:
1695  case MISCREG_ID_ISAR1:
1696  case MISCREG_ID_ISAR2:
1697  case MISCREG_ID_ISAR3:
1698  case MISCREG_ID_ISAR4:
1699  case MISCREG_ID_ISAR5:
1700 
1701  case MISCREG_MPIDR:
1702  case MISCREG_FPSID:
1703  case MISCREG_TLBTR:
1704  case MISCREG_MVFR0:
1705  case MISCREG_MVFR1:
1706 
1707  case MISCREG_ID_AA64AFR0_EL1:
1708  case MISCREG_ID_AA64AFR1_EL1:
1709  case MISCREG_ID_AA64DFR0_EL1:
1710  case MISCREG_ID_AA64DFR1_EL1:
1711  case MISCREG_ID_AA64ISAR0_EL1:
1712  case MISCREG_ID_AA64ISAR1_EL1:
1713  case MISCREG_ID_AA64MMFR0_EL1:
1714  case MISCREG_ID_AA64MMFR1_EL1:
1715  case MISCREG_ID_AA64MMFR2_EL1:
1716  case MISCREG_ID_AA64PFR0_EL1:
1717  case MISCREG_ID_AA64PFR1_EL1:
1718  // ID registers are constants.
1719  return;
1720 
1721  // TLB Invalidate All
1722  case MISCREG_ACTLR:
1723  warn("Not doing anything for write of miscreg ACTLR\n");
1724  break;
1725 
1726  case MISCREG_PMXEVTYPER_PMCCFILTR:
1727  case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1728  case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1729  case MISCREG_PMCR ... MISCREG_PMOVSSET:
1730  pmu->setMiscReg(misc_reg, newVal);
1731  break;
1732 
1733 
1734  case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1735  {
1736  HSTR hstrMask = 0;
1737  hstrMask.tjdbx = 1;
1738  newVal &= ~((uint32_t) hstrMask);
1739  break;
1740  }
1741  case MISCREG_HCPTR:
1742  {
1743  // If a CP bit in NSACR is 0 then the corresponding bit in
1744  // HCPTR is RAO/WI. Same applies to NSASEDIS
1745  secure_lookup = release->has(ArmExtension::SECURITY) &&
1746  isSecure(tc);
1747  if (!secure_lookup) {
1748  RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1749  RegVal mask =
1750  (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
1751  newVal = (newVal & ~mask) | (oldValue & mask);
1752  }
1753  break;
1754  }
1755  case MISCREG_HDFAR: // alias for secure DFAR
1756  misc_reg = MISCREG_DFAR_S;
1757  break;
1758  case MISCREG_HIFAR: // alias for secure IFAR
1759  misc_reg = MISCREG_IFAR_S;
1760  break;
1761  case MISCREG_ATS1CPR:
1762  addressTranslation(MMU::S1CTran, BaseMMU::Read, 0, val);
1763  return;
1764  case MISCREG_ATS1CPW:
1765  addressTranslation(MMU::S1CTran, BaseMMU::Write, 0, val);
1766  return;
1767  case MISCREG_ATS1CUR:
1768  addressTranslation(MMU::S1CTran, BaseMMU::Read,
1769  MMU::UserMode, val);
1770  return;
1771  case MISCREG_ATS1CUW:
1772  addressTranslation(MMU::S1CTran, BaseMMU::Write,
1773  MMU::UserMode, val);
1774  return;
1775  case MISCREG_ATS12NSOPR:
1776  if (!release->has(ArmExtension::SECURITY))
1777  panic("Security Extensions required for ATS12NSOPR");
1778  addressTranslation(MMU::S1S2NsTran, BaseMMU::Read, 0, val);
1779  return;
1780  case MISCREG_ATS12NSOPW:
1781  if (!release->has(ArmExtension::SECURITY))
1782  panic("Security Extensions required for ATS12NSOPW");
1783  addressTranslation(MMU::S1S2NsTran, BaseMMU::Write, 0, val);
1784  return;
1785  case MISCREG_ATS12NSOUR:
1786  if (!release->has(ArmExtension::SECURITY))
1787  panic("Security Extensions required for ATS12NSOUR");
1788  addressTranslation(MMU::S1S2NsTran, BaseMMU::Read,
1789  MMU::UserMode, val);
1790  return;
1791  case MISCREG_ATS12NSOUW:
1792  if (!release->has(ArmExtension::SECURITY))
1793  panic("Security Extensions required for ATS12NSOUW");
1794  addressTranslation(MMU::S1S2NsTran, BaseMMU::Write,
1795  MMU::UserMode, val);
1796  return;
1797  case MISCREG_ATS1HR:
1798  addressTranslation(MMU::HypMode, BaseMMU::Read, 0, val);
1799  return;
1800  case MISCREG_ATS1HW:
1801  addressTranslation(MMU::HypMode, BaseMMU::Write, 0, val);
1802  return;
1803  case MISCREG_TTBCR:
1804  {
1805  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1806  const uint32_t ones = (uint32_t)(-1);
1807  TTBCR ttbcrMask = 0;
1808  TTBCR ttbcrNew = newVal;
1809 
1810  // ARM DDI 0406C.b, ARMv7-32
1811  ttbcrMask.n = ones; // T0SZ
1812  if (release->has(ArmExtension::SECURITY)) {
1813  ttbcrMask.pd0 = ones;
1814  ttbcrMask.pd1 = ones;
1815  }
1816  ttbcrMask.epd0 = ones;
1817  ttbcrMask.irgn0 = ones;
1818  ttbcrMask.orgn0 = ones;
1819  ttbcrMask.sh0 = ones;
1820  ttbcrMask.ps = ones; // T1SZ
1821  ttbcrMask.a1 = ones;
1822  ttbcrMask.epd1 = ones;
1823  ttbcrMask.irgn1 = ones;
1824  ttbcrMask.orgn1 = ones;
1825  ttbcrMask.sh1 = ones;
1826  if (release->has(ArmExtension::LPAE))
1827  ttbcrMask.eae = ones;
1828 
1829  if (release->has(ArmExtension::LPAE) && ttbcrNew.eae) {
1830  newVal = newVal & ttbcrMask;
1831  } else {
1832  newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1833  }
1834  // Invalidate TLB MiscReg
1835  getMMUPtr(tc)->invalidateMiscReg();
1836  break;
1837  }
1838  case MISCREG_TTBR0:
1839  case MISCREG_TTBR1:
1840  {
1841  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1842  if (release->has(ArmExtension::LPAE)) {
1843  if (ttbcr.eae) {
1844  // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1845  // ARMv8 AArch32 bit 63-56 only
1846  uint64_t ttbrMask = mask(63,56) | mask(47,40);
1847  newVal = (newVal & (~ttbrMask));
1848  }
1849  }
1850  // Invalidate TLB MiscReg
1851  getMMUPtr(tc)->invalidateMiscReg();
1852  break;
1853  }
1854  case MISCREG_SCTLR_EL1:
1855  case MISCREG_CONTEXTIDR:
1856  case MISCREG_PRRR:
1857  case MISCREG_NMRR:
1858  case MISCREG_MAIR0:
1859  case MISCREG_MAIR1:
1860  case MISCREG_DACR:
1861  case MISCREG_VTTBR:
1862  case MISCREG_SCR_EL3:
1863  case MISCREG_TCR_EL1:
1864  case MISCREG_TCR_EL2:
1865  case MISCREG_TCR_EL3:
1866  case MISCREG_VTCR_EL2:
1867  case MISCREG_SCTLR_EL2:
1868  case MISCREG_SCTLR_EL3:
1869  case MISCREG_HSCTLR:
1870  case MISCREG_TTBR0_EL1:
1871  case MISCREG_TTBR1_EL1:
1872  case MISCREG_TTBR0_EL2:
1873  case MISCREG_TTBR1_EL2:
1874  case MISCREG_TTBR0_EL3:
1875  getMMUPtr(tc)->invalidateMiscReg();
1876  break;
1877  case MISCREG_HCR_EL2:
1878  {
1879  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1880  selfDebug->setenableTDETGE((HCR)val, mdcr);
1881  getMMUPtr(tc)->invalidateMiscReg();
1882  }
1883  break;
1884  case MISCREG_NZCV:
1885  {
1886  CPSR cpsr = val;
1887 
1888  tc->setReg(cc_reg::Nz, cpsr.nz);
1889  tc->setReg(cc_reg::C, cpsr.c);
1890  tc->setReg(cc_reg::V, cpsr.v);
1891  }
1892  break;
1893  case MISCREG_DAIF:
1894  {
1895  CPSR cpsr = miscRegs[MISCREG_CPSR];
1896  cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1897  newVal = cpsr;
1898  misc_reg = MISCREG_CPSR;
1899  }
1900  break;
1901  case MISCREG_SP_EL0:
1902  tc->setReg(int_reg::Sp0, newVal);
1903  break;
1904  case MISCREG_SP_EL1:
1905  tc->setReg(int_reg::Sp1, newVal);
1906  break;
1907  case MISCREG_SP_EL2:
1908  tc->setReg(int_reg::Sp2, newVal);
1909  break;
1910  case MISCREG_SPSEL:
1911  {
1912  CPSR cpsr = miscRegs[MISCREG_CPSR];
1913  cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1914  newVal = cpsr;
1915  misc_reg = MISCREG_CPSR;
1916  }
1917  break;
1918  case MISCREG_CURRENTEL:
1919  {
1920  CPSR cpsr = miscRegs[MISCREG_CPSR];
1921  cpsr.el = (uint8_t) ((CPSR) newVal).el;
1922  newVal = cpsr;
1923  misc_reg = MISCREG_CPSR;
1924  }
1925  break;
1926  case MISCREG_PAN:
1927  {
1928  // PAN is affecting data accesses
1929  getMMUPtr(tc)->invalidateMiscReg();
1930 
1931  CPSR cpsr = miscRegs[MISCREG_CPSR];
1932  cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
1933  newVal = cpsr;
1934  misc_reg = MISCREG_CPSR;
1935  }
1936  break;
1937  case MISCREG_UAO:
1938  {
1939  // UAO is affecting data accesses
1940  getMMUPtr(tc)->invalidateMiscReg();
1941 
1942  CPSR cpsr = miscRegs[MISCREG_CPSR];
1943  cpsr.uao = (uint8_t) ((CPSR) newVal).uao;
1944  newVal = cpsr;
1945  misc_reg = MISCREG_CPSR;
1946  }
1947  break;
1948  case MISCREG_AT_S1E1R_Xt:
1949  addressTranslation64(MMU::S1E1Tran, BaseMMU::Read, 0, val);
1950  return;
1951  case MISCREG_AT_S1E1W_Xt:
1952  addressTranslation64(MMU::S1E1Tran, BaseMMU::Write, 0, val);
1953  return;
1954  case MISCREG_AT_S1E0R_Xt:
1955  addressTranslation64(MMU::S1E0Tran, BaseMMU::Read,
1956  MMU::UserMode, val);
1957  return;
1958  case MISCREG_AT_S1E0W_Xt:
1959  addressTranslation64(MMU::S1E0Tran, BaseMMU::Write,
1960  MMU::UserMode, val);
1961  return;
1962  case MISCREG_AT_S1E2R_Xt:
1963  addressTranslation64(MMU::S1E2Tran, BaseMMU::Read, 0, val);
1964  return;
1965  case MISCREG_AT_S1E2W_Xt:
1966  addressTranslation64(MMU::S1E2Tran, BaseMMU::Write, 0, val);
1967  return;
1968  case MISCREG_AT_S12E1R_Xt:
1969  addressTranslation64(MMU::S12E1Tran, BaseMMU::Read, 0, val);
1970  return;
1971  case MISCREG_AT_S12E1W_Xt:
1972  addressTranslation64(MMU::S12E1Tran, BaseMMU::Write, 0, val);
1973  return;
1974  case MISCREG_AT_S12E0R_Xt:
1975  addressTranslation64(MMU::S12E0Tran, BaseMMU::Read,
1976  MMU::UserMode, val);
1977  return;
1978  case MISCREG_AT_S12E0W_Xt:
1979  addressTranslation64(MMU::S12E0Tran, BaseMMU::Write,
1980  MMU::UserMode, val);
1981  return;
1982  case MISCREG_AT_S1E3R_Xt:
1983  addressTranslation64(MMU::S1E3Tran, BaseMMU::Read, 0, val);
1984  return;
1985  case MISCREG_AT_S1E3W_Xt:
1986  addressTranslation64(MMU::S1E3Tran, BaseMMU::Write, 0, val);
1987  return;
1988  case MISCREG_L2CTLR:
1989  warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
1990  miscRegName[misc_reg], uint32_t(val));
1991  break;
1992 
1993  // Generic Timer registers
1994  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
1995  case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
1996  getGenericTimer().setMiscReg(misc_reg, newVal);
1997  break;
1998  case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
1999  case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
2000  case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2001  getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
2002  return;
2003  case MISCREG_ZCR_EL3:
2004  case MISCREG_ZCR_EL2:
2005  case MISCREG_ZCR_EL1:
2006  tc->getDecoderPtr()->as<Decoder>().setSveLen(
2007  (getCurSveVecLenInBits() >> 7) - 1);
2008  break;
2009  }
2010  setMiscRegNoEffect(misc_reg, newVal);
2011  }
2012 }
2013 
2014 BaseISADevice &
2015 ISA::getGenericTimer()
2016 {
2017  // We only need to create an ISA interface the first time we try
2018  // to access the timer.
2019  if (timer)
2020  return *timer.get();
2021 
2022  assert(system);
2023  GenericTimer *generic_timer(system->getGenericTimer());
2024  if (!generic_timer) {
2025  panic("Trying to get a generic timer from a system that hasn't "
2026  "been configured to use a generic timer.\n");
2027  }
2028 
2029  timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2030  timer->setThreadContext(tc);
2031 
2032  return *timer.get();
2033 }
2034 
2035 BaseISADevice &
2036 ISA::getGICv3CPUInterface()
2037 {
2038  panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2039  return *gicv3CpuInterface.get();
2040 }
2041 
2042 bool
2043 ISA::inSecureState() const
2044 {
2045  if (!release->has(ArmExtension::SECURITY)) {
2046  return false;
2047  }
2048 
2049  SCR scr = miscRegs[MISCREG_SCR];
2050  CPSR cpsr = miscRegs[MISCREG_CPSR];
2051 
2052  switch ((OperatingMode) (uint8_t) cpsr.mode) {
2053  case MODE_MON:
2054  case MODE_EL3T:
2055  case MODE_EL3H:
2056  return true;
2057  case MODE_HYP:
2058  case MODE_EL2T:
2059  case MODE_EL2H:
2060  return false;
2061  default:
2062  return !scr.ns;
2063  }
2064 }
2065 
2066 ExceptionLevel
2067 ISA::currEL() const
2068 {
2069  CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
2070 
2071  return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
2072 }
2073 
2074 unsigned
2075 ISA::getCurSveVecLenInBits() const
2076 {
2077  if (!FullSystem) {
2078  return sveVL * 128;
2079  }
2080 
2081  panic_if(!tc,
2082  "A ThreadContext is needed to determine the SVE vector length "
2083  "in full-system mode");
2084 
2085  CPSR cpsr = miscRegs[MISCREG_CPSR];
2086  ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2087 
2088  unsigned len = 0;
2089 
2090  if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2091  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2092  }
2093 
2094  if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2095  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2096  } else if (release->has(ArmExtension::VIRTUALIZATION) && !isSecure(tc) &&
2097  (el == EL0 || el == EL1)) {
2098  len = std::min(
2099  len,
2100  static_cast<unsigned>(
2101  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2102  }
2103 
2104  if (el == EL3) {
2105  len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2106  } else if (release->has(ArmExtension::SECURITY)) {
2107  len = std::min(
2108  len,
2109  static_cast<unsigned>(
2110  static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2111  }
2112 
2113  len = std::min(len, sveVL - 1);
2114 
2115  return (len + 1) * 128;
2116 }
2117 
2118 void
2119 ISA::serialize(CheckpointOut &cp) const
2120 {
2121  DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
2122  SERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2123 }
2124 
2125 void
2126 ISA::unserialize(CheckpointIn &cp)
2127 {
2128  DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
2129  UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2130  CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
2131  updateRegMap(tmp_cpsr);
2132 }
2133 
2134 void
2135 ISA::addressTranslation64(MMU::ArmTranslationType tran_type,
2136  BaseMMU::Mode mode, Request::Flags flags, RegVal val)
2137 {
2138  // If we're in timing mode then doing the translation in
2139  // functional mode then we're slightly distorting performance
2140  // results obtained from simulations. The translation should be
2141  // done in the same mode the core is running in. NOTE: This
2142  // can't be an atomic translation because that causes problems
2143  // with unexpected atomic snoop requests.
2144  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2145 
2146  auto req = std::make_shared<Request>(
2147  val, 0, flags, Request::funcRequestorId,
2148  tc->pcState().instAddr(), tc->contextId());
2149 
2150  Fault fault = getMMUPtr(tc)->translateFunctional(
2151  req, tc, mode, tran_type);
2152 
2153  PAR par = 0;
2154  if (fault == NoFault) {
2155  Addr paddr = req->getPaddr();
2156  uint64_t attr = getMMUPtr(tc)->getAttr();
2157  uint64_t attr1 = attr >> 56;
2158  if (!attr1 || attr1 ==0x44) {
2159  attr |= 0x100;
2160  attr &= ~ uint64_t(0x80);
2161  }
2162  par = (paddr & mask(47, 12)) | attr;
2163  DPRINTF(MiscRegs,
2164  "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2165  val, par);
2166  } else {
2167  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2168  arm_fault->update(tc);
2169  // Set fault bit and FSR
2170  FSR fsr = arm_fault->getFsr(tc);
2171 
2172  par.f = 1; // F bit
2173  par.fst = fsr.status; // FST
2174  par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
2175  par.s = arm_fault->isStage2() ? 1 : 0; // S
2176 
2177  DPRINTF(MiscRegs,
2178  "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2179  val, fsr, par);
2180  }
2181  setMiscRegNoEffect(MISCREG_PAR_EL1, par);
2182  return;
2183 }
2184 
2185 void
2186 ISA::addressTranslation(MMU::ArmTranslationType tran_type,
2187  BaseMMU::Mode mode, Request::Flags flags, RegVal val)
2188 {
2189  // If we're in timing mode then doing the translation in
2190  // functional mode then we're slightly distorting performance
2191  // results obtained from simulations. The translation should be
2192  // done in the same mode the core is running in. NOTE: This
2193  // can't be an atomic translation because that causes problems
2194  // with unexpected atomic snoop requests.
2195  warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2196 
2197  auto req = std::make_shared<Request>(
2198  val, 0, flags, Request::funcRequestorId,
2199  tc->pcState().instAddr(), tc->contextId());
2200 
2201  Fault fault = getMMUPtr(tc)->translateFunctional(
2202  req, tc, mode, tran_type);
2203 
2204  PAR par = 0;
2205  if (fault == NoFault) {
2206  Addr paddr = req->getPaddr();
2207  TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2208  HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
2209 
2210  uint8_t max_paddr_bit = 0;
2211  if (release->has(ArmExtension::LPAE) &&
2212  (ttbcr.eae || tran_type & MMU::HypMode ||
2213  ((tran_type & MMU::S1S2NsTran) && hcr.vm) )) {
2214 
2215  max_paddr_bit = 39;
2216  } else {
2217  max_paddr_bit = 31;
2218  }
2219 
2220  par = (paddr & mask(max_paddr_bit, 12)) |
2221  (getMMUPtr(tc)->getAttr());
2222 
2223  DPRINTF(MiscRegs,
2224  "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2225  val, par);
2226  } else {
2227  ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2228  arm_fault->update(tc);
2229  // Set fault bit and FSR
2230  FSR fsr = arm_fault->getFsr(tc);
2231 
2232  par.f = 0x1; // F bit
2233  par.lpae = fsr.lpae;
2234  par.ptw = (arm_fault->iss() >> 7) & 0x1;
2235  par.s = arm_fault->isStage2() ? 1 : 0;
2236 
2237  if (par.lpae) {
2238  // LPAE - rearange fault status
2239  par.fst = fsr.status;
2240  } else {
2241  // VMSA - rearange fault status
2242  par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
2243  par.fs5 = fsr.ext;
2244  }
2245  DPRINTF(MiscRegs,
2246  "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2247  val, fsr, par);
2248  }
2249  setMiscRegNoEffect(MISCREG_PAR, par);
2250  return;
2251 }
2252 
2253 ISA::MiscRegLUTEntryInitializer::chain
2254 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2255 {
2256  switch (FullSystem ? sys->highestEL() : EL1) {
2257  case EL0:
2258  case EL1: priv(); break;
2259  case EL2: hyp(); break;
2260  case EL3: mon(); break;
2261  }
2262  return *this;
2263 }
2264 
2265 template <class XC>
2266 static inline void
2267 lockedSnoopHandler(ThreadContext *tc, XC *xc, PacketPtr pkt,
2268  Addr cacheBlockMask)
2269 {
2270  // Should only every see invalidations / direct writes
2271  assert(pkt->isInvalidate() || pkt->isWrite());
2272 
2273  DPRINTF(LLSC, "%s: handling snoop for address: %#x locked: %d\n",
2274  tc->getCpuPtr()->name(), pkt->getAddr(),
2275  xc->readMiscReg(MISCREG_LOCKFLAG));
2276  if (!xc->readMiscReg(MISCREG_LOCKFLAG))
2277  return;
2278 
2279  Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
2280  // If no caches are attached, the snoop address always needs to be masked
2281  Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
2282 
2283  DPRINTF(LLSC, "%s: handling snoop for address: %#x locked addr: %#x\n",
2284  tc->getCpuPtr()->name(), snoop_addr, locked_addr);
2285  if (locked_addr == snoop_addr) {
2286  DPRINTF(LLSC, "%s: address match, clearing lock and signaling sev\n",
2287  tc->getCpuPtr()->name());
2288  xc->setMiscReg(MISCREG_LOCKFLAG, false);
2289  // Implement ARMv8 WFE/SEV semantics
2290  sendEvent(tc);
2291  xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2292  }
2293 }
2294 
2295 void
2296 ISA::handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
2297 {
2298  lockedSnoopHandler(tc, tc, pkt, cacheBlockMask);
2299 }
2300 
2301 void
2302 ISA::handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)
2303 {
2304  lockedSnoopHandler(xc->tcBase(), xc, pkt, cacheBlockMask);
2305 }
2306 
2307 void
2308 ISA::handleLockedRead(const RequestPtr &req)
2309 {
2310  tc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
2311  tc->setMiscReg(MISCREG_LOCKFLAG, true);
2312  DPRINTF(LLSC, "%s: Placing address %#x in monitor\n",
2313  tc->getCpuPtr()->name(), req->getPaddr());
2314 }
2315 
2316 void
2317 ISA::handleLockedRead(ExecContext *xc, const RequestPtr &req)
2318 {
2319  xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
2320  xc->setMiscReg(MISCREG_LOCKFLAG, true);
2321  DPRINTF(LLSC, "%s: Placing address %#x in monitor\n",
2322  xc->tcBase()->getCpuPtr()->name(), req->getPaddr());
2323 }
2324 
2325 void
2326 ISA::handleLockedSnoopHit()
2327 {
2328  DPRINTF(LLSC, "%s: handling snoop lock hit address: %#x\n",
2329  tc->getCpuPtr()->name(), tc->readMiscReg(MISCREG_LOCKADDR));
2330  tc->setMiscReg(MISCREG_LOCKFLAG, false);
2331  tc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2332 }
2333 
2334 void
2335 ISA::handleLockedSnoopHit(ExecContext *xc)
2336 {
2337  DPRINTF(LLSC, "%s: handling snoop lock hit address: %#x\n",
2338  xc->tcBase()->getCpuPtr()->name(),
2339  xc->readMiscReg(MISCREG_LOCKADDR));
2340  xc->setMiscReg(MISCREG_LOCKFLAG, false);
2341  xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2342 }
2343 
2344 template <class XC>
2345 static inline bool
2346 lockedWriteHandler(ThreadContext *tc, XC *xc, const RequestPtr &req,
2347  Addr cacheBlockMask)
2348 {
2349  if (req->isSwap())
2350  return true;
2351 
2352  DPRINTF(LLSC, "Handling locked write for address %#x in monitor.\n",
2353  req->getPaddr());
2354  // Verify that the lock flag is still set and the address
2355  // is correct
2356  bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
2357  Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
2358  if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
2359  // Lock flag not set or addr mismatch in CPU;
2360  // don't even bother sending to memory system
2361  req->setExtraData(0);
2362  xc->setMiscReg(MISCREG_LOCKFLAG, false);
2363  DPRINTF(LLSC, "clearing lock flag in handle locked write\n",
2364  tc->getCpuPtr()->name());
2365  // the rest of this code is not architectural;
2366  // it's just a debugging aid to help detect
2367  // livelock by warning on long sequences of failed
2368  // store conditionals
2369  int stCondFailures = xc->readStCondFailures();
2370  stCondFailures++;
2371  xc->setStCondFailures(stCondFailures);
2372  if (stCondFailures % 100000 == 0) {
2373  warn("context %d: %d consecutive "
2374  "store conditional failures\n",
2375  tc->contextId(), stCondFailures);
2376  }
2377 
2378  // store conditional failed already, so don't issue it to mem
2379  return false;
2380  }
2381  return true;
2382 }
2383 
2384 bool
2385 ISA::handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
2386 {
2387  return lockedWriteHandler(tc, tc, req, cacheBlockMask);
2388 }
2389 
2390 bool
2391 ISA::handleLockedWrite(ExecContext *xc, const RequestPtr &req,
2392  Addr cacheBlockMask)
2393 {
2394  return lockedWriteHandler(xc->tcBase(), xc, req, cacheBlockMask);
2395 }
2396 
2397 void
2398 ISA::globalClearExclusive()
2399 {
2400  // A spinlock would typically include a Wait For Event (WFE) to
2401  // conserve energy. The ARMv8 architecture specifies that an event
2402  // is automatically generated when clearing the exclusive monitor
2403  // to wake up the processor in WFE.
2404  DPRINTF(LLSC, "Clearing lock and signaling sev\n");
2405  tc->setMiscReg(MISCREG_LOCKFLAG, false);
2406  // Implement ARMv8 WFE/SEV semantics
2407  sendEvent(tc);
2408  tc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2409 }
2410 
2411 void
2412 ISA::globalClearExclusive(ExecContext *xc)
2413 {
2414  // A spinlock would typically include a Wait For Event (WFE) to
2415  // conserve energy. The ARMv8 architecture specifies that an event
2416  // is automatically generated when clearing the exclusive monitor
2417  // to wake up the processor in WFE.
2418  DPRINTF(LLSC, "Clearing lock and signaling sev\n");
2419  xc->setMiscReg(MISCREG_LOCKFLAG, false);
2420  // Implement ARMv8 WFE/SEV semantics
2421  sendEvent(xc->tcBase());
2422  xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
2423 }
2424 
2425 } // namespace ArmISA
2426 } // namespace gem5
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: misc.hh:576
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: misc.hh:617
gem5::ArmISA::MODE_EL2H
@ MODE_EL2H
Definition: types.hh:285
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: misc.hh:650
gem5::ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: misc.hh:166
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: misc.hh:246
gic_v3_cpu_interface.hh
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
gem5::ArmISA::BaseISADevice::setISA
virtual void setISA(ISA *isa)
Definition: isa_device.cc:55
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition: misc.hh:220
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:589
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: misc.hh:484
gem5::ArmISA::MMU::S12E0Tran
@ S12E0Tran
Definition: mmu.hh:130
gem5::ArmSystem::physAddrRange
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:213
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: misc.hh:449
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: misc.hh:352
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: misc.hh:428
gem5::ArmISA::ISA::addressTranslation64
void addressTranslation64(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2135
gem5::ArmISA::SelfDebug::setenableTDETGE
void setenableTDETGE(HCR hcr, HDCR mdcr)
Definition: self_debug.hh:397
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition: pcstate.hh:107
gem5::BaseMMU::Read
@ Read
Definition: mmu.hh:56
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: misc.hh:231
gem5::ArmISA::SelfDebug::init
void init(ThreadContext *tc)
Definition: self_debug.cc:331
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: misc.hh:96
gem5::ArmISA::MMU::S12E1Tran
@ S12E1Tran
Definition: mmu.hh:131
gem5::ArmISA::ISA::dummyDevice
DummyISADevice dummyDevice
Dummy device for to handle non-existing ISA devices.
Definition: isa.hh:78
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: misc.hh:604
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: misc.hh:729
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:675
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_TVAL_EL2
Definition: misc.hh:787
gem5::ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: misc.hh:132
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:253
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ArmISA::ISA::currEL
ExceptionLevel currEL() const
Returns the current Exception Level (EL) of the ISA object.
Definition: isa.cc:2067
gem5::ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition: misc.hh:730
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:292
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:445
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: misc.hh:253
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: misc.hh:597
gem5::ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: misc.hh:368
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: misc.hh:610
warn
#define warn(...)
Definition: logging.hh:246
gem5::System::Threads::size
int size() const
Definition: system.hh:214
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: misc.hh:226
gem5::ArmISA::vecRegClassOps
TypedRegClassOps< ArmISA::VecRegContainer > vecRegClassOps
Definition: isa.cc:88
gem5::ArmISA::ISA::selfDebug
SelfDebug * selfDebug
Definition: isa.hh:108
gem5::ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: misc.hh:385
gem5::ArmISA::MISCREG_CNTP_CTL_EL02
@ MISCREG_CNTP_CTL_EL02
Definition: misc.hh:763
gem5::ArmISA::BaseISADevice::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Read a system register belonging to this device.
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ExecContext::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Sets a miscellaneous register, handling any architectural side effects due to writing that register.
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: misc.hh:592
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: misc.hh:521
gem5::ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: misc.hh:382
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: misc.hh:678
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:802
system.hh
gem5::ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2075
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:183
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: misc.hh:510
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: misc.hh:619
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: misc.hh:255
gem5::ArmISA::ISA::gicv3CpuInterface
std::unique_ptr< BaseISADevice > gicv3CpuInterface
Definition: isa.hh:87
gem5::igbreg::txd_op::ic
bool ic(TxDesc *d)
Definition: i8254xGBe_defs.hh:304
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: misc.hh:416
gem5::Gicv3::getCPUInterface
Gicv3CPUInterface * getCPUInterface(int cpu_id) const
Definition: gic_v3.hh:178
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:676
gem5::ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: misc.hh:170
gem5::ArmISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:753
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:80
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: misc.hh:165
gem5::ArmISA::ISA::clear
void clear()
Definition: isa.cc:146
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: misc.hh:210
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: misc.hh:414
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:478
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: misc.hh:400
gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
Definition: misc.hh:780
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:760
gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
Definition: misc.hh:786
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: misc.hh:308
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: misc.hh:605
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: misc.hh:490
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:757
gem5::ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: misc.hh:243
gem5::ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition: misc.hh:651
gem5::ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: misc.hh:71
gem5::ArmISA::MMU::getAttr
uint64_t getAttr() const
Definition: mmu.hh:369
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: misc.hh:234
gem5::ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: misc.hh:237
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: misc.hh:163
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: misc.hh:128
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:588
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:476
gem5::ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: misc.hh:164
gem5::ArmISA::ISA::haveLargeAsid64
bool haveLargeAsid64
Definition: isa.hh:91
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: misc.hh:73
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition: isa.hh:292
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: misc.hh:311
gem5::ArmISA::MODE_EL2T
@ MODE_EL2T
Definition: types.hh:284
gem5::ArmISA::ISA::takeOverFrom
void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override
Definition: isa.cc:557
gem5::ArmISA::ISA::handleLockedSnoop
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
Definition: isa.cc:2296
gem5::ArmISA::ISA::initID32
void initID32(const ArmISAParams &p)
Definition: isa.cc:339
gem5::InstDecoder::as
Type & as()
Definition: decoder.hh:71
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::ArmISA::attr
attr
Definition: misc_types.hh:656
gem5::ArmISA::lockedWriteHandler
static bool lockedWriteHandler(ThreadContext *tc, XC *xc, const RequestPtr &req, Addr cacheBlockMask)
Definition: isa.cc:2346
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: misc.hh:620
gem5::ArmISA::MODE_EL1H
@ MODE_EL1H
Definition: types.hh:283
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::ArmISA::ISA::updateRegMap
void updateRegMap(CPSR cpsr)
Definition: isa.hh:573
gem5::BaseMMU::Write
@ Write
Definition: mmu.hh:56
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:594
gem5::ArmISA::ISA::release
const ArmRelease * release
This could be either a FS or a SE release.
Definition: isa.hh:98
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:519
gem5::ArmISA::ISA::timer
std::unique_ptr< BaseISADevice > timer
Definition: isa.hh:84
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: misc.hh:123
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition: utility.cc:1316
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:621
gem5::ArmISA::MISCREG_CNTP_TVAL
@ MISCREG_CNTP_TVAL
Definition: misc.hh:423
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: misc.hh:600
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: misc.hh:741
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: misc.hh:261
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: misc.hh:644
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: misc.hh:202
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:247
gem5::ArmISA::SelfDebug::updateOSLock
void updateOSLock(RegVal val)
Definition: self_debug.hh:403
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: misc.hh:645
gem5::ArmISA::MMU::S1E0Tran
@ S1E0Tran
Definition: mmu.hh:126
gem5::ArmSystem::haveLargeAsid64
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:202
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: misc.hh:663
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:516
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:517
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: misc.hh:530
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:483
gem5::ArmISA::MMU::S1CTran
@ S1CTran
Definition: mmu.hh:117
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:711
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:591
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: misc.hh:209
gem5::ArmISA::daif
Bitfield< 9, 6 > daif
Definition: misc_types.hh:70
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:746
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: misc.hh:567
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1273
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: misc.hh:611
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: misc.hh:291
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: misc.hh:83
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: misc.hh:159
gem5::ArmISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:564
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: misc.hh:224
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:488
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:570
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:487
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: misc.hh:219
gem5::ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: misc.hh:168
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:390
std::vector
STL vector class.
Definition: stl.hh:37
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: misc.hh:188
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:287
gem5::ArmISA::CpsrMaskQ
static const uint32_t CpsrMaskQ
Definition: misc.hh:2293
gem5::ThreadContext::getRegFlat
virtual RegVal getRegFlat(const RegId &reg) const
Flat register interfaces.
Definition: thread_context.cc:201
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: misc.hh:367
gem5::ArmISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:2119
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: misc.hh:727
gem5::ArmISA::MMU::S1E3Tran
@ S1E3Tran
Definition: mmu.hh:129
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: misc.hh:371
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: misc.hh:222
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: misc.hh:310
gem5::ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition: misc.hh:616
gem5::VegaISA::r
Bitfield< 5 > r
Definition: pagetable.hh:60
SERIALIZE_MAPPING
#define SERIALIZE_MAPPING(member, names, size)
Definition: serialize.hh:660
gem5::ExecContext::readMiscReg
virtual RegVal readMiscReg(int misc_reg)=0
Reads a miscellaneous register, handling any architectural side effects due to reading that register.
gem5::ArmISA::FpscrQcMask
static const uint32_t FpscrQcMask
Definition: misc.hh:2310
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: misc.hh:915
gem5::ArmISA::ISA::sveVL
unsigned sveVL
SVE vector length in quadwords.
Definition: isa.hh:95
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::chain
const typedef MiscRegLUTEntryInitializer & chain
Definition: isa.hh:140
gem5::ArmISA::MISCREG_CNTV_CVAL_EL02
@ MISCREG_CNTV_CVAL_EL02
Definition: misc.hh:767
gem5::TypedRegClassOps
Definition: reg_class.hh:210
system.hh
gem5::ArmISA::MISCREG_IMPLEMENTED
@ MISCREG_IMPLEMENTED
Definition: misc.hh:1101
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:565
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:236
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: misc.hh:656
faults.hh
gem5::ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: misc.hh:960
gem5::ArmISA::MODE_EL3H
@ MODE_EL3H
Definition: types.hh:287
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:756
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:755
gem5::ArmISA::FpscrExcMask
static const uint32_t FpscrExcMask
Definition: misc.hh:2314
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:512
gem5::ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: misc.hh:162
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: misc.hh:417
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: misc.hh:200
gem5::ArmISA::SelfDebug::updateDBGBCR
void updateDBGBCR(int index, DBGBCR val)
Definition: self_debug.hh:409
gem5::ArmISA::MISCREG_CNTP_TVAL_EL02
@ MISCREG_CNTP_TVAL_EL02
Definition: misc.hh:765
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: misc.hh:217
gem5::ArmISA::MISCREG_CNTV_TVAL_EL02
@ MISCREG_CNTV_TVAL_EL02
Definition: misc.hh:768
gem5::ArmSystem::getGIC
BaseGic * getGIC() const
Get a pointer to the system's GIC.
Definition: system.hh:176
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: misc.hh:138
gem5::ArmISA::MISCREG_CNTKCTL_EL12
@ MISCREG_CNTKCTL_EL12
Definition: misc.hh:770
gem5::ArmISA::MMU::S1E2Tran
@ S1E2Tran
Definition: mmu.hh:128
gem5::ArmISA::getMMUPtr
MMU * getMMUPtr(T *tc)
Definition: mmu.hh:512
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:545
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: misc.hh:203
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: misc.hh:607
gem5::ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: misc.hh:129
gem5::ArmISA::miscRegInfo
std::bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: misc.cc:806
gem5::System::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: system.hh:312
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:513
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: misc.hh:266
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:252
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: misc.hh:158
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: misc.hh:221
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:769
gem5::ArmISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:1089
gem5::ArmISA::ISA::initID64
void initID64(const ArmISAParams &p)
Definition: isa.cc:392
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: misc.hh:104
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: misc.hh:731
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: misc.hh:218
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: misc.hh:272
gem5::ArmISA::cc_reg::Nz
constexpr RegId Nz(CCRegClass, _NzIdx)
gem5::ArmISA::SelfDebug::setbSDD
void setbSDD(RegVal val)
Definition: self_debug.hh:377
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition: misc.hh:601
mmu.hh
gem5::ArmISA::ISA::handleLockedRead
void handleLockedRead(const RequestPtr &req) override
Definition: isa.cc:2308
gem5::ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: misc.hh:238
gem5::ArmISA::vecRegElemClassOps
VecElemRegClassOps< ArmISA::VecElem > vecRegElemClassOps(NumVecElemPerVecReg)
gem5::ArmISA::ArmFault::iss
virtual uint32_t iss() const =0
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: misc.hh:522
gem5::ArmISA::MMU::UserMode
@ UserMode
Definition: mmu.hh:111
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition: misc.hh:777
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition: system.hh:75
gem5::ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: misc.hh:250
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:774
htm.hh
gem5::ArmISA::Interrupts
Definition: interrupts.hh:71
gem5::Flags< FlagsType >
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: misc.hh:434
gem5::ArmISA::MODE_EL3T
@ MODE_EL3T
Definition: types.hh:286
gem5::ArmISA::SelfDebug::setMDBGen
void setMDBGen(RegVal val)
Definition: self_debug.hh:391
gem5::ArmISA::ISA::pmu
BaseISADevice * pmu
Definition: isa.hh:81
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: misc.hh:615
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: misc.hh:124
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: misc.hh:370
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:67
gem5::ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: vec.hh:81
decoder.hh
gem5::ThreadContext::setHtmCheckpointPtr
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:187
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: misc.hh:155
gem5::ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: misc.hh:739
gem5::ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: misc.hh:131
interrupts.hh
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: misc.hh:133
gem5::ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: misc.hh:169
gem5::ArmISA::ISA::handleLockedSnoopHit
void handleLockedSnoopHit() override
Definition: isa.cc:2326
gem5::ArmISA::cc_reg::NumRegs
@ NumRegs
Definition: cc.hh:60
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: misc.hh:307
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: misc.hh:563
gem5::ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition: misc.hh:581
gem5::ArmISA::SelfDebug::setMDSCRvals
void setMDSCRvals(RegVal val)
Definition: self_debug.hh:383
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:509
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:294
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: misc.hh:126
gem5::ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition: misc.hh:584
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:580
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:823
gem5::ArmISA::ISA::clear64
void clear64(const ArmISAParams &p)
Definition: isa.cc:290
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: misc.hh:223
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: misc.hh:1052
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: misc.hh:251
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:596
gem5::ArmISA::cc_reg::V
constexpr RegId V(CCRegClass, _VIdx)
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: misc.hh:225
gem5::ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition: misc.hh:603
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition: misc.hh:747
gem5::ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: misc.hh:137
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: misc.hh:395
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: misc.hh:726
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: misc.hh:160
gem5::ThreadContext::getDecoderPtr
virtual InstDecoder * getDecoderPtr()=0
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: misc.hh:379
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: misc.hh:732
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: misc.hh:75
gem5::ArmISA::ISA::globalClearExclusive
void globalClearExclusive() override
Definition: isa.cc:2398
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: misc.hh:540
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:661
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition: misc.hh:776
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: misc.hh:585
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: misc.hh:566
gem5::ArmISA::ISA::getMiscIndices
std::pair< int, int > getMiscIndices(int misc_reg) const
Definition: isa.hh:874
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1096
isa.hh
gem5::ArmISA::uao
Bitfield< 23 > uao
Definition: misc_types.hh:58
gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2
@ MISCREG_CNTHVS_CTL_EL2
Definition: misc.hh:785
gem5::ArmISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:2126
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:279
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::ArmISA::ArmFault::update
void update(ThreadContext *tc)
Definition: faults.cc:428
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: misc.hh:228
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:511
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::ArmISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:91
gem5::ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: misc.hh:74
cpu.hh
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition: isa.hh:454
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: misc.hh:235
gem5::ArmISA::ISA::addressTranslation
void addressTranslation(MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Definition: isa.cc:2186
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: misc.hh:90
gem5::ArmISA::Decoder
Definition: decoder.hh:63
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: misc.hh:508
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::GenericTimer
Definition: generic_timer.hh:286
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: misc.hh:883
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: misc.hh:583
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: misc.hh:320
gem5::ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: misc.hh:134
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: misc.hh:618
gem5::ArmISA::pan
Bitfield< 22 > pan
Definition: misc_types.hh:59
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: misc.hh:541
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: misc.hh:239
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: misc.hh:626
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:666
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: misc.hh:628
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: misc.hh:662
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: misc.hh:397
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: misc.hh:742
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: misc.hh:215
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: misc.hh:206
cprintf.hh
gem5::insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:166
gem5::ArmISA::ISA::handleLockedWrite
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
Definition: isa.cc:2385
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
flags
uint8_t flags
Definition: helpers.cc:66
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:479
gem5::ArmISA::miscRegClassOps
gem5::ArmISA::MiscRegClassOps miscRegClassOps
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::ArmISA::ISA::getGICv3CPUInterface
BaseISADevice & getGICv3CPUInterface()
Definition: isa.cc:2036
gem5::ArmISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:777
gem5::ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: misc.hh:295
gem5::ArmISA::MISCREG_CNTP_CVAL
@ MISCREG_CNTP_CVAL
Definition: misc.hh:420
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:288
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition: misc.hh:775
gem5::ThreadContext::setRegFlat
virtual void setRegFlat(const RegId &reg, RegVal val)
Definition: thread_context.cc:209
gem5::ArmISA::MISCREG_CNTV_CTL_EL02
@ MISCREG_CNTV_CTL_EL02
Definition: misc.hh:766
gem5::ArmISA::ISA::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: isa.cc:519
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: misc.hh:213
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:564
faults.hh
generic_timer.hh
gem5::ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition: misc.hh:427
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: misc.hh:761
gem5::ArmISA::ISA::getGenericTimer
BaseISADevice & getGenericTimer()
Definition: isa.cc:2015
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: misc.hh:290
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:571
gem5::ArmISA::MISCREG_ZCR_EL12
@ MISCREG_ZCR_EL12
Definition: misc.hh:1058
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: misc.hh:613
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: misc.hh:744
gem5::ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: misc.hh:394
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: misc.hh:208
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: misc.hh:135
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: misc.hh:377
gem5::ArmISA::MISCREG_LOCKADDR
@ MISCREG_LOCKADDR
Definition: misc.hh:82
gem5::ArmISA::cc_reg::C
constexpr RegId C(CCRegClass, _CIdx)
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: misc.hh:269
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: misc.hh:376
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:475
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: misc.hh:759
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: misc.hh:643
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: misc.hh:673
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: misc.hh:258
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:73
gem5::ArmISA::MMU::HypMode
@ HypMode
Definition: mmu.hh:118
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: misc.cc:1325
gem5::ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: misc.hh:289
gem5::ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition: misc.hh:639
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: misc.hh:635
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:569
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:672
gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: misc.hh:1055
gem5::ArmISA::ArmFault::getFsr
virtual FSR getFsr(ThreadContext *tc) const
Definition: faults.hh:256
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: misc.hh:156
utility.hh
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:482
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition: isa.hh:90
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:480
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:279
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: misc.hh:373
gem5::ArmISA::HTMCheckpoint
Definition: htm.hh:58
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: misc.hh:485
gem5::ArmISA::ArmFault
Definition: faults.hh:64
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: misc.hh:127
gem5::ArmISA::ISA::setupThreadContext
void setupThreadContext()
Definition: isa.cc:536
gem5::ArmISA::ISA::lookUpMiscReg
static std::vector< struct MiscRegLUTEntry > lookUpMiscReg
Metadata table accessible via the value of the register.
Definition: isa.hh:134
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:789
gem5::ThreadContext::pcStateNoRecord
virtual void pcStateNoRecord(const PCStateBase &val)=0
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: misc.hh:507
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: misc.hh:309
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: misc.hh:230
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: misc.hh:161
stat_control.hh
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:518
gem5::ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: misc.hh:81
gem5::ArmISA::MMU::ArmTranslationType
ArmTranslationType
Definition: mmu.hh:114
gem5::Gicv3
Definition: gic_v3.hh:95
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: misc.hh:306
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::ArmISA::MMU::S1S2NsTran
@ S1S2NsTran
Definition: mmu.hh:121
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: misc.hh:207
gem5::ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: misc.hh:1092
gem5::ArmSystem
Definition: system.hh:91
gem5::ArmISA::BaseISADevice::setThreadContext
virtual void setThreadContext(ThreadContext *tc)
Definition: isa_device.hh:68
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: misc.hh:249
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: misc.hh:286
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: misc.hh:321
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition: isa.cc:2254
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: misc.hh:262
gem5::Gicv3CPUInterface
Definition: gic_v3_cpu_interface.hh:58
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: misc.hh:312
gem5::ArmSystem::sveVL
unsigned sveVL() const
Returns the SVE vector length at reset, in quadwords.
Definition: system.hh:205
gem5::ArmISA::MiscRegClassOps
Definition: isa.cc:77
base.hh
gem5::ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: misc.hh:80
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:677
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:758
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: misc.hh:72
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: misc.hh:1059
gem5::SimObject::startup
virtual void startup()
startup() is the final initialization call before simulation.
Definition: sim_object.cc:99
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: misc.hh:229
gem5::ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: misc.hh:886
gem5::ArmISA::MMU::translateFunctional
TranslationGenPtr translateFunctional(Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
Returns a translation generator for a region of virtual addresses, instead of directly translating a ...
Definition: mmu.hh:91
gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition: misc.hh:784
gem5::ArmISA::ISA::miscRegs
RegVal miscRegs[NUM_MISCREGS]
Definition: isa.hh:569
gem5::ArmISA::lockedSnoopHandler
static void lockedSnoopHandler(ThreadContext *tc, XC *xc, PacketPtr pkt, Addr cacheBlockMask)
Definition: isa.cc:2267
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: misc.hh:125
misc.hh
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:64
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:477
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:514
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::ISA::system
ArmSystem * system
Definition: isa.hh:72
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: misc.hh:189
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: misc.hh:838
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: misc.hh:244
reg_class.hh
gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2
@ MISCREG_CNTHPS_CTL_EL2
Definition: misc.hh:778
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: misc.hh:627
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: misc.hh:212
gem5::ArmSystem::resetAddr
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:198
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: misc.hh:579
gem5::ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition: misc.hh:728
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::VecElemRegClassOps
Definition: reg_class.hh:222
gem5::ArmSystem::releaseFS
const ArmRelease * releaseFS() const
Definition: system.hh:152
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:791
gem5::ArmSystem::getGenericTimer
GenericTimer * getGenericTimer() const
Get a pointer to the system's generic timer model.
Definition: system.hh:173
gem5::ArmISA::MMU::invalidateMiscReg
void invalidateMiscReg()
Definition: mmu.cc:197
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: misc.hh:211
pmu.hh
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:481
gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_CVAL_EL2
Definition: misc.hh:779
gem5::ArmISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:1111
gem5::ArmISA::BaseISADevice::setMiscReg
virtual void setMiscReg(int misc_reg, RegVal val)=0
Write to a system register belonging to this device.
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:623
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: misc.hh:1056
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmISA::NUM_PHYS_MISCREGS
@ NUM_PHYS_MISCREGS
Definition: misc.hh:1066
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ArmISA::MMU::S1E1Tran
@ S1E1Tran
Definition: mmu.hh:127
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: misc.hh:636
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition: misc.hh:637
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition: misc.hh:227
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:818
gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition: misc.hh:783
gem5::ArmISA::ISA::physAddrRange
uint8_t physAddrRange
Definition: isa.hh:92
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: misc.hh:577
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:622
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::ArmISA::ISA::redirectRegVHE
int redirectRegVHE(int misc_reg)
Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at ...
Definition: isa.cc:607
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: misc.hh:754
gem5::ArmISA::SelfDebug::updateDBGWCR
void updateDBGWCR(int index, DBGWCR val)
Definition: self_debug.hh:415
self_debug.hh
gem5::BaseISA
Definition: isa.hh:57
gem5::ArmISA::ISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition: isa.hh:400
gem5::ArmISA::sp
Bitfield< 0 > sp
Definition: misc_types.hh:75
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: misc.hh:157
gem5::ArmISA::ISA::afterStartup
bool afterStartup
Definition: isa.hh:106
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:674
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:587
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: misc.hh:638
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: misc.hh:305
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: misc.hh:598
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:486
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: misc.hh:1057
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: misc.hh:652
gem5::ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: misc.hh:91
decoder.hh
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:515
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:562
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: misc.hh:97
gem5::ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: misc.hh:167
gem5::ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition: misc.hh:599
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: misc.hh:426
gem5::ArmISA::SelfDebug::setDebugMask
void setDebugMask(bool mask)
Definition: self_debug.hh:421
gem5::ArmISA::ArmFault::isStage2
virtual bool isStage2() const
Definition: faults.hh:255
gem5::GenericTimerISA
Definition: generic_timer.hh:399
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition: misc.hh:782
gem5::ArmISA::MISCREG_CNTP_CVAL_EL02
@ MISCREG_CNTP_CVAL_EL02
Definition: misc.hh:764
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: misc.hh:640
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: misc.hh:216
gem5::ArmISA::MMU
Definition: mmu.hh:60
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: misc.hh:737
UNSERIALIZE_MAPPING
#define UNSERIALIZE_MAPPING(member, names, size)
Definition: serialize.hh:666
gem5::ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition: misc.hh:641
gem5::loader::Arm
@ Arm
Definition: object_file.hh:71
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: misc.hh:242
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: misc.hh:456
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:489
gem5::ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
gem5::ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition: misc.hh:738
gic_v3.hh
gem5::ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: misc.cc:702
gem5::ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: misc.hh:130
gem5::ArmISA::ISA::clear32
void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
Definition: isa.cc:238
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: misc.hh:740
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: misc.hh:568
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: misc.hh:529
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:660
gem5::RegClassOps
Definition: reg_class.hh:72
gem5::ArmISA::readMPIDR
RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR),...
Definition: utility.cc:143
gem5::ArmISA::MISCREG_UAO
@ MISCREG_UAO
Definition: misc.hh:1093
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: misc.hh:821
gem5::ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: misc.hh:136
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: misc.hh:214
gem5::ArmISA::MiscRegClassOps::regName
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
Definition: isa.cc:81
gem5::ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition: misc.hh:614
gem5::ArmISA::ISA::inSecureState
bool inSecureState() const
Return true if the PE is in Secure state.
Definition: isa.cc:2043
gem5::ArmISA::vecPredRegClassOps
TypedRegClassOps< ArmISA::VecPredRegContainer > vecPredRegClassOps
Definition: isa.cc:89
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: misc.cc:718
gem5::Packet::isInvalidate
bool isInvalidate() const
Definition: packet.hh:606
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: misc.hh:602
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::BaseISADevice
Base class for devices that use the MiscReg interfaces.
Definition: isa_device.hh:61
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: misc.hh:762
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition: misc.hh:1104
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:671
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:520
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: misc.hh:79
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