#include <Sequencer.hh>

Inheritance diagram for gem5::ruby::Sequencer:

Public Types
typedef RubySequencerParams	Params

Public Types inherited from gem5::ruby::RubyPort
typedef RubyPortParams	Params

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject.

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
	Sequencer (const Params &)

	~Sequencer ()

void	writeCallbackScFail (Addr address, DataBlock &data)
	Proxy function to writeCallback that first invalidates the line address in the local monitor.

virtual void	wakeup ()

void	resetStats () override
	Callback to reset stats.

void	collateStats ()

void	writeCallback (Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0), const bool noCoales=false)

void	writeUniqueCallback (Addr address, DataBlock &data)

void	readCallback (Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))

void	atomicCallback (Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))

void	unaddressedCallback (Addr unaddressedReqId, RubyRequestType requestType, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))

void	completeHitCallback (std::vector< PacketPtr > &list)

void	invL1Callback ()

void	invL1 ()

RequestStatus	makeRequest (PacketPtr pkt) override

virtual bool	empty () const

int	outstandingCount () const override

bool	isDeadlockEventScheduled () const override

void	descheduleDeadlockEvent () override

virtual void	print (std::ostream &out) const

void	markRemoved ()

void	evictionCallback (Addr address)

int	coreId () const

virtual int	functionalWrite (Packet *func_pkt) override

void	recordRequestType (SequencerRequestType requestType)

statistics::Histogram &	getOutstandReqHist ()

statistics::Histogram &	getLatencyHist ()

statistics::Histogram &	getTypeLatencyHist (uint32_t t)

statistics::Histogram &	getHitLatencyHist ()

statistics::Histogram &	getHitTypeLatencyHist (uint32_t t)

statistics::Histogram &	getHitMachLatencyHist (uint32_t t)

statistics::Histogram &	getHitTypeMachLatencyHist (uint32_t r, uint32_t t)

statistics::Histogram &	getMissLatencyHist ()

statistics::Histogram &	getMissTypeLatencyHist (uint32_t t)

statistics::Histogram &	getMissMachLatencyHist (uint32_t t) const

statistics::Histogram &	getMissTypeMachLatencyHist (uint32_t r, uint32_t t) const

statistics::Histogram &	getIssueToInitialDelayHist (uint32_t t) const

statistics::Histogram &	getInitialToForwardDelayHist (const MachineType t) const

statistics::Histogram &	getForwardRequestToFirstResponseHist (const MachineType t) const

statistics::Histogram &	getFirstResponseToCompletionDelayHist (const MachineType t) const

statistics::Counter	getIncompleteTimes (const MachineType t) const

bool	llscCheckMonitor (const Addr)
	Searches for cache line address in the global monitor tagged with this Sequencer object's version id.

void	llscClearLocalMonitor ()
	Removes all addresses from the local monitor.

Public Member Functions inherited from gem5::ruby::RubyPort
	RubyPort (const Params &p)

virtual	~RubyPort ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected.

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index.

void	setController (AbstractController *_cntrl)

uint32_t	getId ()

DrainState	drain () override
	Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

bool	isCPUSequencer ()

Addr	getOffset (Addr addr) const

Addr	makeLineAddress (Addr addr) const

std::string	printAddress (Addr addr) const

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.

virtual void	regProbePoints ()
	Register probe points for this object.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

virtual void	startup ()
	startup() is the final initialization call before simulation.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters.

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (std::string_view name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick.

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge.

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Member Functions
void	issueRequest (PacketPtr pkt, RubyRequestType type)

virtual void	hitCallback (SequencerRequest *srequest, DataBlock &data, bool llscSuccess, const MachineType mach, const bool externalHit, const Cycles initialRequestTime, const Cycles forwardRequestTime, const Cycles firstResponseTime, const bool was_coalesced)

virtual bool	processReadCallback (SequencerRequest &seq_req, DataBlock &data, const bool rubyRequest, bool externalHit, const MachineType mach, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime)

void	recordMissLatency (SequencerRequest *srequest, bool llscSuccess, const MachineType respondingMach, bool isExternalHit, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime)

virtual RequestStatus	insertRequest (PacketPtr pkt, RubyRequestType primary_type, RubyRequestType secondary_type)

Protected Member Functions inherited from gem5::ruby::RubyPort
void	trySendRetries ()

void	ruby_hit_callback (PacketPtr pkt)

void	ruby_unaddressed_callback (PacketPtr pkt)

void	ruby_stale_translation_callback (Addr txnId)

void	testDrainComplete ()

void	ruby_eviction_callback (Addr address)

bool	recvTimingResp (PacketPtr pkt, PortID request_port_id)
	Called by the PIO port when receiving a timing response.

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain.

void	signalDrainDone () const
	Signal that an object is drained.

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters.

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance.

void	resetClock () const
	Reset the object's clock using the current global tick value.

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.

Protected Attributes
std::unordered_map< Addr, std::list< SequencerRequest > >	m_RequestTable

std::unordered_map< uint64_t, SequencerRequest >	m_UnaddressedRequestTable

Cycles	m_deadlock_threshold

RubySystem *	m_ruby_system

Protected Attributes inherited from gem5::ruby::RubyPort
RubySystem *	m_ruby_system

uint32_t	m_version

AbstractController *	m_controller

MessageBuffer *	m_mandatory_q_ptr

bool	m_usingRubyTester

System *	system

std::vector< MemResponsePort * >	response_ports

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Private Member Functions
	Sequencer (const Sequencer &obj)

Sequencer &	operator= (const Sequencer &obj)

void	llscLoadLinked (const Addr)
	Places the cache line address into the global monitor tagged with this Sequencer object's version id.

void	llscClearMonitor (const Addr)
	Removes the cache line address from the global monitor.

bool	llscStoreConditional (const Addr)
	Searches for cache line address in the global monitor tagged with this Sequencer object's version id.

void	incrementUnaddressedTransactionCnt ()
	Increment the unaddressed transaction counter.

uint64_t	getCurrentUnaddressedTransactionID () const
	Generate the current unaddressed transaction ID based on the counter and the Sequencer object's version id.

Private Attributes
int	m_max_outstanding_requests

int	m_num_pending_invs

PacketPtr	m_cache_inv_pkt

CacheMemory *	m_dataCache_ptr

Cycles	m_data_cache_hit_latency

Cycles	m_inst_cache_hit_latency

int	m_outstanding_count

bool	m_deadlock_check_scheduled

int	m_coreId

uint64_t	m_unaddressedTransactionCnt

bool	m_runningGarnetStandalone

statistics::Histogram	m_outstandReqHist
	Histogram for number of outstanding requests per cycle.

statistics::Histogram	m_latencyHist
	Histogram for holding latency profile of all requests.

std::vector< statistics::Histogram * >	m_typeLatencyHist

statistics::Histogram	m_hitLatencyHist
	Histogram for holding latency profile of all requests that hit in the controller connected to this sequencer.

std::vector< statistics::Histogram * >	m_hitTypeLatencyHist

std::vector< statistics::Histogram * >	m_hitMachLatencyHist
	Histograms for profiling the latencies for requests that did not required external messages.

std::vector< std::vector< statistics::Histogram * > >	m_hitTypeMachLatencyHist

statistics::Histogram	m_missLatencyHist
	Histogram for holding latency profile of all requests that miss in the controller connected to this sequencer.

std::vector< statistics::Histogram * >	m_missTypeLatencyHist

std::vector< statistics::Histogram * >	m_missMachLatencyHist
	Histograms for profiling the latencies for requests that required external messages.

std::vector< std::vector< statistics::Histogram * > >	m_missTypeMachLatencyHist

std::vector< statistics::Histogram * >	m_IssueToInitialDelayHist
	Histograms for recording the breakdown of miss latency.

std::vector< statistics::Histogram * >	m_InitialToForwardDelayHist

std::vector< statistics::Histogram * >	m_ForwardToFirstResponseDelayHist

std::vector< statistics::Histogram * >	m_FirstResponseToCompletionDelayHist

std::vector< statistics::Counter >	m_IncompleteTimes

EventFunctionWrapper	deadlockCheckEvent

Additional Inherited Members
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Detailed Description

Definition at line 85 of file Sequencer.hh.

Member Typedef Documentation

◆ Params

typedef RubySequencerParams gem5::ruby::Sequencer::Params

Definition at line 88 of file Sequencer.hh.

Constructor & Destructor Documentation

◆ Sequencer() [1/2]

gem5::ruby::Sequencer::Sequencer ( const Params & p )

Definition at line 70 of file Sequencer.cc.

References deadlockCheckEvent, m_IncompleteTimes, gem5::MipsISA::p, gem5::ruby::RubyPort::RubyPort(), and wakeup().

Referenced by gem5::ruby::HTMSequencer::HTMSequencer(), operator=(), Sequencer(), and gem5::ruby::VIPERSequencer::VIPERSequencer().

◆ ~Sequencer()

gem5::ruby::Sequencer::~Sequencer ( )

Definition at line 152 of file Sequencer.cc.

◆ Sequencer() [2/2]

gem5::ruby::Sequencer::Sequencer ( const Sequencer & obj )

private

References Sequencer().

Member Function Documentation

◆ atomicCallback()

void gem5::ruby::Sequencer::atomicCallback	(	Addr	address,
		DataBlock &	data,
		const bool	externalHit = false,
		const MachineType	mach = MachineType_NUM,
		const Cycles	initialRequestTime = Cycles(0),
		const Cycles	forwardRequestTime = Cycles(0),
		const Cycles	firstResponseTime = Cycles(0) )

Definition at line 640 of file Sequencer.cc.

References data, hitCallback(), issueRequest(), llscClearMonitor(), m_RequestTable, gem5::ruby::SequencerRequest::m_second_type, gem5::ruby::SequencerRequest::m_type, gem5::ruby::RubyPort::makeLineAddress(), markRemoved(), gem5::ruby::SequencerRequest::pkt, and recordMissLatency().

◆ collateStats()

void gem5::ruby::Sequencer::collateStats ( )

References data.

◆ completeHitCallback()

void gem5::ruby::Sequencer::completeHitCallback ( std::vector< PacketPtr > & list )

Definition at line 851 of file Sequencer.cc.

References gem5::ruby::RubyPort::MemResponsePort::hitCallback(), m_ruby_system, gem5::ArmISA::rs, gem5::safe_cast(), gem5::ArmISA::ss, gem5::ruby::RubyPort::testDrainComplete(), gem5::ruby::RubyPort::trySendRetries(), and gem5::MemCmd::WriteReq.

Referenced by invL1Callback().

◆ coreId()

int gem5::ruby::Sequencer::coreId ( ) const

inline

Definition at line 161 of file Sequencer.hh.

References m_coreId.

Referenced by issueRequest().

◆ descheduleDeadlockEvent()

void gem5::ruby::Sequencer::descheduleDeadlockEvent ( )

inlineoverridevirtual

Implements gem5::ruby::RubyPort.

Definition at line 154 of file Sequencer.hh.

References deadlockCheckEvent, and gem5::EventManager::deschedule().

◆ empty()

bool gem5::ruby::Sequencer::empty ( ) const

virtual

Reimplemented in gem5::ruby::HTMSequencer.

Definition at line 933 of file Sequencer.cc.

References m_RequestTable, and m_UnaddressedRequestTable.

Referenced by gem5::ruby::HTMSequencer::empty().

◆ evictionCallback()

void gem5::ruby::Sequencer::evictionCallback ( Addr address )

Definition at line 1200 of file Sequencer.cc.

References llscClearMonitor(), and gem5::ruby::RubyPort::ruby_eviction_callback().

◆ functionalWrite()

int gem5::ruby::Sequencer::functionalWrite ( Packet * func_pkt )

overridevirtual

Reimplemented from gem5::ruby::RubyPort.

Definition at line 264 of file Sequencer.cc.

References gem5::ruby::RubyPort::functionalWrite(), gem5::Packet::getAddr(), llscClearMonitor(), m_RequestTable, and gem5::ruby::RubyPort::makeLineAddress().

◆ getCurrentUnaddressedTransactionID()

uint64_t gem5::ruby::Sequencer::getCurrentUnaddressedTransactionID ( ) const

private

Generate the current unaddressed transaction ID based on the counter and the Sequencer object's version id.

Definition at line 1221 of file Sequencer.cc.

References m_ruby_system, m_unaddressedTransactionCnt, and gem5::ruby::RubyPort::m_version.

Referenced by insertRequest().

◆ getFirstResponseToCompletionDelayHist()

statistics::Histogram & gem5::ruby::Sequencer::getFirstResponseToCompletionDelayHist ( const MachineType t ) const

inline

Definition at line 206 of file Sequencer.hh.

References m_FirstResponseToCompletionDelayHist, and gem5::ArmISA::t.

◆ getForwardRequestToFirstResponseHist()

statistics::Histogram & gem5::ruby::Sequencer::getForwardRequestToFirstResponseHist ( const MachineType t ) const

inline

Definition at line 202 of file Sequencer.hh.

References m_ForwardToFirstResponseDelayHist, and gem5::ArmISA::t.

◆ getHitLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getHitLatencyHist ( )

inline

Definition at line 172 of file Sequencer.hh.

References m_hitLatencyHist.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getHitMachLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getHitMachLatencyHist ( uint32_t t )

inline

Definition at line 176 of file Sequencer.hh.

References m_hitMachLatencyHist, and gem5::ArmISA::t.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getHitTypeLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getHitTypeLatencyHist ( uint32_t t )

inline

Definition at line 173 of file Sequencer.hh.

References m_hitTypeLatencyHist, and gem5::ArmISA::t.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getHitTypeMachLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getHitTypeMachLatencyHist	(	uint32_t	r,
		uint32_t	t )

inline

Definition at line 179 of file Sequencer.hh.

References m_hitTypeMachLatencyHist, gem5::MipsISA::r, and gem5::ArmISA::t.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getIncompleteTimes()

statistics::Counter gem5::ruby::Sequencer::getIncompleteTimes ( const MachineType t ) const

inline

Definition at line 209 of file Sequencer.hh.

References m_IncompleteTimes, and gem5::ArmISA::t.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getInitialToForwardDelayHist()

statistics::Histogram & gem5::ruby::Sequencer::getInitialToForwardDelayHist ( const MachineType t ) const

inline

Definition at line 198 of file Sequencer.hh.

References m_InitialToForwardDelayHist, and gem5::ArmISA::t.

◆ getIssueToInitialDelayHist()

statistics::Histogram & gem5::ruby::Sequencer::getIssueToInitialDelayHist ( uint32_t t ) const

inline

Definition at line 194 of file Sequencer.hh.

References m_IssueToInitialDelayHist, and gem5::ArmISA::t.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getLatencyHist ( )

inline

Definition at line 168 of file Sequencer.hh.

References m_latencyHist.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getMissLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getMissLatencyHist ( )

inline

Definition at line 182 of file Sequencer.hh.

References m_missLatencyHist.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getMissMachLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getMissMachLatencyHist ( uint32_t t ) const

inline

Definition at line 187 of file Sequencer.hh.

References m_missMachLatencyHist, and gem5::ArmISA::t.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getMissTypeLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getMissTypeLatencyHist ( uint32_t t )

inline

Definition at line 184 of file Sequencer.hh.

References m_missTypeLatencyHist, and gem5::ArmISA::t.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getMissTypeMachLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getMissTypeMachLatencyHist	(	uint32_t	r,
		uint32_t	t ) const

inline

Definition at line 191 of file Sequencer.hh.

References m_missTypeMachLatencyHist, gem5::MipsISA::r, and gem5::ArmISA::t.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getOutstandReqHist()

statistics::Histogram & gem5::ruby::Sequencer::getOutstandReqHist ( )

inline

Definition at line 166 of file Sequencer.hh.

References m_outstandReqHist.

Referenced by gem5::ruby::Profiler::collateStats().

◆ getTypeLatencyHist()

statistics::Histogram & gem5::ruby::Sequencer::getTypeLatencyHist ( uint32_t t )

inline

Definition at line 169 of file Sequencer.hh.

References m_typeLatencyHist, and gem5::ArmISA::t.

Referenced by gem5::ruby::Profiler::collateStats().

◆ hitCallback()

void gem5::ruby::Sequencer::hitCallback	(	SequencerRequest *	srequest,
		DataBlock &	data,
		bool	llscSuccess,
		const MachineType	mach,
		const bool	externalHit,
		const Cycles	initialRequestTime,
		const Cycles	forwardRequestTime,
		const Cycles	firstResponseTime,
		const bool	was_coalesced )

protectedvirtual

Reimplemented in gem5::ruby::VIPERSequencer.

Definition at line 696 of file Sequencer.cc.

References gem5::Packet::cmdString(), data, DPRINTF, gem5::Packet::findNextSenderState(), gem5::Packet::getAddr(), gem5::Packet::getAtomicOp(), gem5::ruby::RubyPort::getOffset(), gem5::Packet::getSize(), gem5::Packet::isAtomicOp(), gem5::Packet::isFlush(), gem5::Packet::isMaskedWrite(), llscLoadLinked(), gem5::ruby::RubyPort::m_controller, m_ruby_system, gem5::ruby::SequencerRequest::m_type, gem5::ruby::RubyPort::m_usingRubyTester, gem5::ruby::RubyPort::makeLineAddress(), gem5::ruby::SubBlock::mergeFrom(), gem5::ruby::SequencerRequest::pkt, gem5::ruby::RubyPort::printAddress(), gem5::Packet::req, gem5::ArmISA::rs, gem5::ruby::RubyPort::ruby_hit_callback(), gem5::Packet::setData(), gem5::RubyTester::SenderState::subBlock, gem5::ruby::RubyPort::testDrainComplete(), warn_once, and gem5::Packet::writeData().

Referenced by atomicCallback(), gem5::ruby::VIPERSequencer::hitCallback(), readCallback(), and writeCallback().

◆ incrementUnaddressedTransactionCnt()

void gem5::ruby::Sequencer::incrementUnaddressedTransactionCnt ( )

private

Increment the unaddressed transaction counter.

Definition at line 1207 of file Sequencer.cc.

References m_ruby_system, and m_unaddressedTransactionCnt.

Referenced by insertRequest().

◆ insertRequest()

RequestStatus gem5::ruby::Sequencer::insertRequest	(	PacketPtr	pkt,
		RubyRequestType	primary_type,
		RubyRequestType	secondary_type )

protectedvirtual

◆ invL1()

void gem5::ruby::Sequencer::invL1 ( )

Definition at line 903 of file Sequencer.cc.

References gem5::X86ISA::addr, gem5::Clocked::clockEdge(), gem5::Clocked::cyclesToTicks(), DPRINTF, gem5::ArmISA::i, gem5::ruby::RubyPort::m_controller, m_dataCache_ptr, gem5::ruby::RubyPort::m_mandatory_q_ptr, m_num_pending_invs, and m_ruby_system.

Referenced by makeRequest().

◆ invL1Callback()

void gem5::ruby::Sequencer::invL1Callback ( )

Definition at line 888 of file Sequencer.cc.

References completeHitCallback(), m_cache_inv_pkt, and m_num_pending_invs.

◆ isDeadlockEventScheduled()

bool gem5::ruby::Sequencer::isDeadlockEventScheduled ( ) const

inlineoverridevirtual

Implements gem5::ruby::RubyPort.

Definition at line 151 of file Sequencer.hh.

References deadlockCheckEvent.

◆ issueRequest()

void gem5::ruby::Sequencer::issueRequest	(	PacketPtr	pkt,
		RubyRequestType	type )

protected

◆ llscCheckMonitor()

bool gem5::ruby::Sequencer::llscCheckMonitor ( const Addr address )

Searches for cache line address in the global monitor tagged with this Sequencer object's version id.

Returns: a boolean indicating if the line address was found.

Definition at line 207 of file Sequencer.cc.

References gem5::ruby::AbstractCacheEntry::isLocked(), m_dataCache_ptr, gem5::ruby::RubyPort::m_version, and gem5::ruby::RubyPort::makeLineAddress().

◆ llscClearLocalMonitor()

void gem5::ruby::Sequencer::llscClearLocalMonitor ( )

Removes all addresses from the local monitor.

This is independent of this Sequencer object's version id.

Definition at line 223 of file Sequencer.cc.

References m_dataCache_ptr, and gem5::ruby::RubyPort::m_version.

◆ llscClearMonitor()

void gem5::ruby::Sequencer::llscClearMonitor ( const Addr claddr )

private

Removes the cache line address from the global monitor.

This is independent of this Sequencer object's version id.

Definition at line 170 of file Sequencer.cc.

References gem5::ruby::AbstractCacheEntry::clearLocked(), DPRINTF, gem5::ruby::AbstractCacheEntry::isLocked(), m_dataCache_ptr, and gem5::ruby::RubyPort::m_version.

Referenced by atomicCallback(), evictionCallback(), functionalWrite(), writeCallback(), and writeCallbackScFail().

◆ llscLoadLinked()

void gem5::ruby::Sequencer::llscLoadLinked ( const Addr claddr )

private

Places the cache line address into the global monitor tagged with this Sequencer object's version id.

Definition at line 157 of file Sequencer.cc.

References DPRINTF, fatal_if, m_dataCache_ptr, gem5::ruby::RubyPort::m_version, gem5::Named::name(), and gem5::ruby::AbstractCacheEntry::setLocked().

Referenced by hitCallback().

◆ llscStoreConditional()

bool gem5::ruby::Sequencer::llscStoreConditional ( const Addr claddr )

private

Searches for cache line address in the global monitor tagged with this Sequencer object's version id.

If a match is found, the entry is is erased from the global monitor.

Returns: a boolean indicating if the line address was found.

Definition at line 184 of file Sequencer.cc.

References gem5::ruby::AbstractCacheEntry::clearLocked(), DPRINTF, fatal_if, gem5::ruby::AbstractCacheEntry::isLocked(), m_dataCache_ptr, gem5::ruby::RubyPort::m_version, and gem5::Named::name().

Referenced by writeCallback().

◆ makeRequest()

RequestStatus gem5::ruby::Sequencer::makeRequest ( PacketPtr pkt )

overridevirtual

◆ markRemoved()

void gem5::ruby::Sequencer::markRemoved ( )

Definition at line 385 of file Sequencer.cc.

References m_outstanding_count.

Referenced by atomicCallback(), gem5::ruby::HTMSequencer::htmCallback(), readCallback(), and writeCallback().

◆ operator=()

Sequencer & gem5::ruby::Sequencer::operator= ( const Sequencer & obj )

private

References Sequencer().

◆ outstandingCount()

int gem5::ruby::Sequencer::outstandingCount ( ) const

inlineoverridevirtual

Implements gem5::ruby::RubyPort.

Definition at line 149 of file Sequencer.hh.

References m_outstanding_count.

◆ print()

void gem5::ruby::Sequencer::print ( std::ostream & out ) const

virtual

Reimplemented in gem5::ruby::HTMSequencer.

Definition at line 1185 of file Sequencer.cc.

References m_outstanding_count, m_RequestTable, and gem5::ruby::RubyPort::m_version.

Referenced by gem5::ruby::operator<<(), and gem5::ruby::HTMSequencer::print().

◆ processReadCallback()

bool gem5::ruby::Sequencer::processReadCallback	(	SequencerRequest &	seq_req,
		DataBlock &	data,
		const bool	rubyRequest,
		bool	externalHit,
		const MachineType	mach,
		Cycles	initialRequestTime,
		Cycles	forwardRequestTime,
		Cycles	firstResponseTime )

protectedvirtual

Reimplemented in gem5::ruby::VIPERSequencer.

Definition at line 568 of file Sequencer.cc.

References data, issueRequest(), gem5::ruby::SequencerRequest::m_second_type, gem5::ruby::SequencerRequest::m_type, and gem5::ruby::SequencerRequest::pkt.

Referenced by gem5::ruby::VIPERSequencer::processReadCallback(), and readCallback().

◆ readCallback()

void gem5::ruby::Sequencer::readCallback	(	Addr	address,
		DataBlock &	data,
		const bool	externalHit = false,
		const MachineType	mach = MachineType_NUM,
		const Cycles	initialRequestTime = Cycles(0),
		const Cycles	forwardRequestTime = Cycles(0),
		const Cycles	firstResponseTime = Cycles(0) )

Definition at line 595 of file Sequencer.cc.

References data, hitCallback(), m_RequestTable, gem5::ruby::RubyPort::makeLineAddress(), markRemoved(), processReadCallback(), and recordMissLatency().

◆ recordMissLatency()

void gem5::ruby::Sequencer::recordMissLatency	(	SequencerRequest *	srequest,
		bool	llscSuccess,
		const MachineType	respondingMach,
		bool	isExternalHit,
		Cycles	initialRequestTime,
		Cycles	forwardRequestTime,
		Cycles	firstResponseTime )

protected

◆ recordRequestType()

void gem5::ruby::Sequencer::recordRequestType ( SequencerRequestType requestType )

Definition at line 1194 of file Sequencer.cc.

References DPRINTF.

◆ resetStats()

void gem5::ruby::Sequencer::resetStats ( )

overridevirtual

Callback to reset stats.

Reimplemented from gem5::statistics::Group.

Definition at line 281 of file Sequencer.cc.

References gem5::ArmISA::i, m_FirstResponseToCompletionDelayHist, m_ForwardToFirstResponseDelayHist, m_hitLatencyHist, m_hitMachLatencyHist, m_hitTypeLatencyHist, m_hitTypeMachLatencyHist, m_IncompleteTimes, m_InitialToForwardDelayHist, m_IssueToInitialDelayHist, m_latencyHist, m_missLatencyHist, m_missMachLatencyHist, m_missTypeLatencyHist, m_missTypeMachLatencyHist, m_outstandReqHist, and m_typeLatencyHist.

◆ unaddressedCallback()

void gem5::ruby::Sequencer::unaddressedCallback	(	Addr	unaddressedReqId,
		RubyRequestType	requestType,
		const MachineType	mach = MachineType_NUM,
		const Cycles	initialRequestTime = Cycles(0),
		const Cycles	forwardRequestTime = Cycles(0),
		const Cycles	firstResponseTime = Cycles(0) )

Definition at line 801 of file Sequencer.cc.

References DPRINTF, gem5::ruby::SequencerRequest::m_type, m_UnaddressedRequestTable, panic, gem5::ruby::SequencerRequest::pkt, gem5::ruby::RubyPort::ruby_stale_translation_callback(), gem5::ruby::RubyPort::ruby_unaddressed_callback(), and gem5::ruby::RubyPort::testDrainComplete().

◆ wakeup()

void gem5::ruby::Sequencer::wakeup ( )

virtual

Reimplemented in gem5::ruby::HTMSequencer.

Definition at line 229 of file Sequencer.cc.

References gem5::Clocked::clockEdge(), gem5::Clocked::clockPeriod(), gem5::Clocked::curCycle(), deadlockCheckEvent, gem5::Draining, gem5::Drainable::drainState(), m_deadlock_threshold, m_outstanding_count, m_RequestTable, gem5::ruby::RubyPort::m_version, panic, and gem5::EventManager::schedule().

Referenced by Sequencer(), and gem5::ruby::HTMSequencer::wakeup().

◆ writeCallback()

void gem5::ruby::Sequencer::writeCallback	(	Addr	address,
		DataBlock &	data,
		const bool	externalHit = false,
		const MachineType	mach = MachineType_NUM,
		const Cycles	initialRequestTime = Cycles(0),
		const Cycles	forwardRequestTime = Cycles(0),
		const Cycles	firstResponseTime = Cycles(0),
		const bool	noCoales = false )

Definition at line 464 of file Sequencer.cc.

References data, hitCallback(), issueRequest(), llscClearMonitor(), llscStoreConditional(), gem5::ruby::RubyPort::m_controller, gem5::ruby::RubyPort::m_mandatory_q_ptr, m_RequestTable, gem5::ruby::SequencerRequest::m_second_type, gem5::ruby::SequencerRequest::m_type, gem5::ruby::RubyPort::makeLineAddress(), markRemoved(), gem5::ruby::SequencerRequest::pkt, recordMissLatency(), and gem5::Packet::req.

Referenced by writeCallbackScFail(), and writeUniqueCallback().

◆ writeCallbackScFail()

void gem5::ruby::Sequencer::writeCallbackScFail	(	Addr	address,
		DataBlock &	data )

Proxy function to writeCallback that first invalidates the line address in the local monitor.

Definition at line 457 of file Sequencer.cc.

References data, llscClearMonitor(), and writeCallback().

◆ writeUniqueCallback()

void gem5::ruby::Sequencer::writeUniqueCallback	(	Addr	address,
		DataBlock &	data )

inline

Definition at line 114 of file Sequencer.hh.

References data, and writeCallback().

Member Data Documentation

◆ deadlockCheckEvent

EventFunctionWrapper gem5::ruby::Sequencer::deadlockCheckEvent

private

Definition at line 318 of file Sequencer.hh.

Referenced by descheduleDeadlockEvent(), insertRequest(), isDeadlockEventScheduled(), Sequencer(), and wakeup().

◆ m_cache_inv_pkt

PacketPtr gem5::ruby::Sequencer::m_cache_inv_pkt

private

Definition at line 262 of file Sequencer.hh.

Referenced by invL1Callback(), and makeRequest().

◆ m_coreId

int gem5::ruby::Sequencer::m_coreId

private

Definition at line 277 of file Sequencer.hh.

Referenced by coreId().

◆ m_data_cache_hit_latency

Cycles gem5::ruby::Sequencer::m_data_cache_hit_latency

private

Definition at line 270 of file Sequencer.hh.

◆ m_dataCache_ptr

CacheMemory* gem5::ruby::Sequencer::m_dataCache_ptr

private

Definition at line 264 of file Sequencer.hh.

Referenced by invL1(), llscCheckMonitor(), llscClearLocalMonitor(), llscClearMonitor(), llscLoadLinked(), and llscStoreConditional().

◆ m_deadlock_check_scheduled

bool gem5::ruby::Sequencer::m_deadlock_check_scheduled

private

Definition at line 275 of file Sequencer.hh.

◆ m_deadlock_threshold

Cycles gem5::ruby::Sequencer::m_deadlock_threshold

protected

Definition at line 249 of file Sequencer.hh.

Referenced by insertRequest(), gem5::ruby::HTMSequencer::wakeup(), and wakeup().

◆ m_FirstResponseToCompletionDelayHist

std::vector<statistics::Histogram *> gem5::ruby::Sequencer::m_FirstResponseToCompletionDelayHist

private

Definition at line 315 of file Sequencer.hh.

Referenced by getFirstResponseToCompletionDelayHist(), recordMissLatency(), and resetStats().

◆ m_ForwardToFirstResponseDelayHist

std::vector<statistics::Histogram *> gem5::ruby::Sequencer::m_ForwardToFirstResponseDelayHist

private

Definition at line 314 of file Sequencer.hh.

Referenced by getForwardRequestToFirstResponseHist(), recordMissLatency(), and resetStats().

◆ m_hitLatencyHist

statistics::Histogram gem5::ruby::Sequencer::m_hitLatencyHist

private

Histogram for holding latency profile of all requests that hit in the controller connected to this sequencer.

Definition at line 292 of file Sequencer.hh.

Referenced by getHitLatencyHist(), recordMissLatency(), and resetStats().

◆ m_hitMachLatencyHist

std::vector<statistics::Histogram *> gem5::ruby::Sequencer::m_hitMachLatencyHist

private

Histograms for profiling the latencies for requests that did not required external messages.

Definition at line 297 of file Sequencer.hh.

Referenced by getHitMachLatencyHist(), recordMissLatency(), and resetStats().

◆ m_hitTypeLatencyHist

std::vector<statistics::Histogram *> gem5::ruby::Sequencer::m_hitTypeLatencyHist

private

Definition at line 293 of file Sequencer.hh.

Referenced by getHitTypeLatencyHist(), recordMissLatency(), and resetStats().

◆ m_hitTypeMachLatencyHist

std::vector<std::vector<statistics::Histogram *> > gem5::ruby::Sequencer::m_hitTypeMachLatencyHist

private

Definition at line 298 of file Sequencer.hh.

Referenced by getHitTypeMachLatencyHist(), recordMissLatency(), and resetStats().

◆ m_IncompleteTimes

std::vector<statistics::Counter> gem5::ruby::Sequencer::m_IncompleteTimes

private

Definition at line 316 of file Sequencer.hh.

Referenced by getIncompleteTimes(), recordMissLatency(), resetStats(), and Sequencer().

◆ m_InitialToForwardDelayHist

std::vector<statistics::Histogram *> gem5::ruby::Sequencer::m_InitialToForwardDelayHist

private

Definition at line 313 of file Sequencer.hh.

Referenced by getInitialToForwardDelayHist(), recordMissLatency(), and resetStats().

◆ m_inst_cache_hit_latency

Cycles gem5::ruby::Sequencer::m_inst_cache_hit_latency

private

Definition at line 271 of file Sequencer.hh.

◆ m_IssueToInitialDelayHist

std::vector<statistics::Histogram *> gem5::ruby::Sequencer::m_IssueToInitialDelayHist

private

Histograms for recording the breakdown of miss latency.

Definition at line 312 of file Sequencer.hh.

Referenced by getIssueToInitialDelayHist(), recordMissLatency(), and resetStats().

◆ m_latencyHist

statistics::Histogram gem5::ruby::Sequencer::m_latencyHist

private

Histogram for holding latency profile of all requests.

Definition at line 287 of file Sequencer.hh.

Referenced by getLatencyHist(), recordMissLatency(), and resetStats().

◆ m_max_outstanding_requests

int gem5::ruby::Sequencer::m_max_outstanding_requests

private

Definition at line 258 of file Sequencer.hh.

Referenced by makeRequest().

◆ m_missLatencyHist

statistics::Histogram gem5::ruby::Sequencer::m_missLatencyHist

private

Histogram for holding latency profile of all requests that miss in the controller connected to this sequencer.

Definition at line 302 of file Sequencer.hh.

Referenced by getMissLatencyHist(), recordMissLatency(), and resetStats().

◆ m_missMachLatencyHist

std::vector<statistics::Histogram *> gem5::ruby::Sequencer::m_missMachLatencyHist

private

Histograms for profiling the latencies for requests that required external messages.

Definition at line 307 of file Sequencer.hh.

Referenced by getMissMachLatencyHist(), recordMissLatency(), and resetStats().

◆ m_missTypeLatencyHist

std::vector<statistics::Histogram *> gem5::ruby::Sequencer::m_missTypeLatencyHist

private

Definition at line 303 of file Sequencer.hh.

Referenced by getMissTypeLatencyHist(), recordMissLatency(), and resetStats().

◆ m_missTypeMachLatencyHist

std::vector<std::vector<statistics::Histogram *> > gem5::ruby::Sequencer::m_missTypeMachLatencyHist

private

Definition at line 309 of file Sequencer.hh.

Referenced by getMissTypeMachLatencyHist(), recordMissLatency(), and resetStats().

◆ m_num_pending_invs

int gem5::ruby::Sequencer::m_num_pending_invs

private

Definition at line 260 of file Sequencer.hh.

Referenced by invL1(), and invL1Callback().

◆ m_outstanding_count

int gem5::ruby::Sequencer::m_outstanding_count

private

Definition at line 274 of file Sequencer.hh.

Referenced by insertRequest(), makeRequest(), markRemoved(), outstandingCount(), print(), and wakeup().

◆ m_outstandReqHist

statistics::Histogram gem5::ruby::Sequencer::m_outstandReqHist

private

Histogram for number of outstanding requests per cycle.

Definition at line 284 of file Sequencer.hh.

Referenced by getOutstandReqHist(), insertRequest(), and resetStats().

◆ m_RequestTable

std::unordered_map<Addr, std::list<SequencerRequest> > gem5::ruby::Sequencer::m_RequestTable

protected

Definition at line 244 of file Sequencer.hh.

Referenced by atomicCallback(), empty(), functionalWrite(), gem5::ruby::HTMSequencer::htmCallback(), insertRequest(), print(), readCallback(), wakeup(), and writeCallback().

◆ m_ruby_system

RubySystem* gem5::ruby::Sequencer::m_ruby_system

protected

Definition at line 255 of file Sequencer.hh.

Referenced by completeHitCallback(), getCurrentUnaddressedTransactionID(), hitCallback(), gem5::ruby::VIPERSequencer::hitCallback(), incrementUnaddressedTransactionCnt(), invL1(), issueRequest(), and makeRequest().

◆ m_runningGarnetStandalone

bool gem5::ruby::Sequencer::m_runningGarnetStandalone

private

Definition at line 281 of file Sequencer.hh.

◆ m_typeLatencyHist

std::vector<statistics::Histogram *> gem5::ruby::Sequencer::m_typeLatencyHist

private

Definition at line 288 of file Sequencer.hh.

Referenced by getTypeLatencyHist(), recordMissLatency(), and resetStats().

◆ m_UnaddressedRequestTable

std::unordered_map<uint64_t, SequencerRequest> gem5::ruby::Sequencer::m_UnaddressedRequestTable

protected

Definition at line 247 of file Sequencer.hh.

Referenced by empty(), insertRequest(), and unaddressedCallback().

◆ m_unaddressedTransactionCnt

uint64_t gem5::ruby::Sequencer::m_unaddressedTransactionCnt

private

Definition at line 279 of file Sequencer.hh.

Referenced by getCurrentUnaddressedTransactionID(), and incrementUnaddressedTransactionCnt().

The documentation for this class was generated from the following files:

mem/ruby/system/Sequencer.hh
mem/ruby/system/Sequencer.cc

Public Types

Public Member Functions

Protected Member Functions

Protected Attributes

Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ Params

Constructor & Destructor Documentation

◆ Sequencer() [1/2]

◆ ~Sequencer()

◆ Sequencer() [2/2]

Member Function Documentation

◆ atomicCallback()

◆ collateStats()

◆ completeHitCallback()

◆ coreId()

◆ descheduleDeadlockEvent()

◆ empty()

◆ evictionCallback()

◆ functionalWrite()

◆ getCurrentUnaddressedTransactionID()

◆ getFirstResponseToCompletionDelayHist()

◆ getForwardRequestToFirstResponseHist()

◆ getHitLatencyHist()

◆ getHitMachLatencyHist()

◆ getHitTypeLatencyHist()

◆ getHitTypeMachLatencyHist()

◆ getIncompleteTimes()

◆ getInitialToForwardDelayHist()

◆ getIssueToInitialDelayHist()

◆ getLatencyHist()

◆ getMissLatencyHist()

◆ getMissMachLatencyHist()

◆ getMissTypeLatencyHist()

◆ getMissTypeMachLatencyHist()

◆ getOutstandReqHist()

◆ getTypeLatencyHist()

◆ hitCallback()

◆ incrementUnaddressedTransactionCnt()

◆ insertRequest()

◆ invL1()

◆ invL1Callback()

◆ isDeadlockEventScheduled()

◆ issueRequest()

◆ llscCheckMonitor()

◆ llscClearLocalMonitor()

◆ llscClearMonitor()

◆ llscLoadLinked()

◆ llscStoreConditional()

◆ makeRequest()

◆ markRemoved()

◆ operator=()

◆ outstandingCount()

◆ print()

◆ processReadCallback()

◆ readCallback()

◆ recordMissLatency()

◆ recordRequestType()

◆ resetStats()

◆ unaddressedCallback()

◆ wakeup()

◆ writeCallback()

◆ writeCallbackScFail()

◆ writeUniqueCallback()

Member Data Documentation

◆ deadlockCheckEvent

◆ m_cache_inv_pkt

◆ m_coreId

◆ m_data_cache_hit_latency

◆ m_dataCache_ptr

◆ m_deadlock_check_scheduled

◆ m_deadlock_threshold

◆ m_FirstResponseToCompletionDelayHist

◆ m_ForwardToFirstResponseDelayHist

◆ m_hitLatencyHist

◆ m_hitMachLatencyHist

◆ m_hitTypeLatencyHist