gem5 [DEVELOP-FOR-25.0]
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thread_context.cc
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1/*
2 * Copyright (c) 2010-2012, 2016-2017, 2019 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
43
44#include "debug/O3CPU.hh"
45
46namespace gem5
47{
48
49namespace o3
50{
51
52void
54{
55 gem5::takeOverFrom(*this, *old_context);
56
57 getIsaPtr()->takeOverFrom(this, old_context);
58
59 InstDecoder *newDecoder = getDecoderPtr();
60 InstDecoder *oldDecoder = old_context->getDecoderPtr();
61 newDecoder->takeOverFrom(oldDecoder);
62
63 thread->noSquashFromTC = false;
64 thread->trapPending = false;
65}
66
67void
69{
70 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
71 threadId());
72
73 if (thread->status() == gem5::ThreadContext::Active)
74 return;
75
76 thread->lastActivate = curTick();
78
79 // status() == Suspended
80 cpu->activateContext(thread->threadId());
81}
82
83void
85{
86 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
87 threadId());
88
90 return;
91
92 if (cpu->isDraining()) {
93 DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
94 return;
95 }
96
97 thread->lastActivate = curTick();
98 thread->lastSuspend = curTick();
99
101 cpu->suspendContext(thread->threadId());
102}
103
104void
106{
107 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
108
109 if (thread->status() == gem5::ThreadContext::Halting ||
111 return;
112
113 // the thread is not going to halt/terminate immediately in this cycle.
114 // The thread will be removed after an exit trap is processed
115 // (e.g., after trapLatency cycles). Until then, the thread's status
116 // will be Halting.
118
119 // add this thread to the exiting list to mark that it is trying to exit.
120 cpu->addThreadToExitingList(thread->threadId());
121}
122
123Tick
125{
126 return thread->lastActivate;
127}
128
129Tick
131{
132 return thread->lastSuspend;
133}
134
135void
137{
138 // Prevent squashing
139 thread->noSquashFromTC = true;
140 getIsaPtr()->copyRegsFrom(tc);
141 thread->noSquashFromTC = false;
142}
143
144void
146{
147 cpu->isa[thread->threadId()]->clear();
148}
149
150RegVal
152{
153 return cpu->getArchReg(reg, thread->threadId());
154}
155
156void *
158{
159 return cpu->getWritableArchReg(reg, thread->threadId());
160}
161
162void
163ThreadContext::getReg(const RegId &reg, void *val) const
164{
165 cpu->getArchReg(reg, val, thread->threadId());
166}
167
168void
170{
171 cpu->setArchReg(reg, val, thread->threadId());
173}
174
175void
176ThreadContext::setReg(const RegId &reg, const void *val)
177{
178 cpu->setArchReg(reg, val, thread->threadId());
180}
181
182void
184{
185 cpu->pcState(val, thread->threadId());
186
188}
189
190void
192{
193 cpu->pcState(val, thread->threadId());
194
196}
197
198void
200{
201 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
202
204}
205
206void
208{
209 cpu->setMiscReg(misc_reg, val, thread->threadId());
210
212}
213
214// hardware transactional memory
215void
218{
219 cpu->htmSendAbortSignal(thread->threadId(), htmUid, cause);
220
222}
223
226{
227 return thread->htmCheckpoint;
228}
229
230void
232{
233 thread->htmCheckpoint = std::move(new_cpt);
234}
235
236} // namespace o3
237} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:209
virtual void copyRegsFrom(ThreadContext *src)=0
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition isa.hh:84
virtual void takeOverFrom(InstDecoder *old)
Take over the state from an old decoder when switching CPUs.
Definition decoder.hh:89
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
ThreadContext is the external interface to all thread state for anything outside of the CPU.
@ Halted
Permanently shut down.
@ Halting
Trying to exit and waiting for an event to completely exit.
@ Suspended
Temporarily inactive.
virtual InstDecoder * getDecoderPtr()=0
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
void conditionalSquash()
check if the cpu is currently in state update mode and squash if not.
ThreadState * thread
Pointer to the thread state that this TC corrseponds to.
void pcStateNoRecord(const PCStateBase &val) override
void clearArchRegs() override
Resets all architectural registers to 0.
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
void * getWritableReg(const RegId &reg) override
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
void activate() override
Set the status to Active.
void suspend() override
Set the status to Suspended.
int threadId() const override
Returns this thread's ID number.
void halt() override
Set the status to Halted.
void takeOverFrom(gem5::ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
const PCStateBase & pcState() const override
Reads this thread's PC state.
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
CPU * cpu
Pointer to the CPU.
void setReg(const RegId &reg, RegVal val) override
RegVal getReg(const RegId &reg) const override
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
BaseISA * getIsaPtr() const override
InstDecoder * getDecoderPtr() override
void copyArchRegs(gem5::ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
Bitfield< 5, 3 > reg
Definition types.hh:92
Bitfield< 63 > val
Definition misc.hh:804
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
uint16_t RegIndex
Definition types.hh:176
uint64_t RegVal
Definition types.hh:173
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
uint64_t Tick
Tick count type.
Definition types.hh:58
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition htm.hh:127
HtmFailureFaultCause
Definition htm.hh:48

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