Derived ThreadContext class for use with the O3CPU. More...

#include <thread_context.hh>

Inheritance diagram for gem5::o3::ThreadContext:

Public Member Functions
bool	schedule (PCEvent *e) override

bool	remove (PCEvent *e) override

void	scheduleInstCountEvent (Event *event, Tick count) override

void	descheduleInstCountEvent (Event *event) override

Tick	getCurrentInstCount () override

BaseMMU *	getMMUPtr () override
	Returns a pointer to the MMU.

CheckerCPU *	getCheckerCpuPtr () override

BaseISA *	getIsaPtr () const override

InstDecoder *	getDecoderPtr () override

BaseCPU *	getCpuPtr () override
	Returns a pointer to this CPU.

int	cpuId () const override
	Reads this CPU's ID.

uint32_t	socketId () const override
	Reads this CPU's Socket ID.

ContextID	contextId () const override

void	setContextId (ContextID id) override

int	threadId () const override
	Returns this thread's ID number.

void	setThreadId (int id) override

System *	getSystemPtr () override
	Returns a pointer to the system.

Process *	getProcessPtr () override
	Returns a pointer to this thread's process.

void	setProcessPtr (Process *p) override

Status	status () const override
	Returns this thread's status.

void	setStatus (Status new_status) override
	Sets this thread's status.

void	activate () override
	Set the status to Active.

void	suspend () override
	Set the status to Suspended.

void	halt () override
	Set the status to Halted.

void	takeOverFrom (gem5::ThreadContext *old_context) override
	Takes over execution of a thread from another CPU.

Tick	readLastActivate () override
	Reads the last tick that this thread was activated on.

Tick	readLastSuspend () override
	Reads the last tick that this thread was suspended on.

void	copyArchRegs (gem5::ThreadContext *tc) override
	Copies the architectural registers from another TC into this TC.

void	clearArchRegs () override
	Resets all architectural registers to 0.

const PCStateBase &	pcState () const override
	Reads this thread's PC state.

void	pcState (const PCStateBase &val) override
	Sets this thread's PC state.

void	pcStateNoRecord (const PCStateBase &val) override

RegVal	readMiscRegNoEffect (RegIndex misc_reg) const override
	Reads a miscellaneous register.

RegVal	readMiscReg (RegIndex misc_reg) override
	Reads a misc.

void	setMiscRegNoEffect (RegIndex misc_reg, RegVal val) override
	Sets a misc.

void	setMiscReg (RegIndex misc_reg, RegVal val) override
	Sets a misc.

unsigned	readStCondFailures () const override
	Returns the number of consecutive store conditional failures.

void	setStCondFailures (unsigned sc_failures) override
	Sets the number of consecutive store conditional failures.

void	conditionalSquash ()
	check if the cpu is currently in state update mode and squash if not.

RegVal	getReg (const RegId &reg) const override

void	getReg (const RegId &reg, void *val) const override

void *	getWritableReg (const RegId &reg) override

void	setReg (const RegId &reg, RegVal val) override

void	setReg (const RegId &reg, const void *val) override

void	htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override

BaseHTMCheckpointPtr &	getHtmCheckpointPtr () override

void	setHtmCheckpointPtr (BaseHTMCheckpointPtr new_cpt) override

Public Member Functions inherited from gem5::ThreadContext
bool	getUseForClone ()

void	setUseForClone (bool new_val)

virtual	~ThreadContext ()

virtual void	sendFunctional (PacketPtr pkt)

void	quiesce ()
	Quiesce thread context.

void	quiesceTick (Tick resume)
	Quiesce, suspend, and schedule activate at resume.

virtual void	regStats (const std::string &name)

void	pcState (Addr addr)

virtual int	exit ()

Public Attributes
CPU *	cpu
	Pointer to the CPU.

ThreadState *	thread
	Pointer to the thread state that this TC corrseponds to.

Public Attributes inherited from gem5::ThreadContext
int	intResult = DefaultIntResult

double	floatResult = DefaultFloatResult

int	intOffset = 0

Additional Inherited Members
Public Types inherited from gem5::ThreadContext
enum	Status { Active , Suspended , Halting , Halted }

Static Public Member Functions inherited from gem5::ThreadContext
static void	compare (ThreadContext one, ThreadContext two)
	function to compare two thread contexts (for debugging)

Static Public Attributes inherited from gem5::ThreadContext
static const int	ints []

static const double	floats []

static const int	DefaultIntResult = 0

static const double	DefaultFloatResult = 0.0

Protected Attributes inherited from gem5::ThreadContext
bool	useForClone = false

Detailed Description

Derived ThreadContext class for use with the O3CPU.

It provides the interface for any external objects to access a single thread's state and some general CPU state. Any time external objects try to update state through this interface, the CPU will create an event to squash all in-flight instructions in order to ensure state is maintained correctly. It must be defined specifically for the O3CPU because not all architectural state is located within the ThreadState (such as the commit PC, and registers), and specific actions must be taken when using this interface (such as squashing all in-flight instructions when doing a write to this interface).

Definition at line 67 of file thread_context.hh.

Member Function Documentation

◆ activate()

void gem5::o3::ThreadContext::activate ( )

overridevirtual

Set the status to Active.

Public Member Functions

Public Attributes

Additional Inherited Members

Detailed Description

Member Function Documentation

◆ activate()

◆ clearArchRegs()

◆ conditionalSquash()

◆ contextId()

◆ copyArchRegs()

◆ cpuId()

◆ descheduleInstCountEvent()

◆ getCheckerCpuPtr()

◆ getCpuPtr()

◆ getCurrentInstCount()

◆ getDecoderPtr()

◆ getHtmCheckpointPtr()

◆ getIsaPtr()

◆ getMMUPtr()

◆ getProcessPtr()

◆ getReg() [1/2]

◆ getReg() [2/2]

◆ getSystemPtr()

◆ getWritableReg()

◆ halt()

◆ htmAbortTransaction()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ pcStateNoRecord()

◆ readLastActivate()

◆ readLastSuspend()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ readStCondFailures()

◆ remove()

◆ schedule()

◆ scheduleInstCountEvent()

◆ setContextId()

◆ setHtmCheckpointPtr()

◆ setMiscReg()

◆ setMiscRegNoEffect()

◆ setProcessPtr()

◆ setReg() [1/2]

◆ setReg() [2/2]

◆ setStatus()

◆ setStCondFailures()

◆ setThreadId()

◆ socketId()

◆ status()

◆ suspend()

◆ takeOverFrom()

◆ threadId()

Member Data Documentation

◆ cpu

◆ thread