42#ifndef __CPU_O3_THREAD_CONTEXT_HH__
43#define __CPU_O3_THREAD_CONTEXT_HH__
76 return thread->pcEventQueue.schedule(
e);
81 return thread->pcEventQueue.remove(
e);
97 return thread->comInstEventQueue.getCurTick();
117 return cpu->fetch.decoder[
thread->threadId()];
124 int cpuId()
const override {
return cpu->cpuId(); }
152 thread->setStatus(new_status);
162 void halt()
override;
217 return thread->storeCondFailures;
224 thread->storeCondFailures = sc_failures;
Register ID: describe an architectural register with its class and index.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Derived ThreadContext class for use with the O3CPU.
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
void conditionalSquash()
check if the cpu is currently in state update mode and squash if not.
BaseCPU * getCpuPtr() override
Returns a pointer to this CPU.
ThreadState * thread
Pointer to the thread state that this TC corrseponds to.
void pcStateNoRecord(const PCStateBase &val) override
bool remove(PCEvent *e) override
void clearArchRegs() override
Resets all architectural registers to 0.
uint32_t socketId() const override
Reads this CPU's Socket ID.
void setThreadId(int id) override
void setContextId(ContextID id) override
BaseMMU * getMMUPtr() override
Returns a pointer to the MMU.
void setProcessPtr(Process *p) override
Status status() const override
Returns this thread's status.
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
void scheduleInstCountEvent(Event *event, Tick count) override
void * getWritableReg(const RegId ®) override
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
int cpuId() const override
Reads this CPU's ID.
void activate() override
Set the status to Active.
void suspend() override
Set the status to Suspended.
int threadId() const override
Returns this thread's ID number.
void halt() override
Set the status to Halted.
void setStCondFailures(unsigned sc_failures) override
Sets the number of consecutive store conditional failures.
void takeOverFrom(gem5::ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
Tick getCurrentInstCount() override
void setStatus(Status new_status) override
Sets this thread's status.
const PCStateBase & pcState() const override
Reads this thread's PC state.
unsigned readStCondFailures() const override
Returns the number of consecutive store conditional failures.
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
CPU * cpu
Pointer to the CPU.
void descheduleInstCountEvent(Event *event) override
void setReg(const RegId ®, RegVal val) override
RegVal getReg(const RegId ®) const override
CheckerCPU * getCheckerCpuPtr() override
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Process * getProcessPtr() override
Returns a pointer to this thread's process.
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
BaseISA * getIsaPtr() const override
System * getSystemPtr() override
Returns a pointer to the system.
bool schedule(PCEvent *e) override
RegVal readMiscReg(RegIndex misc_reg) override
Reads a misc.
InstDecoder * getDecoderPtr() override
void copyArchRegs(gem5::ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Reads a miscellaneous register.
ContextID contextId() const override
Class that has various thread state, such as the status, the current instruction being processed,...
Copyright (c) 2024 Arm Limited All rights reserved.
uint64_t Tick
Tick count type.
int ContextID
Globally unique thread context ID.
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr