ftq.hh

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 * Copyright (c) 2025 Arm Limited
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 *
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
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#ifndef __CPU_O3_FTQ_HH__
#define __CPU_O3_FTQ_HH__
 
#include <list>
#include <string>
 
#include "arch/generic/pcstate.hh"
#include "base/statistics.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/limits.hh"
#include "cpu/pred/bpred_unit.hh"
#include "sim/probe/probe.hh"
 
namespace gem5
{
 
struct BaseO3CPUParams;
 
namespace o3
{
 
class CPU;
 
struct DerivO3CPUParams;
 
// Fetch target sequence type. Basically the same as the instruction sequence
// number but since the fetch target is generated before instructions.
typedef InstSeqNum FTSeqNum;

class FetchTarget
{
  public:
    FetchTarget(const ThreadID _tid, const PCStateBase &_start_pc,
                FTSeqNum _seqNum);
 
  private:
    std::unique_ptr<PCStateBase> startPC;

    std::unique_ptr<PCStateBase> endPC;

    std::unique_ptr<PCStateBase> predPC;
 
    /* Fetch targets sequence number */
    const FTSeqNum ftSeqNum;

    const ThreadID tid;

    bool is_branch;

    bool taken;
 
  public:
    branch_prediction::BPredUnit::PredictorHistory *bpuHistory;
 
    /* Start address of the basic block */
    Addr
    startAddress()
    {
        return startPC->instAddr();
    }
 
    /* End address of the basic block */
    Addr
    endAddress()
    {
        return (endPC) ? endPC->instAddr() : MaxAddr;
    }
 
    /* Fetch Target size (number of bytes) */
    unsigned
    size()
    {
        return endAddress() - startAddress();
    }
 
    bool
    inRange(Addr addr)
    {
        return addr >= startAddress() && addr <= endAddress();
    }
 
    bool
    isExitInst(Addr addr)
    {
        return addr == endAddress();
    }
 
    bool
    isExitBranch(Addr addr)
    {
        return (addr == endAddress()) && is_branch;
    }
 
    bool
    hasExceeded(Addr addr)
    {
        return addr > endAddress();
    }

    FTSeqNum
    ftNum()
    {
        return ftSeqNum;
    }

    ThreadID
    getTid()
    {
        return tid;
    }

    void
    setPredTarg(const PCStateBase &pred_pc)
    {
        set(predPC, pred_pc);
    }

    const PCStateBase &
    readPredTarg()
    {
        assert(predPC != nullptr);
        return *predPC;
    }

    const PCStateBase &
    readStartPC()
    {
        assert(startPC != nullptr);
        return *startPC;
    }

    const PCStateBase &
    readEndPC()
    {
        assert(endPC != nullptr);
        return *endPC;
    }

    bool
    predTaken()
    {
        return taken;
    }

    void finalize(const PCStateBase &exit_pc, bool _is_branch, bool pred_taken,
                  const PCStateBase &pred_pc);

    std::string toString();
};
 
typedef std::shared_ptr<FetchTarget> FetchTargetPtr;

class FTQ
{
  public:
    FTQ(CPU *_cpu, const BaseO3CPUParams &params);
 
    std::string name() const;
 
  private:
    enum Status
    {
        Invalid,
        Valid,
        Full,
        Locked
    };

    std::array<Status, MaxThreads> ftqStatus;

    CPU *cpu;

    const unsigned numEntries;

    ProbePointArg<FetchTargetPtr> *ppFTQInsert;
    ProbePointArg<FetchTargetPtr> *ppFTQRemove;

    std::array<std::list<FetchTargetPtr>, MaxThreads> ftq;
 
  public:
    void regProbePoints();

    void resetState(ThreadID tid);

    unsigned numFreeEntries(ThreadID tid);

    unsigned size(ThreadID tid);

    bool isFull(ThreadID tid);

    bool isEmpty(ThreadID tid) const;

    void invalidate(ThreadID tid);

    bool isReady(ThreadID tid);

    void lock(ThreadID tid);

    bool isLocked(ThreadID tid);

    void forAllForward(ThreadID tid, std::function<void(FetchTargetPtr &)> f);

    void forAllBackward(ThreadID tid, std::function<void(FetchTargetPtr &)> f);

    void insert(ThreadID tid, FetchTargetPtr fetchTarget);

    void squash(ThreadID tid);

    void squashSanityCheck(ThreadID tid);

    bool isHeadReady(ThreadID tid);

    FetchTargetPtr readHead(ThreadID tid);

    bool popHead(ThreadID tid);

    void printFTQ(ThreadID tid);
 
  private:
    struct FTQStats : public statistics::Group
    {
        FTQStats(CPU *cpu, unsigned numFTQEntries);
 
        statistics::Scalar inserts;
        statistics::Scalar removals;
        statistics::Scalar squashes;
        statistics::Scalar locks;
 
        statistics::Distribution occupancy;
    } stats;
};
 
} // namespace o3
} // namespace gem5
 
#endif //__CPU_O3_FTQ_HH__