cpu.hh

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/*
 * Copyright (c) 2011-2013, 2016-2020 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * Copyright (c) 2022-2023 The University of Edinburgh
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2005 The Regents of The University of Michigan
 * Copyright (c) 2011 Regents of the University of California
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef __CPU_O3_CPU_HH__
#define __CPU_O3_CPU_HH__
 
#include <iostream>
#include <list>
#include <queue>
#include <set>
#include <vector>
 
#include "arch/generic/pcstate.hh"
#include "base/statistics.hh"
#include "cpu/activity.hh"
#include "cpu/base.hh"
#include "cpu/o3/bac.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/decode.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/fetch.hh"
#include "cpu/o3/free_list.hh"
#include "cpu/o3/ftq.hh"
#include "cpu/o3/iew.hh"
#include "cpu/o3/limits.hh"
#include "cpu/o3/rename.hh"
#include "cpu/o3/rob.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/thread_state.hh"
#include "cpu/simple_thread.hh"
#include "cpu/timebuf.hh"
#include "params/BaseO3CPU.hh"
#include "sim/process.hh"
 
namespace gem5
{
 
template <class>
class Checker;
class ThreadContext;
 
class Checkpoint;
class Process;
 
namespace o3
{
 
class ThreadContext;

class CPU : public BaseCPU
{
  public:
    typedef std::list<DynInstPtr>::iterator ListIt;
 
    friend class ThreadContext;
 
  public:
    enum Status
    {
        Running,
        Idle,
        Halted,
        Blocked,
        SwitchedOut
    };
 
    BaseMMU *mmu;
    using LSQRequest = LSQ::LSQRequest;
 
    using PerThreadUnifiedRenameMap =
        UnifiedRenameMap::PerThreadUnifiedRenameMap;

    Status _status;
 
  private:

    EventFunctionWrapper tickEvent;

    EventFunctionWrapper threadExitEvent;

    void
    scheduleTickEvent(Cycles delay)
    {
        if (tickEvent.squashed())
            reschedule(tickEvent, clockEdge(delay));
        else if (!tickEvent.scheduled())
            schedule(tickEvent, clockEdge(delay));
    }

    void
    unscheduleTickEvent()
    {
        if (tickEvent.scheduled())
            tickEvent.squash();
    }

    bool tryDrain();

    void drainSanityCheck() const;

    bool isCpuDrained() const;
 
  public:
    CPU(const BaseO3CPUParams &params);
 
    ProbePointArg<PacketPtr> *ppInstAccessComplete;
    ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;

    void regProbePoints() override;
 
    void
    demapPage(Addr vaddr, uint64_t asn)
    {
        mmu->demapPage(vaddr, asn);
    }

    void tick();

    void init() override;
 
    void startup() override;

    int
    numActiveThreads()
    {
        return activeThreads.size();
    }

    void activateThread(ThreadID tid);

    void deactivateThread(ThreadID tid);

    void insertThread(ThreadID tid);

    void removeThread(ThreadID tid);

    Counter totalInsts() const override;

    Counter totalOps() const override;

    void activateContext(ThreadID tid) override;

    void suspendContext(ThreadID tid) override;

    void haltContext(ThreadID tid) override;

    void updateThreadPriority();

    bool isDraining() const { return drainState() == DrainState::Draining; }
 
    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
    void unserializeThread(CheckpointIn &cp, ThreadID tid) override;

    void addThreadToExitingList(ThreadID tid);

    bool isThreadExiting(ThreadID tid) const;

    void scheduleThreadExitEvent(ThreadID tid);

    void exitThreads();
 
  public:
    DrainState drain() override;

    void drainResume() override;

    void commitDrained(ThreadID tid);

    void switchOut() override;

    void takeOverFrom(BaseCPU *oldCPU) override;
 
    void verifyMemoryMode() const override;

    InstSeqNum getAndIncrementInstSeq() { return globalSeqNum++; }

    InstSeqNum
    getAndIncrementFTSeq()
    {
        return globalFTSeqNum++;
    }

    void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);

    Fault getInterrupts();

    void processInterrupts(const Fault &interrupt);

    void halt() { panic("Halt not implemented!\n"); }


    RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;

    RegVal readMiscReg(int misc_reg, ThreadID tid);

    void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);

    void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
 
    RegVal getReg(PhysRegIdPtr phys_reg, ThreadID tid);
    void getReg(PhysRegIdPtr phys_reg, void *val, ThreadID tid);
    void *getWritableReg(PhysRegIdPtr phys_reg, ThreadID tid);
 
    void setReg(PhysRegIdPtr phys_reg, RegVal val, ThreadID tid);
    void setReg(PhysRegIdPtr phys_reg, const void *val, ThreadID tid);

 
    RegVal getArchReg(const RegId &reg, ThreadID tid);
    void getArchReg(const RegId &reg, void *val, ThreadID tid);
    void *getWritableArchReg(const RegId &reg, ThreadID tid);
 
    void setArchReg(const RegId &reg, RegVal val, ThreadID tid);
    void setArchReg(const RegId &reg, const void *val, ThreadID tid);

    void pcState(const PCStateBase &new_pc_state, ThreadID tid);

    const PCStateBase &pcState(ThreadID tid);

    void squashFromTC(ThreadID tid);

    ListIt addInst(const DynInstPtr &inst);

    void instDone(ThreadID tid, const DynInstPtr &inst);

    void removeFrontInst(const DynInstPtr &inst);

    void removeInstsNotInROB(ThreadID tid);

    void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);

    void squashInstIt(const ListIt &instIt, ThreadID tid);

    void cleanUpRemovedInsts();

    void dumpInsts();
 
  public:
#ifndef NDEBUG
    int instcount;
#endif

    std::list<DynInstPtr> instList;

    std::queue<ListIt> removeList;
 
#ifdef GEM5_DEBUG
    std::set<InstSeqNum> snList;
#endif

    bool removeInstsThisCycle;
 
  protected:
    BAC bac;

    FTQ ftq;

    Fetch fetch;

    Decode decode;

    Rename rename;

    IEW iew;

    Commit commit;

    PhysRegFile regFile;

    UnifiedFreeList freeList;

    PerThreadUnifiedRenameMap renameMap;

    PerThreadUnifiedRenameMap commitRenameMap;

    ROB rob;

    std::list<ThreadID> activeThreads;

    std::unordered_map<ThreadID, bool> exitingThreads;

    Scoreboard scoreboard;
 
    std::vector<BaseISA *> isa;
 
  public:
    enum StageIdx
    {
        BACIdx,
        FetchIdx,
        DecodeIdx,
        RenameIdx,
        IEWIdx,
        CommitIdx,
        NumStages
    };

    TimeBuffer<TimeStruct> timeBuffer;

    TimeBuffer<FetchStruct> fetchQueue;

    TimeBuffer<DecodeStruct> decodeQueue;

    TimeBuffer<RenameStruct> renameQueue;

    TimeBuffer<IEWStruct> iewQueue;
 
  private:
    ActivityRecorder activityRec;
 
  public:
    void activityThisCycle() { activityRec.activity(); }

    void
    activateStage(const StageIdx idx)
    {
        activityRec.activateStage(idx);
    }

    void
    deactivateStage(const StageIdx idx)
    {
        activityRec.deactivateStage(idx);
    }

    void wakeCPU();
 
    virtual void wakeup(ThreadID tid) override;

    ThreadID getFreeTid();

    bool inUserMode(ThreadID tid);
 
  public:
    gem5::ThreadContext *
    tcBase(ThreadID tid)
    {
        return thread[tid]->getTC();
    }

    InstSeqNum globalSeqNum;

    FTSeqNum globalFTSeqNum;

    gem5::Checker<DynInstPtr> *checker;

    System *system;

    std::vector<ThreadState *> thread;

    std::list<int> cpuWaitList;

    Cycles lastRunningCycle;

    Tick lastActivatedCycle;

    std::map<ThreadID, unsigned> threadMap;

    std::vector<ThreadID> tids;

    Fault
    pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
                unsigned int size, Addr addr, Request::Flags flags,
                uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr,
                const std::vector<bool>& byte_enable=std::vector<bool>())
 
    {
        return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
                flags, res, std::move(amo_op), byte_enable);
    }

    Port &
    getInstPort() override
    {
        return fetch.getInstPort();
    }

    Port &
    getDataPort() override
    {
        return iew.ldstQueue.getDataPort();
    }
 
    struct CPUStats : public statistics::Group
    {
        CPUStats(CPU *cpu);

        statistics::Scalar timesIdled;
        statistics::Scalar idleCycles;
        statistics::Scalar quiesceCycles;
    } cpuStats;
 
  public:
    // hardware transactional memory
    void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
                            HtmFailureFaultCause cause) override;
};
 
} // namespace o3
} // namespace gem5
 
#endif // __CPU_O3_CPU_HH__