gem5 [DEVELOP-FOR-25.1]
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host.cc
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1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "dev/pci/host.hh"
39
40#include "base/addr_range.hh"
41#include "debug/PciHost.hh"
42#include "dev/pci/device.hh"
43#include "dev/pci/types.hh"
44#include "dev/pci/upstream.hh"
45#include "dev/platform.hh"
46#include "params/GenericPciHost.hh"
47#include "params/PciHost.hh"
48
49namespace gem5
50{
51
52PciHost::PciHost(const PciHostParams &p) : PciUpstream(p)
53{}
54
58
59GenericPciHost::GenericPciHost(const GenericPciHostParams &p)
60 : PciHost(p),
62 confBase(p.conf_base), confSize(p.conf_size),
63 confDeviceBits(p.conf_device_bits),
64 pciPioBase(p.pci_pio_base), pciMemBase(p.pci_mem_base),
65 pciDmaBase(p.pci_dma_base)
66{
67}
68
72
78
81{
82 Addr bus_addr = (getBusNum() << 8) + (dev_addr.dev << 3) + dev_addr.func;
83
84 Addr start = confBase + (bus_addr << confDeviceBits);
85
86 return RangeSize(start, 1 << confDeviceBits);
87}
88
89void
94
95void
100
101uint32_t
103{
104 const PciDevice *dev(getDevice(addr));
105 assert(dev);
106
107 return dev->interruptLine();
108}
109
110} // namespace gem5
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition addr_range.hh:82
PciBusNum getBusNum() const override
Get the PCI bus number assign to that upstream.
Definition host.hh:138
const uint8_t confDeviceBits
Definition host.hh:155
virtual uint32_t mapPciInterrupt(const PciDevAddr &dev_addr, PciIntPin pin) const
Definition host.cc:102
const Addr confBase
Definition host.hh:153
GenericPciHost(const GenericPciHostParams &p)
Definition host.cc:59
void interfaceClearInt(const PciDevAddr &addr, PciIntPin pin) override
Post an interrupt to the CPU.
Definition host.cc:96
const Addr pciMemBase
Definition host.hh:158
AddrRange interfaceConfigRange(const PciDevAddr &dev_addr) const override
Calculate the physical address range of the PCI device configuration space.
Definition host.cc:80
const Addr confSize
Definition host.hh:154
virtual ~GenericPciHost()
Definition host.cc:69
AddrRange getConfigAddrRange() const override
Get the range for the configuration memory space for which this PCI upstream is responsible.
Definition host.cc:74
const Addr pciDmaBase
Definition host.hh:159
Platform & platform
Definition host.hh:151
void interfacePostInt(const PciDevAddr &addr, PciIntPin pin) override
Post an interrupt to the CPU.
Definition host.cc:90
const Addr pciPioBase
Definition host.hh:157
Base class to represent a PCI device.
Definition device.hh:297
uint8_t interruptLine() const
Definition device.hh:447
PciHost(const PciHostParams &p)
Definition host.cc:52
virtual ~PciHost()
Definition host.cc:55
PciUpstream(const Params &p)
Definition upstream.cc:69
PciDevice * getDevice(const PciDevAddr &addr)
Retrieve a PCI device from its bus address.
Definition upstream.cc:99
AddrRange RangeSize(Addr start, Addr size)
Bitfield< 0 > p
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
PciIntPin
Definition types.hh:74
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
Generic interface for platforms.
uint8_t dev
Definition types.hh:62
uint8_t func
Definition types.hh:63

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