lsq_unit.hh

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#ifndef __CPU_O3_LSQ_UNIT_HH__
#define __CPU_O3_LSQ_UNIT_HH__
 
#include <algorithm>
#include <cstring>
#include <map>
#include <memory>
#include <queue>
 
#include "arch/generic/debugfaults.hh"
#include "arch/generic/vec_reg.hh"
#include "base/circular_queue.hh"
#include "cpu/base.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/lsq.hh"
#include "cpu/timebuf.hh"
#include "debug/HtmCpu.hh"
#include "debug/LSQUnit.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
 
namespace gem5
{
 
struct BaseO3CPUParams;
 
namespace o3
{
 
class IEW;

class LSQUnit
{
  public:
    static constexpr auto MaxDataBytes = MaxVecRegLenInBytes;
 
    using LSQRequest = LSQ::LSQRequest;
  private:
    class LSQEntry
    {
      private:
        DynInstPtr _inst;
        LSQRequest* _request = nullptr;
        uint32_t _size = 0;
        bool _valid = false;
 
      public:
        ~LSQEntry()
        {
            if (_request != nullptr) {
                _request->freeLSQEntry();
                _request = nullptr;
            }
        }
 
        void
        clear()
        {
            _inst = nullptr;
            if (_request != nullptr) {
                _request->freeLSQEntry();
            }
            _request = nullptr;
            _valid = false;
            _size = 0;
        }
 
        void
        set(const DynInstPtr& new_inst)
        {
            assert(!_valid);
            _inst = new_inst;
            _valid = true;
            _size = 0;
        }
 
        LSQRequest* request() { return _request; }
        void setRequest(LSQRequest* r) { _request = r; }
        bool hasRequest() { return _request != nullptr; }
        bool valid() const { return _valid; }
        uint32_t& size() { return _size; }
        const uint32_t& size() const { return _size; }
        const DynInstPtr& instruction() const { return _inst; }
    };
 
    class SQEntry : public LSQEntry
    {
      private:
        char _data[MaxDataBytes];
        bool _canWB = false;
        bool _committed = false;
        bool _completed = false;
        bool _isAllZeros = false;
 
      public:
        static constexpr size_t DataSize = sizeof(_data);
        SQEntry()
        {
            std::memset(_data, 0, DataSize);
        }
 
        void set(const DynInstPtr& inst) { LSQEntry::set(inst); }
 
        void
        clear()
        {
            LSQEntry::clear();
            _canWB = _completed = _committed = _isAllZeros = false;
        }

        bool& canWB() { return _canWB; }
        const bool& canWB() const { return _canWB; }
        bool& completed() { return _completed; }
        const bool& completed() const { return _completed; }
        bool& committed() { return _committed; }
        const bool& committed() const { return _committed; }
        bool& isAllZeros() { return _isAllZeros; }
        const bool& isAllZeros() const { return _isAllZeros; }
        char* data() { return _data; }
        const char* data() const { return _data; }
    };
    using LQEntry = LSQEntry;

    enum class AddrRangeCoverage
    {
        PartialAddrRangeCoverage, /* Two ranges partly overlap */
        FullAddrRangeCoverage, /* One range fully covers another */
        NoAddrRangeCoverage /* Two ranges are disjoint */
    };
 
  public:
    using LoadQueue = CircularQueue<LQEntry>;
    using StoreQueue = CircularQueue<SQEntry>;
 
  public:
    LSQUnit(uint32_t lqEntries, uint32_t sqEntries);

    LSQUnit(const LSQUnit &l): stats(nullptr)
    {
        panic("LSQUnit is not copy-able");
    }

    void init(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params,
            LSQ *lsq_ptr, unsigned id);

    std::string name() const;

    void setDcachePort(RequestPort *dcache_port);

    void drainSanityCheck() const;

    void takeOverFrom();

    void insert(const DynInstPtr &inst);
    void insertLoad(const DynInstPtr &load_inst);
    void insertStore(const DynInstPtr &store_inst);

    Fault checkViolations(typename LoadQueue::iterator& loadIt,
            const DynInstPtr& inst);

    void checkSnoop(PacketPtr pkt);

    Fault executeLoad(const DynInstPtr &inst);
 
    Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
    Fault executeStore(const DynInstPtr &inst);

    void commitLoad();
    void commitLoads(InstSeqNum &youngest_inst);

    void commitStores(InstSeqNum &youngest_inst);

    void writebackStores();

    void completeDataAccess(PacketPtr pkt);

    void squash(const InstSeqNum &squashed_num);

    bool violation() { return memDepViolator; }

    DynInstPtr getMemDepViolator();

    unsigned numFreeLoadEntries();

    unsigned numFreeStoreEntries();

    int numLoads() { return loadQueue.size(); }

    int numStores() { return storeQueue.size(); }
 
    // hardware transactional memory
    int numHtmStarts() const { return htmStarts; }
    int numHtmStops() const { return htmStops; }
    void resetHtmStartsStops() { htmStarts = htmStops = 0; }
    uint64_t getLatestHtmUid() const;
    void
    setLastRetiredHtmUid(uint64_t htm_uid)
    {
        assert(htm_uid >= lastRetiredHtmUid);
        lastRetiredHtmUid = htm_uid;
    }
 
    // Stale translation checks
    void startStaleTranslationFlush();
    bool checkStaleTranslations() const;

    bool isFull() { return lqFull() || sqFull(); }

    bool isEmpty() const { return lqEmpty() && sqEmpty(); }

    bool lqFull() { return loadQueue.full(); }

    bool sqFull() { return storeQueue.full(); }

    bool lqEmpty() const { return loadQueue.size() == 0; }

    bool sqEmpty() const { return storeQueue.size() == 0; }

    unsigned getCount() { return loadQueue.size() + storeQueue.size(); }

    bool hasStoresToWB() { return storesToWB; }

    int numStoresToWB() { return storesToWB; }

    bool
    willWB()
    {
        return storeWBIt.dereferenceable() &&
                        storeWBIt->valid() &&
                        storeWBIt->canWB() &&
                        !storeWBIt->completed() &&
                        !isStoreBlocked;
    }

    void recvRetry();
 
    unsigned int cacheLineSize();
  private:
    void resetState();

    void writeback(const DynInstPtr &inst, PacketPtr pkt);

    void writebackBlockedStore();

    void completeStore(typename StoreQueue::iterator store_idx);

    void storePostSend();
 
  public:
    bool trySendPacket(bool isLoad, PacketPtr data_pkt);
 

    void dumpInsts() const;

    void schedule(Event& ev, Tick when);
 
    BaseMMU *getMMUPtr();
 
  private:
    CPU *cpu;

    IEW *iewStage;

    LSQ *lsq;

    RequestPort *dcachePort;

    class WritebackEvent : public Event
    {
      public:
        WritebackEvent(const DynInstPtr &_inst, PacketPtr pkt,
                LSQUnit *lsq_ptr);

        void process();

        const char *description() const;
 
      private:
        DynInstPtr inst;

        PacketPtr pkt;

        LSQUnit *lsqPtr;
    };
 
  public:
    bool recvTimingResp(PacketPtr pkt);
 
  private:
    ThreadID lsqID;
  public:
    StoreQueue storeQueue;

    LoadQueue loadQueue;
 
  private:
    unsigned depCheckShift;

    bool checkLoads;

    int storesToWB;
 
    // hardware transactional memory
    // nesting depth
    int htmStarts;
    int htmStops;
    // sanity checks and debugging
    uint64_t lastRetiredHtmUid;

    typename StoreQueue::iterator storeWBIt;

    Addr cacheBlockMask;

    typename TimeBuffer<IssueStruct>::wire fromIssue;

    bool stalled;
    InstSeqNum stallingStoreIsn;
    ssize_t stallingLoadIdx;

    PacketPtr retryPkt;

    bool isStoreBlocked;

    bool storeInFlight;

    DynInstPtr memDepViolator;

    bool needsTSO;
 
  protected:
    // Will also need how many read/write ports the Dcache has.  Or keep track
    // of that in stage that is one level up, and only call executeLoad/Store
    // the appropriate number of times.
    struct LSQUnitStats : public statistics::Group
    {
        LSQUnitStats(statistics::Group *parent);

        statistics::Scalar forwLoads;

        statistics::Scalar squashedLoads;

        statistics::Scalar ignoredResponses;

        statistics::Scalar memOrderViolation;

        statistics::Scalar squashedStores;

        statistics::Scalar rescheduledLoads;

        statistics::Scalar blockedByCache;

        statistics::Distribution loadToUse;

        statistics::Scalar addedLoadsAndStores;
    } stats;
 
  public:
    Fault read(LSQRequest *request, ssize_t load_idx);

    Fault write(LSQRequest *requst, uint8_t *data, ssize_t store_idx);

    int getLoadHead() { return loadQueue.head(); }

    InstSeqNum getLoadHeadSeqNum();

    int getStoreHead() { return storeQueue.head(); }
    InstSeqNum getStoreHeadSeqNum();

    bool isStalled()  { return stalled; }
  public:
    typedef typename CircularQueue<LQEntry>::iterator LQIterator;
    typedef typename CircularQueue<SQEntry>::iterator SQIterator;
};
 
} // namespace o3
} // namespace gem5
 
#endif // __CPU_O3_LSQ_UNIT_HH__