isa.hh File Reference

#include <string>
#include <unordered_map>
#include <vector>
#include "arch/generic/isa.hh"
#include "arch/riscv/pcstate.hh"
#include "arch/riscv/regs/misc.hh"
#include "arch/riscv/types.hh"
#include "base/types.hh"

Go to the source code of this file.

Classes
class	gem5::RiscvISA::ISA

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::RiscvISA

Typedefs
using	gem5::RiscvISA::VPUStatus = FPUStatus

Enumerations
enum	gem5::RiscvISA::PrivilegeMode { gem5::RiscvISA::PRV_U = 0 , gem5::RiscvISA::PRV_S = 1 , gem5::RiscvISA::PRV_HS = 2 , gem5::RiscvISA::PRV_M = 3 }
enum	gem5::RiscvISA::FPUStatus { gem5::RiscvISA::OFF = 0 , gem5::RiscvISA::INITIAL = 1 , gem5::RiscvISA::CLEAN = 2 , gem5::RiscvISA::DIRTY = 3 }

Functions
bool	gem5::RiscvISA::virtualizationEnabled (ExecContext *xc)
bool	gem5::RiscvISA::virtualizationEnabled (ThreadContext *tc)
void	gem5::RiscvISA::setV (ExecContext *xc)
void	gem5::RiscvISA::setV (ThreadContext *tc)
void	gem5::RiscvISA::resetV (ExecContext *xc)
void	gem5::RiscvISA::resetV (ThreadContext *tc)
Fault	gem5::RiscvISA::updateFPUStatus (ExecContext *xc, ExtMachInst machInst, bool set_dirty)
Fault	gem5::RiscvISA::updateVPUStatus (ExecContext *xc, ExtMachInst machInst, bool set_dirty, bool check_vill)
std::ostream &	operator<< (std::ostream &os, gem5::RiscvISA::PrivilegeMode pm)

Function Documentation

operator<<()

std::ostream & operator<<	(	std::ostream &	os,
		gem5::RiscvISA::PrivilegeMode	pm )

Definition at line 1421 of file isa.cc.

References gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, and gem5::RiscvISA::PRV_U.

Referenced by sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_unsigned::operator<<, sc_dt::sc_unsigned::operator<<, sc_dt::sc_unsigned::operator<<, and sc_dt::sc_unsigned::operator<<.