gem5 v25.0.0.1
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Public Types | Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
gem5::RiscvISA::ISA Class Reference

#include <isa.hh>

Inheritance diagram for gem5::RiscvISA::ISA:
gem5::BaseISA gem5::SimObject gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Public Types

using Params = RiscvISAParams
Public Types inherited from gem5::BaseISA
typedef std::vector< const RegClass * > RegClasses
Public Types inherited from gem5::SimObject
typedef SimObjectParams Params

Public Member Functions

void clear () override
PCStateBase * newPCState (Addr new_inst_addr=0) const override
RegVal readMiscRegNoEffect (RegIndex idx) const override
RegVal readMiscReg (RegIndex idx) override
void setMiscRegNoEffect (RegIndex idx, RegVal val) override
void setMiscReg (RegIndex idx, RegVal val) override
virtual const std::unordered_map< int, CSRMetadata > & getCSRDataMap () const
virtual const std::unordered_map< int, RegVal > & getCSRMaskMap () const
virtual const std::unordered_map< int, RegVal > & getCSRWriteMaskMap () const
bool inUserMode () const override
void copyRegsFrom (ThreadContext *src) override
void serialize (CheckpointOut &cp) const override
 Serialize an object.
void unserialize (CheckpointIn &cp) override
 Unserialize an object.
 ISA (const Params &p)
void handleLockedRead (const RequestPtr &req) override
bool handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) override
void handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) override
void globalClearExclusive () override
void resetThread () override
RiscvType rvType () const
bool getEnableRvv () const
bool virtualizationEnabled () const
void clearLoadReservation (ContextID cid)
unsigned getVecLenInBits ()
 Methods for getting VLEN, VLENB and ELEN values.
unsigned getVecLenInBytes ()
unsigned getVecElemLenInBits ()
int64_t getVectorLengthInBytes () const override
 This function returns the vector length of the Vector Length Agnostic extension of the ISA.
PrivilegeModeSet getPrivilegeModeSet ()
bool resumeOnPending ()
bool enableZcd ()
bool enableSmrnmi ()
virtual Addr getFaultHandlerAddr (RegIndex idx, uint64_t cause, bool intr) const
Addr rvSext (Addr addr) const
void swapToVirtCSR (uint64_t &csr, RegIndex &midx, std::string &csrName)
Fault hpmCounterCheck (int counter, ExtMachInst machInst) const
Fault tvmChecks (uint64_t csr, PrivilegeMode pm, ExtMachInst machInst)
RegVal backdoorReadCSRAllBits (ExecContext *xc, uint64_t csr)
RegVal readCSR (ExecContext *xc, uint64_t csr)
void writeCSR (ExecContext *xc, uint64_t csr, RegVal writeData)
Public Member Functions inherited from gem5::BaseISA
virtual void takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc)
virtual void setThreadContext (ThreadContext *_tc)
virtual uint64_t getExecutingAsid () const
const RegClasses & regClasses () const
const std::string & getIsaName () const
virtual void handleLockedRead (ExecContext *xc, const RequestPtr &req)
virtual bool handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask)
virtual void handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)
virtual void handleLockedSnoopHit ()
virtual void handleLockedSnoopHit (ExecContext *xc)
virtual void globalClearExclusive (ExecContext *xc)
Public Member Functions inherited from gem5::SimObject
const Params & params () const
 SimObject (const Params &p)
virtual ~SimObject ()
virtual void init ()
 init() is called after all C++ SimObjects have been created and all ports are connected.
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint.
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint.
virtual void regProbePoints ()
 Register probe points for this object.
virtual void regProbeListeners ()
 Register probe listeners for this object.
ProbeManager * getProbeManager ()
 Get the probe manager for this object.
virtual Port & getPort (const std::string &if_name, PortID idx=InvalidPortID)
 Get a port with a given name and index.
virtual void startup ()
 startup() is the final initialization call before simulation.
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining.
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes.
virtual void memInvalidate ()
 Invalidate the contents of memory buffers.
void serialize (CheckpointOut &cp) const override
 Serialize an object.
void unserialize (CheckpointIn &cp) override
 Unserialize an object.
Public Member Functions inherited from gem5::EventManager
EventQueue * eventQueue () const
void schedule (Event &event, Tick when)
void deschedule (Event &event)
void reschedule (Event &event, Tick when, bool always=false)
void schedule (Event *event, Tick when)
void deschedule (Event *event)
void reschedule (Event *event, Tick when, bool always=false)
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.
void setCurTick (Tick newVal)
 EventManager (EventManager &em)
 Event manger manages events in the event queue.
 EventManager (EventManager *em)
 EventManager (EventQueue *eq)
Public Member Functions inherited from gem5::Serializable
 Serializable ()
virtual ~Serializable ()
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section.
void serializeSection (CheckpointOut &cp, const std::string &name) const
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object.
void unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object.
virtual void notifyFork ()
 Notify a child process of a fork.
Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group.
virtual ~Group ()
virtual void regStats ()
 Callback to set stat parameters.
virtual void resetStats ()
 Callback to reset stats.
virtual void preDumpStats ()
 Callback before stats are dumped.
void addStat (statistics::Info *info)
 Register a stat with this group.
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object.
const std::vector< Info * > & getStats () const
 Get all stats associated with this object.
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block.
const Info * resolveStat (std::string name) const
 Resolve a stat by its name within this group.
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block.
 Group ()=delete
 Group (const Group &)=delete
Group & operator= (const Group &)=delete
Public Member Functions inherited from gem5::Named
 Named (std::string_view name_)
virtual ~Named ()=default
virtual std::string name () const

Protected Member Functions

bool hpmCounterEnabled (int counter) const
Protected Member Functions inherited from gem5::BaseISA
 BaseISA (const SimObjectParams &p, const std::string &name)
Protected Member Functions inherited from gem5::Drainable
 Drainable ()
virtual ~Drainable ()
virtual void drainResume ()
 Resume execution after a successful drain.
void signalDrainDone () const
 Signal that an object is drained.

Protected Attributes

RiscvType _rvType
std::vector< RegVal > miscRegFile
bool enableRvv
const int WARN_FAILURE = 10000
const Addr INVALID_RESERVATION_ADDR = (Addr)-1
std::unordered_map< int, Addr > load_reservation_addrs
unsigned vlen
 Length of each vector register in bits.
unsigned elen
 Length of each vector element in bits.
PrivilegeModeSet _privilegeModeSet
 The combination of privilege modes in Privilege Levels section of RISC-V privileged spec.
const bool _wfiResumeOnPending
 The WFI instruction can halt the execution of a hart.
bool _enableZcd
 Enable Zcd extensions.
bool _enableSmrnmi
 Resumable non-maskable interrupt Set true to make NMI recoverable.
Protected Attributes inherited from gem5::BaseISA
ThreadContext * tc = nullptr
RegClasses _regClasses
std::string isaName
Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters.
Protected Attributes inherited from gem5::EventManager
EventQueue * eventq
 A pointer to this object's event queue.

Additional Inherited Members

Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system.
static SimObject * find (const char *name)
 Find the SimObject with the given name and return a pointer to it.
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
static SimObjectResolver * getSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section.
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it.

Detailed Description

Definition at line 76 of file isa.hh.

Member Typedef Documentation

◆ Params

using gem5::RiscvISA::ISA::Params = RiscvISAParams

Definition at line 129 of file isa.hh.

Constructor & Destructor Documentation

◆ ISA()

gem5::RiscvISA::ISA::ISA ( const Params & p)

Definition at line 300 of file isa.cc.

References _enableSmrnmi, _enableZcd, _privilegeModeSet, gem5::BaseISA::_regClasses, _rvType, _wfiResumeOnPending, gem5::BaseISA::BaseISA(), gem5::ArmISA::ccRegClass, clear(), elen, enableRvv, fatal_if, gem5::RiscvISA::floatRegClass(), inform, gem5::RiscvISA::intRegClass(), gem5::ArmISA::matRegClass, gem5::RiscvISA::miscRegClass(), miscRegFile, gem5::RiscvISA::NUM_PHYS_MISCREGS, gem5::RiscvISA::p, gem5::ArmISA::vecElemClass, gem5::ArmISA::vecPredRegClass, gem5::RiscvISA::vecRegClass, and vlen.

Member Function Documentation

◆ backdoorReadCSRAllBits()

RegVal gem5::RiscvISA::ISA::backdoorReadCSRAllBits ( ExecContext * xc,
uint64_t csr )

Definition at line 1143 of file isa.cc.

References gem5::RiscvISA::CSR_FCSR, gem5::RiscvISA::FRM_OFFSET, getCSRDataMap(), gem5::RiscvISA::MISCREG_FFLAGS, gem5::RiscvISA::MISCREG_FRM, panic_if, and gem5::ExecContext::readMiscReg().

Referenced by readCSR(), and writeCSR().

◆ clear()

void gem5::RiscvISA::ISA::clear ( )
overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 357 of file isa.cc.

References _rvType, enableSmrnmi(), getEnableRvv(), getPrivilegeModeSet(), inform, gem5::RiscvISA::INITIAL, gem5::RiscvISA::MISCREG_ARCHID, gem5::RiscvISA::MISCREG_HSTATUS, gem5::RiscvISA::MISCREG_IMPID, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_MCOUNTEREN, gem5::RiscvISA::MISCREG_NMIE, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SCOUNTEREN, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TSELECT, gem5::RiscvISA::MISCREG_VENDORID, gem5::RiscvISA::MISCREG_VSSTATUS, miscRegFile, gem5::Named::name(), panic, gem5::RiscvISA::PRV_M, gem5::RiscvISA::RV32, gem5::RiscvISA::RV64, and gem5::ArmISA::status.

Referenced by ISA().

◆ clearLoadReservation()

void gem5::RiscvISA::ISA::clearLoadReservation ( ContextID cid)
inline

Definition at line 192 of file isa.hh.

References INVALID_RESERVATION_ADDR, and load_reservation_addrs.

◆ copyRegsFrom()

void gem5::RiscvISA::ISA::copyRegsFrom ( ThreadContext * src)
overridevirtual

Implements gem5::BaseISA.

Definition at line 332 of file isa.cc.

References gem5::RiscvISA::floatRegClass(), gem5::ThreadContext::getReg(), gem5::RiscvISA::i, gem5::RiscvISA::intRegClass(), gem5::RiscvISA::NUM_PHYS_MISCREGS, gem5::ThreadContext::pcState(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::BaseISA::tc, and gem5::RiscvISA::vecRegClass.

◆ enableSmrnmi()

bool gem5::RiscvISA::ISA::enableSmrnmi ( )
inline

Definition at line 211 of file isa.hh.

References _enableSmrnmi.

Referenced by gem5::RiscvISA::Interrupts::checkInterrupts(), clear(), and gem5::RiscvISA::RiscvFault::isResumableNonMaskableInterrupt().

◆ enableZcd()

bool gem5::RiscvISA::ISA::enableZcd ( )
inline

Definition at line 209 of file isa.hh.

References _enableZcd.

Referenced by gem5::RiscvISA::Decoder::Decoder().

◆ getCSRDataMap()

virtual const std::unordered_map< int, CSRMetadata > & gem5::RiscvISA::ISA::getCSRDataMap ( ) const
inlinevirtual

Definition at line 150 of file isa.hh.

References gem5::RiscvISA::CSRData.

Referenced by backdoorReadCSRAllBits(), readCSR(), swapToVirtCSR(), and writeCSR().

◆ getCSRMaskMap()

virtual const std::unordered_map< int, RegVal > & gem5::RiscvISA::ISA::getCSRMaskMap ( ) const
inlinevirtual

Definition at line 155 of file isa.hh.

References _privilegeModeSet, _rvType, and gem5::RiscvISA::CSRMasks.

Referenced by readCSR(), and writeCSR().

◆ getCSRWriteMaskMap()

virtual const std::unordered_map< int, RegVal > & gem5::RiscvISA::ISA::getCSRWriteMaskMap ( ) const
inlinevirtual

Definition at line 161 of file isa.hh.

References _privilegeModeSet, _rvType, and gem5::RiscvISA::CSRWriteMasks.

Referenced by writeCSR().

◆ getEnableRvv()

bool gem5::RiscvISA::ISA::getEnableRvv ( ) const
inline

Definition at line 187 of file isa.hh.

References enableRvv.

Referenced by clear(), and setMiscReg().

◆ getFaultHandlerAddr()

Addr gem5::RiscvISA::ISA::getFaultHandlerAddr ( RegIndex idx,
uint64_t cause,
bool intr ) const
virtual

Definition at line 1321 of file isa.cc.

References gem5::X86ISA::addr, gem5::bits(), gem5::mbits(), gem5::BaseISA::tc, and gem5::PowerISA::vec.

◆ getPrivilegeModeSet()

PrivilegeModeSet gem5::RiscvISA::ISA::getPrivilegeModeSet ( )
inline

Definition at line 205 of file isa.hh.

References _privilegeModeSet.

Referenced by clear(), and setMiscReg().

◆ getVecElemLenInBits()

unsigned gem5::RiscvISA::ISA::getVecElemLenInBits ( )
inline

Definition at line 201 of file isa.hh.

References elen.

Referenced by gem5::RiscvISA::Decoder::Decoder().

◆ getVecLenInBits()

unsigned gem5::RiscvISA::ISA::getVecLenInBits ( )
inline

Methods for getting VLEN, VLENB and ELEN values.

Definition at line 199 of file isa.hh.

References vlen.

Referenced by gem5::RiscvISA::Decoder::Decoder().

◆ getVecLenInBytes()

unsigned gem5::RiscvISA::ISA::getVecLenInBytes ( )
inline

Definition at line 200 of file isa.hh.

References vlen.

Referenced by readMiscReg().

◆ getVectorLengthInBytes()

int64_t gem5::RiscvISA::ISA::getVectorLengthInBytes ( ) const
inlineoverridevirtual

This function returns the vector length of the Vector Length Agnostic extension of the ISA.

For ARM ISA, this function returns the SVE/SVE2 vector length. For RISC-V ISA, this function returns the RVV vector length. For other ISAs, this function returns -1.

Reimplemented from gem5::BaseISA.

Definition at line 203 of file isa.hh.

References vlen.

◆ globalClearExclusive()

void gem5::RiscvISA::ISA::globalClearExclusive ( )
overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 1065 of file isa.cc.

References INVALID_RESERVATION_ADDR, load_reservation_addrs, and gem5::BaseISA::tc.

◆ handleLockedRead()

void gem5::RiscvISA::ISA::handleLockedRead ( const RequestPtr & req)
overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 1007 of file isa.cc.

References DPRINTF, load_reservation_addrs, and gem5::BaseISA::tc.

◆ handleLockedSnoop()

void gem5::RiscvISA::ISA::handleLockedSnoop ( PacketPtr pkt,
Addr cacheBlockMask )
overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 993 of file isa.cc.

References DPRINTF, gem5::Packet::getAddr(), INVALID_RESERVATION_ADDR, load_reservation_addrs, and gem5::BaseISA::tc.

◆ handleLockedWrite()

bool gem5::RiscvISA::ISA::handleLockedWrite ( const RequestPtr & req,
Addr cacheBlockMask )
overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 1017 of file isa.cc.

References gem5::curTick(), DPRINTF, INVALID_RESERVATION_ADDR, load_reservation_addrs, gem5::BaseISA::tc, warn, and WARN_FAILURE.

◆ hpmCounterCheck()

Fault gem5::RiscvISA::ISA::hpmCounterCheck ( int counter,
ExtMachInst machInst ) const

Definition at line 434 of file isa.cc.

References gem5::bits(), gem5::csprintf(), gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_CYCLEH, gem5::RiscvISA::MISCREG_HCOUNTEREN, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_MCOUNTEREN, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SCOUNTEREN, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::NoFault, panic, gem5::RiscvISA::PRV_HS, gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_U, readMiscRegNoEffect(), and virtualizationEnabled().

◆ hpmCounterEnabled()

bool gem5::RiscvISA::ISA::hpmCounterEnabled ( int counter) const
protected

◆ inUserMode()

bool gem5::RiscvISA::ISA::inUserMode ( ) const
overridevirtual

Implements gem5::BaseISA.

Definition at line 326 of file isa.cc.

References gem5::RiscvISA::MISCREG_PRV, miscRegFile, and gem5::RiscvISA::PRV_U.

◆ newPCState()

PCStateBase * gem5::RiscvISA::ISA::newPCState ( Addr new_inst_addr = 0) const
inlineoverridevirtual

Implements gem5::BaseISA.

Definition at line 134 of file isa.hh.

References _rvType, and rvSext().

◆ readCSR()

RegVal gem5::RiscvISA::ISA::readCSR ( ExecContext * xc,
uint64_t csr )

Definition at line 1165 of file isa.cc.

References backdoorReadCSRAllBits(), gem5::RiscvISA::CSR_HIE, gem5::RiscvISA::CSR_HIP, gem5::RiscvISA::CSR_HVIP, gem5::RiscvISA::CSR_SIE, gem5::RiscvISA::CSR_SIP, gem5::RiscvISA::CSR_VSIE, gem5::RiscvISA::CSR_VSIP, getCSRDataMap(), getCSRMaskMap(), gem5::RiscvISA::INTERRUPT, gem5::RiscvISA::mask, gem5::RiscvISA::MISCREG_HIDELEG, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_MIDELEG, panic_if, and gem5::ExecContext::readMiscReg().

◆ readMiscReg()

RegVal gem5::RiscvISA::ISA::readMiscReg ( RegIndex idx)
overridevirtual

Implements gem5::BaseISA.

Definition at line 492 of file isa.cc.

References _rvType, gem5::bits(), gem5::RiscvISA::FFLAGS_MASK, getVecLenInBytes(), gem5::RiscvISA::HS_INTERRUPTS, gem5::mbits(), gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_CYCLEH, gem5::RiscvISA::MISCREG_FFLAGS, gem5::RiscvISA::MISCREG_FFLAGS_EXE, gem5::RiscvISA::MISCREG_HARTID, gem5::RiscvISA::MISCREG_HPMCOUNTER03, gem5::RiscvISA::MISCREG_HPMCOUNTER03H, gem5::RiscvISA::MISCREG_HPMCOUNTER31, gem5::RiscvISA::MISCREG_HPMCOUNTER31H, gem5::RiscvISA::MISCREG_HSTATUS, gem5::RiscvISA::MISCREG_HVIP, gem5::RiscvISA::MISCREG_IE, gem5::RiscvISA::MISCREG_INSTRET, gem5::RiscvISA::MISCREG_INSTRETH, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_MEPC, gem5::RiscvISA::MISCREG_MIDELEG, gem5::RiscvISA::MISCREG_MNEPC, gem5::RiscvISA::MISCREG_MNSTATUS, gem5::RiscvISA::MISCREG_NMIE, gem5::RiscvISA::MISCREG_SEPC, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TIME, gem5::RiscvISA::MISCREG_TIMEH, gem5::RiscvISA::MISCREG_VCSR, gem5::RiscvISA::MISCREG_VL, gem5::RiscvISA::MISCREG_VLENB, gem5::RiscvISA::MISCREG_VSSTATUS, gem5::RiscvISA::MISCREG_VTYPE, gem5::RiscvISA::MISCREG_VXRM, gem5::RiscvISA::MISCREG_VXSAT, gem5::Named::name(), panic, gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, gem5::RiscvISA::PRV_U, readMiscRegNoEffect(), gem5::RiscvISA::RV32, gem5::RiscvISA::RV64, setMiscRegNoEffect(), gem5::ArmISA::status, gem5::BaseISA::tc, gem5::X86ISA::val, gem5::RiscvISA::PCState::vl(), gem5::RiscvISA::VSXL_OFFSET, and gem5::RiscvISA::PCState::vtype().

Referenced by tvmChecks().

◆ readMiscRegNoEffect()

RegVal gem5::RiscvISA::ISA::readMiscRegNoEffect ( RegIndex idx) const
overridevirtual

Implements gem5::BaseISA.

Definition at line 482 of file isa.cc.

References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_PHYS_MISCREGS, and panic_if.

Referenced by hpmCounterCheck(), readMiscReg(), setMiscReg(), and virtualizationEnabled().

◆ resetThread()

void gem5::RiscvISA::ISA::resetThread ( )
overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 1073 of file isa.cc.

References gem5::RiscvISA::Reset::invoke(), and gem5::BaseISA::tc.

◆ resumeOnPending()

bool gem5::RiscvISA::ISA::resumeOnPending ( )
inline

Definition at line 207 of file isa.hh.

References _wfiResumeOnPending.

◆ rvSext()

Addr gem5::RiscvISA::ISA::rvSext ( Addr addr) const
inline

Definition at line 216 of file isa.hh.

References _rvType, gem5::X86ISA::addr, gem5::RiscvISA::RV32, and gem5::sext().

Referenced by newPCState(), and setMiscReg().

◆ rvType()

RiscvType gem5::RiscvISA::ISA::rvType ( ) const
inline

Definition at line 185 of file isa.hh.

References _rvType.

Referenced by gem5::RiscvISA::TLB::getValidAddr().

◆ serialize()

void gem5::RiscvISA::ISA::serialize ( CheckpointOut & cp) const
overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters
cpCheckpoint state

Reimplemented from gem5::BaseISA.

Definition at line 977 of file isa.cc.

References DPRINTF, miscRegFile, gem5::BaseISA::serialize(), and SERIALIZE_CONTAINER.

◆ setMiscReg()

void gem5::RiscvISA::ISA::setMiscReg ( RegIndex idx,
RegVal val )
overridevirtual

Implements gem5::BaseISA.

Definition at line 687 of file isa.cc.

References _rvType, gem5::bits(), gem5::RiscvISA::CSR_VSSTATUS, gem5::RiscvISA::CSRWriteMasks, gem5::RiscvISA::FFLAGS_MASK, getEnableRvv(), getPrivilegeModeSet(), gem5::RiscvISA::i, gem5::RiscvISA::mask, gem5::RiscvISA::MI_MASK, gem5::RiscvISA::MIDELEG_MASK, gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_FFLAGS, gem5::RiscvISA::MISCREG_FFLAGS_EXE, gem5::RiscvISA::MISCREG_HGATP, gem5::RiscvISA::MISCREG_HPMCOUNTER31, gem5::RiscvISA::MISCREG_HVIP, gem5::RiscvISA::MISCREG_IE, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_JVT, gem5::RiscvISA::MISCREG_MIDELEG, gem5::RiscvISA::MISCREG_MNSTATUS, gem5::RiscvISA::MISCREG_NMIE, gem5::RiscvISA::MISCREG_PMPADDR00, gem5::RiscvISA::MISCREG_PMPADDR15, gem5::RiscvISA::MISCREG_PMPCFG0, gem5::RiscvISA::MISCREG_PMPCFG1, gem5::RiscvISA::MISCREG_PMPCFG2, gem5::RiscvISA::MISCREG_PMPCFG3, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SATP, gem5::RiscvISA::MISCREG_SENVCFG, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TSELECT, gem5::RiscvISA::MISCREG_VCSR, gem5::RiscvISA::MISCREG_VIRT, gem5::RiscvISA::MISCREG_VSATP, gem5::RiscvISA::MISCREG_VSSTATUS, gem5::RiscvISA::MISCREG_VXRM, gem5::RiscvISA::MISCREG_VXSAT, gem5::RiscvISA::MiscRegNames, gem5::Named::name(), gem5::GenericISA::PCStateWithNext::npc(), panic, gem5::RiscvISA::PRV_M, readMiscRegNoEffect(), gem5::RiscvISA::RV32, gem5::RiscvISA::RV64, rvSext(), setMiscRegNoEffect(), gem5::RiscvISA::STATUS_SXL_MASK, gem5::RiscvISA::STATUS_UXL_MASK, gem5::RiscvISA::STATUS_VS_MASK, gem5::BaseISA::tc, gem5::X86ISA::val, and warn.

◆ setMiscRegNoEffect()

void gem5::RiscvISA::ISA::setMiscRegNoEffect ( RegIndex idx,
RegVal val )
overridevirtual

Implements gem5::BaseISA.

Definition at line 677 of file isa.cc.

References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_PHYS_MISCREGS, panic_if, and gem5::X86ISA::val.

Referenced by readMiscReg(), and setMiscReg().

◆ swapToVirtCSR()

void gem5::RiscvISA::ISA::swapToVirtCSR ( uint64_t & csr,
RegIndex & midx,
std::string & csrName )

Definition at line 1086 of file isa.cc.

References gem5::RiscvISA::CSR_SATP, gem5::RiscvISA::CSR_SCAUSE, gem5::RiscvISA::CSR_SEPC, gem5::RiscvISA::CSR_SIE, gem5::RiscvISA::CSR_SIP, gem5::RiscvISA::CSR_SSCRATCH, gem5::RiscvISA::CSR_SSTATUS, gem5::RiscvISA::CSR_STVAL, gem5::RiscvISA::CSR_STVEC, gem5::RiscvISA::CSR_VSATP, gem5::RiscvISA::CSR_VSCAUSE, gem5::RiscvISA::CSR_VSEPC, gem5::RiscvISA::CSR_VSIE, gem5::RiscvISA::CSR_VSIP, gem5::RiscvISA::CSR_VSSCRATCH, gem5::RiscvISA::CSR_VSSTATUS, gem5::RiscvISA::CSR_VSTVAL, gem5::RiscvISA::CSR_VSTVEC, getCSRDataMap(), and panic.

◆ tvmChecks()

Fault gem5::RiscvISA::ISA::tvmChecks ( uint64_t csr,
PrivilegeMode pm,
ExtMachInst machInst )

Definition at line 1112 of file isa.cc.

References gem5::RiscvISA::CSR_HGATP, gem5::RiscvISA::CSR_SATP, gem5::RiscvISA::CSR_VSATP, gem5::RiscvISA::MISCREG_HSTATUS, gem5::RiscvISA::MISCREG_STATUS, gem5::NoFault, gem5::RiscvISA::PRV_M, readMiscReg(), gem5::ArmISA::status, and virtualizationEnabled().

◆ unserialize()

void gem5::RiscvISA::ISA::unserialize ( CheckpointIn & cp)
overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters
cpCheckpoint state

Implements gem5::Serializable.

Definition at line 986 of file isa.cc.

References DPRINTF, miscRegFile, and UNSERIALIZE_CONTAINER.

◆ virtualizationEnabled()

bool gem5::RiscvISA::ISA::virtualizationEnabled ( ) const

Definition at line 1079 of file isa.cc.

References gem5::RiscvISA::MISCREG_VIRT, and readMiscRegNoEffect().

Referenced by hpmCounterCheck(), and tvmChecks().

◆ writeCSR()

void gem5::RiscvISA::ISA::writeCSR ( ExecContext * xc,
uint64_t csr,
RegVal writeData )

Definition at line 1213 of file isa.cc.

References backdoorReadCSRAllBits(), gem5::bits(), gem5::RiscvISA::CSR_FCSR, gem5::RiscvISA::CSR_HIE, gem5::RiscvISA::CSR_HIP, gem5::RiscvISA::CSR_HVIP, gem5::RiscvISA::CSR_SIE, gem5::RiscvISA::CSR_SIP, gem5::RiscvISA::CSR_VSIE, gem5::RiscvISA::CSR_VSIP, getCSRDataMap(), getCSRMaskMap(), getCSRWriteMaskMap(), gem5::RiscvISA::INTERRUPT, gem5::RiscvISA::mask, gem5::RiscvISA::MISCREG_FFLAGS, gem5::RiscvISA::MISCREG_FRM, gem5::RiscvISA::MISCREG_HIDELEG, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_MIDELEG, panic_if, gem5::ExecContext::readMiscReg(), gem5::ExecContext::setMiscReg(), and gem5::RiscvISA::VSSI_MASK.

Member Data Documentation

◆ _enableSmrnmi

bool gem5::RiscvISA::ISA::_enableSmrnmi
protected

Resumable non-maskable interrupt Set true to make NMI recoverable.

Definition at line 126 of file isa.hh.

Referenced by enableSmrnmi(), and ISA().

◆ _enableZcd

bool gem5::RiscvISA::ISA::_enableZcd
protected

Enable Zcd extensions.

Set the option to false implies the Zcmp and Zcmt is enable as c.fsdsp is overlap with them. Refs: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc

Definition at line 120 of file isa.hh.

Referenced by enableZcd(), and ISA().

◆ _privilegeModeSet

PrivilegeModeSet gem5::RiscvISA::ISA::_privilegeModeSet
protected

The combination of privilege modes in Privilege Levels section of RISC-V privileged spec.

Definition at line 103 of file isa.hh.

Referenced by getCSRMaskMap(), getCSRWriteMaskMap(), getPrivilegeModeSet(), and ISA().

◆ _rvType

RiscvType gem5::RiscvISA::ISA::_rvType
protected

Definition at line 79 of file isa.hh.

Referenced by clear(), getCSRMaskMap(), getCSRWriteMaskMap(), ISA(), newPCState(), readMiscReg(), rvSext(), rvType(), and setMiscReg().

◆ _wfiResumeOnPending

const bool gem5::RiscvISA::ISA::_wfiResumeOnPending
protected

The WFI instruction can halt the execution of a hart.

If this variable is set true, the execution resumes if an interrupt becomes pending. If this variable is set to false, the execution only resumes if an locally enabled interrupt becomes pending.

Definition at line 112 of file isa.hh.

Referenced by ISA(), and resumeOnPending().

◆ elen

unsigned gem5::RiscvISA::ISA::elen
protected

Length of each vector element in bits.

ELEN in Ch. 2 of RISC-V vector spec

Definition at line 98 of file isa.hh.

Referenced by getVecElemLenInBits(), and ISA().

◆ enableRvv

bool gem5::RiscvISA::ISA::enableRvv
protected

Definition at line 81 of file isa.hh.

Referenced by getEnableRvv(), and ISA().

◆ INVALID_RESERVATION_ADDR

const Addr gem5::RiscvISA::ISA::INVALID_RESERVATION_ADDR = (Addr)-1
protected

Definition at line 87 of file isa.hh.

Referenced by clearLoadReservation(), globalClearExclusive(), handleLockedSnoop(), and handleLockedWrite().

◆ load_reservation_addrs

std::unordered_map<int, Addr> gem5::RiscvISA::ISA::load_reservation_addrs
protected

Definition at line 88 of file isa.hh.

Referenced by clearLoadReservation(), globalClearExclusive(), handleLockedRead(), handleLockedSnoop(), and handleLockedWrite().

◆ miscRegFile

std::vector<RegVal> gem5::RiscvISA::ISA::miscRegFile
protected

Definition at line 80 of file isa.hh.

Referenced by clear(), hpmCounterCheck(), inUserMode(), ISA(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().

◆ vlen

unsigned gem5::RiscvISA::ISA::vlen
protected

Length of each vector register in bits.

VLEN in Ch. 2 of RISC-V vector spec

Definition at line 93 of file isa.hh.

Referenced by getVecLenInBits(), getVecLenInBytes(), getVectorLengthInBytes(), and ISA().

◆ WARN_FAILURE

const int gem5::RiscvISA::ISA::WARN_FAILURE = 10000
protected

Definition at line 86 of file isa.hh.

Referenced by handleLockedWrite().

The documentation for this class was generated from the following files:
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