tlb.hh

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#ifndef __ARCH_AMDGPU_VEGA_TLB_HH__
#define __ARCH_AMDGPU_VEGA_TLB_HH__
 
#include <list>
#include <queue>
#include <string>
#include <vector>
 
#include "arch/amdgpu/vega/pagetable.hh"
#include "arch/generic/mmu.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "params/VegaGPUTLB.hh"
#include "sim/clocked_object.hh"
 
namespace gem5
{
 
class BaseMMU;
class Packet;
class AMDGPUDevice;
class ThreadContext;
 
namespace VegaISA
{
 
class Walker;
 
class GpuTLB : public ClockedObject
{
  public:
    GpuTLB(const VegaGPUTLBParams &p);
    ~GpuTLB();
 
    typedef enum BaseMMU::Mode Mode;
 
    class Translation
    {
      public:
        virtual ~Translation() { }
 
        virtual void markDelayed() = 0;
 
        virtual void finish(Fault fault, const RequestPtr &req,
                            Mode mode) = 0;
 
        virtual bool squashed() const { return false; }
    };
 
    Addr pageAlign(Addr vaddr);
    void dumpAll();
    VegaTlbEntry *lookup(Addr va, bool update_lru=true);
 
    Walker *getWalker();
    void invalidateAll();
    void demapPage(Addr va, uint64_t asn);
 
  protected:
    typedef std::list<VegaTlbEntry*> EntryList;
    EntryList::iterator lookupIt(Addr va, bool update_lru=true);
    Walker *walker;
    AMDGPUDevice *gpuDevice;
 
    int size;
    int assoc;
    int numSets;
 
    bool FA;
    Addr setMask;
 
    bool allocationPolicy;
 
    bool hasMemSidePort;
 
    std::vector<VegaTlbEntry> tlb;
 
    /*
     * It's a per-set list. As long as we have not reached
     * the full capacity of the given set, grab an entry from
     * the freeList.
     */
    std::vector<EntryList> freeList;
 
    std::vector<EntryList> entryList;
 
  public:
    // latencies for a TLB hit, miss and page fault
    int hitLatency;
    int missLatency1;
    int missLatency2;
 
    struct VegaTLBStats : public statistics::Group
    {
        VegaTLBStats(statistics::Group *parent);
 
        statistics::Scalar maxDownstreamReached;
        statistics::Scalar outstandingReqsMax;
 
        // local_stats are as seen from the TLB
        // without taking into account coalescing
        statistics::Scalar localNumTLBAccesses;
        statistics::Scalar localNumTLBHits;
        statistics::Scalar localNumTLBMisses;
        statistics::Formula localTLBMissRate;
 
        // global_stats are as seen from the
        // CU's perspective taking into account
        // all coalesced requests.
        statistics::Scalar globalNumTLBAccesses;
        statistics::Scalar globalNumTLBHits;
        statistics::Scalar globalNumTLBMisses;
        statistics::Formula globalTLBMissRate;
 
        // from the CU perspective (global)
        statistics::Scalar accessCycles;
        statistics::Scalar pageTableCycles;
 
        // from the perspective of this TLB
        statistics::Scalar localCycles;
        statistics::Formula localLatency;
    } stats;
 
 
    VegaTlbEntry *insert(Addr vpn, VegaTlbEntry &entry);
 
    // Checkpointing
    virtual void serialize(CheckpointOut& cp) const override;
    virtual void unserialize(CheckpointIn& cp) override;
    void issueTranslation();
    enum tlbOutcome {TLB_HIT, TLB_MISS, PAGE_WALK, MISS_RETURN};
    VegaTlbEntry *tlbLookup(const RequestPtr &req, bool update_stats);
 
    void walkerResponse(VegaTlbEntry& entry, PacketPtr pkt);
    void handleTranslationReturn(Addr addr, tlbOutcome outcome,
                                 PacketPtr pkt);
 
    void handleFuncTranslationReturn(PacketPtr pkt, tlbOutcome outcome);
 
    void pagingProtectionChecks(PacketPtr pkt,
                                VegaTlbEntry *tlb_entry, Mode mode);
 
    void updatePhysAddresses(Addr virt_page_addr, VegaTlbEntry *tlb_entry,
                             Addr phys_page_addr);
 
    void issueTLBLookup(PacketPtr pkt);
 
    // CpuSidePort is the TLB Port closer to the CPU/CU side
    class CpuSidePort : public ResponsePort
    {
      public:
        CpuSidePort(const std::string &_name, GpuTLB * gpu_TLB,
                    PortID _index)
            : ResponsePort(_name), tlb(gpu_TLB), index(_index) { }
 
      protected:
        GpuTLB *tlb;
        int index;
 
        virtual bool recvTimingReq(PacketPtr pkt);
        virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
        virtual void recvFunctional(PacketPtr pkt);
        virtual void recvRangeChange() { }
        virtual void recvReqRetry();
        virtual void recvRespRetry() { panic("recvRespRetry called"); }
        virtual AddrRangeList getAddrRanges() const;
    };
 
    class MemSidePort : public RequestPort
    {
      public:
        MemSidePort(const std::string &_name, GpuTLB * gpu_TLB,
                    PortID _index)
            : RequestPort(_name), tlb(gpu_TLB), index(_index) { }
 
        std::deque<PacketPtr> retries;
 
      protected:
        GpuTLB *tlb;
        int index;
 
        virtual bool recvTimingResp(PacketPtr pkt);
        virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
        virtual void recvFunctional(PacketPtr pkt) { }
        virtual void recvRangeChange() { }
        virtual void recvReqRetry();
    };
 
    // TLB ports on the cpu Side
    std::vector<CpuSidePort*> cpuSidePort;
    // TLB ports on the memory side
    std::vector<MemSidePort*> memSidePort;
 
    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;
 
    Fault createPagefault(Addr vaddr, Mode mode);
 
    // maximum number of permitted coalesced requests per cycle
    int maxCoalescedReqs;
 
    // Current number of outstandings coalesced requests.
    // Should be <= maxCoalescedReqs
    int outstandingReqs;
 
    void translationReturn(Addr virtPageAddr, tlbOutcome outcome,
                           PacketPtr pkt);
 
    class TLBEvent : public Event
    {
        private:
            GpuTLB *tlb;
            Addr virtPageAddr;
            tlbOutcome outcome;
            PacketPtr pkt;
 
        public:
            TLBEvent(GpuTLB *_tlb, Addr _addr, tlbOutcome outcome,
                    PacketPtr _pkt);
 
            void process();
            const char *description() const;
 
            // updateOutcome updates the tlbOutcome of a TLBEvent
            void updateOutcome(tlbOutcome _outcome);
            Addr getTLBEventVaddr();
    };
 
    std::unordered_map<Addr, TLBEvent*> translationReturnEvent;
 
    // this FIFO queue keeps track of the virt. page addresses
    // that are pending cleanup
    std::queue<Addr> cleanupQueue;
 
    // the cleanupEvent is scheduled after a TLBEvent triggers in order to
    // free memory and do the required clean-up
    void cleanup();
 
    EventFunctionWrapper cleanupEvent;
};
 
} // namespace VegaISA
 
} // namespace gem5
 
#endif // __ARCH_AMDGPU_VEGA_TLB_HH__