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se_workload.hh
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27 
28 #ifndef __ARCH_POWER_SE_WORKLOAD_HH__
29 #define __ARCH_POWER_SE_WORKLOAD_HH__
30 
31 #include "arch/power/regs/int.hh"
32 #include "arch/power/regs/misc.hh"
33 #include "arch/power/remote_gdb.hh"
34 #include "params/PowerSEWorkload.hh"
35 #include "sim/se_workload.hh"
36 #include "sim/syscall_abi.hh"
37 #include "sim/syscall_desc.hh"
38 
39 namespace gem5
40 {
41 
42 namespace PowerISA
43 {
44 
46 {
47  public:
48  PARAMS(PowerSEWorkload);
49  SEWorkload(const Params &p, Addr page_shift) :
50  gem5::SEWorkload(p, page_shift)
51  {}
52 
53  void
54  setSystem(System *sys) override
55  {
57  gdb = BaseRemoteGDB::build<RemoteGDB>(
58  params().remote_gdb_port, system);
59  }
60 
61  loader::Arch getArch() const override { return loader::Power; }
62 
64  {
66  };
67 };
68 
69 } // namespace PowerISA
70 
71 namespace guest_abi
72 {
73 
74 template <>
75 struct Result<PowerISA::SEWorkload::SyscallABI, SyscallReturn>
76 {
77  static void
79  {
81  if (ret.successful()) {
82  cr.cr0.so = 0;
83  } else {
84  cr.cr0.so = 1;
85  }
88  }
89 };
90 
91 } // namespace guest_abi
92 } // namespace gem5
93 
94 #endif // __ARCH_POWER_SE_WORKLOAD_HH__
gem5::PowerISA::SEWorkload::SyscallABI::ArgumentRegs
static const std::vector< RegId > ArgumentRegs
Definition: se_workload.hh:65
remote_gdb.hh
gem5::PowerISA::SEWorkload::setSystem
void setSystem(System *sys) override
Definition: se_workload.hh:54
gem5::SyscallReturn
This class represents the return value from an emulated system call, including any errno setting.
Definition: syscall_return.hh:55
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:180
gem5::PowerISA::SEWorkload::SEWorkload
SEWorkload(const Params &p, Addr page_shift)
Definition: se_workload.hh:49
gem5::Workload::gdb
BaseRemoteGDB * gdb
Definition: workload.hh:77
gem5::PowerISA::ReturnValueReg
constexpr auto & ReturnValueReg
Definition: int.hh:153
gem5::GenericSyscallABI64
Definition: syscall_abi.hh:47
std::vector
STL vector class.
Definition: stl.hh:37
syscall_abi.hh
gem5::SEWorkload::Params
SEWorkloadParams Params
Definition: se_workload.hh:45
gem5::loader::Power
@ Power
Definition: object_file.hh:72
gem5::System
Definition: system.hh:74
gem5::PowerISA::SEWorkload::PARAMS
PARAMS(PowerSEWorkload)
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::X86ISA::misc_reg::cr
static RegIndex cr(int index)
Definition: misc.hh:421
gem5::guest_abi::Result< PowerISA::SEWorkload::SyscallABI, SyscallReturn >::store
static void store(ThreadContext *tc, const SyscallReturn &ret)
Definition: se_workload.hh:78
gem5::PowerISA::SEWorkload::getArch
loader::Arch getArch() const override
Definition: se_workload.hh:61
gem5::loader::Arch
Arch
Definition: object_file.hh:61
int.hh
gem5::SyscallReturn::encodedValue
int64_t encodedValue() const
The encoded value (as described above)
Definition: syscall_return.hh:122
gem5::ArmISA::SEWorkload
Definition: se_workload.hh:42
misc.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::int_reg::Cr
constexpr RegId Cr
Definition: int.hh:138
gem5::ArmISA::SEWorkload::setSystem
void setSystem(System *sys) override
Definition: se_workload.hh:52
gem5::PowerISA::SEWorkload::SyscallABI
Definition: se_workload.hh:63
gem5::Workload::system
System * system
Definition: workload.hh:81
gem5::PowerISA::SEWorkload
Definition: se_workload.hh:45
gem5::guest_abi::Result
Definition: definition.hh:63
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
syscall_desc.hh
gem5::SyscallReturn::successful
bool successful() const
Was the system call successful?
Definition: syscall_return.hh:91
se_workload.hh
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:188

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