#include <base.hh>

Inheritance diagram for gem5::BaseSimpleCPU:

Public Member Functions
	BaseSimpleCPU (const BaseSimpleCPUParams &params)

virtual	~BaseSimpleCPU ()

void	wakeup (ThreadID tid) override

void	checkForInterrupts ()

void	setupFetchRequest (const RequestPtr &req)

void	serviceInstCountEvents ()

void	preExecute ()

void	postExecute ()

void	advancePC (const Fault &fault)

void	haltContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now halted. More...

void	resetStats () override
	Callback to reset stats. More...

virtual Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())

virtual Fault	initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())

virtual Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >())

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)

virtual Fault	initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)

void	countInst ()

void	countFetchInst ()

void	countCommitInst ()

Counter	totalInsts () const override

Counter	totalOps () const override

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override
	Serialize a single thread. More...

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override
	Unserialize one thread. More...

virtual Fault	initiateMemMgmtCmd (Request::Flags flags)=0
	Memory management commands such as hardware transactional memory commands or TLB invalidation commands are memory operations but are neither really (true) loads nor stores. More...

Public Member Functions inherited from gem5::BaseCPU
virtual Port &	getDataPort ()=0
	Purely virtual method that returns a reference to the data port. More...

virtual Port &	getInstPort ()=0
	Purely virtual method that returns a reference to the instruction port. More...

int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID. More...

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

virtual void	activateContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now active. More...

virtual void	suspendContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now suspended. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

	PARAMS (BaseCPU)

	BaseCPU (const Params &params, bool is_checker=false)

virtual	~BaseCPU ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

void	startup () override
	startup() is the final initialization call before simulation. More...

void	regStats () override
	Callback to set stat parameters. More...

void	regProbePoints () override
	Register probe points for this object. More...

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	switchOut ()
	Prepare for another CPU to take over execution. More...

virtual void	takeOverFrom (BaseCPU *cpu)
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...

virtual void	setReset (bool state)
	Set the reset of the CPU to be either asserted or deasserted. More...

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

virtual void	verifyMemoryMode () const
	Verify that the system is in a memory mode supported by the CPU. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

void	scheduleInstStop (ThreadID tid, Counter insts, std::string cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

void	scheduleSimpointsInstStop (std::vector< Counter > inst_starts)
	Schedule simpoint events using the scheduleInstStop function. More...

void	scheduleInstStopAnyThread (Counter max_insts)
	Schedule an exit event when any threads in the core reach the max_insts instructions using the scheduleInstStop function. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseMMU mmu)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

virtual void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
	This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away. More...

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
trace::InstRecord *	traceData

CheckerCPU *	checker

std::vector< SimpleExecContext * >	threadInfo

std::list< ThreadID >	activeThreads

StaticInstPtr	curStaticInst
	Current instruction. More...

StaticInstPtr	curMacroStaticInst

Public Attributes inherited from gem5::BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

gem5::BaseCPU::BaseCPUStats	baseStats

Cycles	syscallRetryLatency

std::vector< std::unique_ptr< FetchCPUStats > >	fetchStats

std::vector< std::unique_ptr< ExecuteCPUStats > >	executeStats

std::vector< std::unique_ptr< CommitCPUStats > >	commitStats

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Protected Types
enum	Status { Idle, Running, Faulting, ITBWaitResponse, IcacheRetry, IcacheWaitResponse, IcacheWaitSwitch, DTBWaitResponse, DcacheRetry, DcacheWaitResponse, DcacheWaitSwitch }

Protected Types inherited from gem5::BaseCPU
enum	CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }

Protected Member Functions
void	checkPcEventQueue ()

void	swapActiveThread ()

void	traceFault ()
	Handler used when encountering a fault; its purpose is to tear down the InstRecord. More...

Protected Member Functions inherited from gem5::BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

probing::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Protected Attributes
ThreadID	curThread

branch_prediction::BPredUnit *	branchPred

Status	_status

std::unique_ptr< PCStateBase >	preExecuteTempPC

Protected Attributes inherited from gem5::BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests More...

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

SignalSinkPort< bool >	modelResetPort

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

probing::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

probing::PMUUPtr	ppRetiredInstsPC

probing::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

probing::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

probing::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

probing::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

probing::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Additional Inherited Members
Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::BaseCPU
static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStats >	globalStats
	Pointer to the global stat structure. More...

Detailed Description

Definition at line 83 of file base.hh.

Member Enumeration Documentation

◆ Status

enum gem5::BaseSimpleCPU::Status

protected

Enumerator
Idle
Running
Faulting
ITBWaitResponse
IcacheRetry
IcacheWaitResponse
IcacheWaitSwitch
DTBWaitResponse
DcacheRetry
DcacheWaitResponse
DcacheWaitSwitch

Definition at line 108 of file base.hh.

Constructor & Destructor Documentation

◆ BaseSimpleCPU()

gem5::BaseSimpleCPU::BaseSimpleCPU ( const BaseSimpleCPUParams & params )

Definition at line 83 of file base.cc.

References checker, fatal, gem5::FullSystem, gem5::SimpleThread::getTC(), gem5::ArmISA::i, gem5::BaseCPU::numThreads, gem5::VegaISA::p, gem5::CheckerCPU::setSystem(), gem5::BaseCPU::threadContexts, and threadInfo.

◆ ~BaseSimpleCPU()

gem5::BaseSimpleCPU::~BaseSimpleCPU ( )

virtual

Definition at line 210 of file base.cc.

Member Function Documentation

◆ advancePC()

void gem5::BaseSimpleCPU::advancePC ( const Fault & fault )

◆ amoMem()

virtual Fault gem5::BaseSimpleCPU::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlinevirtual

Reimplemented in gem5::AtomicSimpleCPU.

Definition at line 171 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::amoMem().

◆ checkForInterrupts()

void gem5::BaseSimpleCPU::checkForInterrupts ( )

Definition at line 273 of file base.cc.

References gem5::BaseCPU::checkInterrupts(), curThread, gem5::SimpleThread::decoder, DPRINTF, gem5::SimpleExecContext::fetchOffset, gem5::SimpleThread::getTC(), gem5::SimpleExecContext::inHtmTransactionalState(), gem5::BaseCPU::interrupts, gem5::NoFault, gem5::InstDecoder::reset(), gem5::SimpleExecContext::thread, and threadInfo.

Referenced by gem5::TimingSimpleCPU::fetch(), and gem5::AtomicSimpleCPU::tick().

◆ checkPcEventQueue()

void gem5::BaseSimpleCPU::checkPcEventQueue ( )

protected

Definition at line 123 of file base.cc.

References curThread, gem5::MipsISA::pc, gem5::BaseCPU::threadContexts, and threadInfo.

Referenced by gem5::TimingSimpleCPU::fetch(), and gem5::AtomicSimpleCPU::tick().

◆ countCommitInst()

void gem5::BaseSimpleCPU::countCommitInst ( )

Definition at line 175 of file base.cc.

References gem5::BaseCPU::baseStats, gem5::BaseCPU::commitStats, curStaticInst, curThread, gem5::StaticInst::isLastMicroop(), gem5::StaticInst::isMicroop(), gem5::BaseCPU::BaseCPUStats::numInsts, gem5::SimpleExecContext::thread, gem5::SimpleThread::threadId(), and threadInfo.

Referenced by postExecute().

◆ countFetchInst()

void gem5::BaseSimpleCPU::countFetchInst ( )

Definition at line 162 of file base.cc.

References curStaticInst, curThread, gem5::BaseCPU::fetchStats, gem5::StaticInst::isLastMicroop(), gem5::StaticInst::isMicroop(), gem5::SimpleExecContext::thread, gem5::SimpleThread::threadId(), and threadInfo.

Referenced by preExecute().

◆ countInst()

void gem5::BaseSimpleCPU::countInst ( )

Definition at line 151 of file base.cc.

References curStaticInst, curThread, gem5::StaticInst::isLastMicroop(), gem5::StaticInst::isMicroop(), gem5::SimpleExecContext::numInst, gem5::SimpleExecContext::numOp, and threadInfo.

Referenced by gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), and gem5::AtomicSimpleCPU::tick().

◆ haltContext()

void gem5::BaseSimpleCPU::haltContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now halted.

Reimplemented from gem5::BaseCPU.

Definition at line 215 of file base.cc.

References gem5::BaseCPU::CPU_STATE_SLEEP, gem5::BaseCPU::suspendContext(), and gem5::BaseCPU::updateCycleCounters().

◆ initiateMemAMO()

virtual Fault gem5::BaseSimpleCPU::initiateMemAMO	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlinevirtual

Reimplemented in gem5::TimingSimpleCPU.

Definition at line 178 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::initiateMemAMO().

◆ initiateMemMgmtCmd()

virtual Fault gem5::BaseSimpleCPU::initiateMemMgmtCmd ( Request::Flags flags )

pure virtual

Memory management commands such as hardware transactional memory commands or TLB invalidation commands are memory operations but are neither really (true) loads nor stores.

For this reason the interface is extended, and initiateMemMgmtCmd() is used to instigate the command.

Implemented in gem5::TimingSimpleCPU, and gem5::AtomicSimpleCPU.

Referenced by gem5::SimpleExecContext::initiateMemMgmtCmd().

◆ initiateMemRead()

virtual Fault gem5::BaseSimpleCPU::initiateMemRead	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inlinevirtual

Reimplemented in gem5::TimingSimpleCPU.

Definition at line 156 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::initiateMemRead().

◆ postExecute()

void gem5::BaseSimpleCPU::postExecute ( )

Definition at line 412 of file base.cc.

Referenced by gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), gem5::AtomicSimpleCPU::tick(), and gem5::TimingSimpleCPU::translationFault().

◆ preExecute()

void gem5::BaseSimpleCPU::preExecute ( )

Definition at line 328 of file base.cc.

Referenced by gem5::TimingSimpleCPU::completeIfetch(), and gem5::AtomicSimpleCPU::tick().

◆ readMem()

virtual Fault gem5::BaseSimpleCPU::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inlinevirtual

Reimplemented in gem5::AtomicSimpleCPU.

Definition at line 149 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::readMem().

◆ resetStats()

void gem5::BaseSimpleCPU::resetStats ( )

overridevirtual

Callback to reset stats.

Reimplemented from gem5::statistics::Group.

Definition at line 223 of file base.cc.

References _status, Idle, gem5::statistics::Group::resetStats(), and threadInfo.

◆ serializeThread()

void gem5::BaseSimpleCPU::serializeThread	(	CheckpointOut &	cp,
		ThreadID	tid
	)		const

overridevirtual

Serialize a single thread.

Parameters

cp	The stream to serialize to.
tid	ID of the current thread.

Reimplemented from gem5::BaseCPU.

Definition at line 232 of file base.cc.

References _status, Idle, Running, and threadInfo.

◆ serviceInstCountEvents()

void gem5::BaseSimpleCPU::serviceInstCountEvents ( )

Definition at line 321 of file base.cc.

References gem5::SimpleThread::comInstEventQueue, curThread, gem5::SimpleExecContext::numInst, gem5::EventQueue::serviceEvents(), gem5::SimpleExecContext::thread, and threadInfo.

Referenced by gem5::TimingSimpleCPU::advanceInst(), and gem5::AtomicSimpleCPU::tick().

◆ setupFetchRequest()

void gem5::BaseSimpleCPU::setupFetchRequest ( const RequestPtr & req )

Definition at line 304 of file base.cc.

References curThread, decoder, gem5::SimpleThread::decoder, DPRINTF, gem5::SimpleExecContext::fetchOffset, gem5::Request::INST_FETCH, gem5::PCStateBase::instAddr(), gem5::BaseCPU::instRequestorId(), gem5::SimpleThread::pcState(), gem5::SimpleExecContext::thread, and threadInfo.

Referenced by gem5::TimingSimpleCPU::fetch(), and gem5::AtomicSimpleCPU::tick().

◆ swapActiveThread()

void gem5::BaseSimpleCPU::swapActiveThread ( )

protected

Definition at line 135 of file base.cc.

References activeThreads, curStaticInst, curThread, gem5::StaticInst::isDelayedCommit(), gem5::BaseCPU::numThreads, and threadInfo.

Referenced by gem5::TimingSimpleCPU::fetch(), and gem5::AtomicSimpleCPU::tick().

◆ totalInsts()

Counter gem5::BaseSimpleCPU::totalInsts ( ) const

overridevirtual

Implements gem5::BaseCPU.

Definition at line 189 of file base.cc.

References threadInfo.

◆ totalOps()

Counter gem5::BaseSimpleCPU::totalOps ( ) const

overridevirtual

Implements gem5::BaseCPU.

Definition at line 200 of file base.cc.

References threadInfo.

◆ traceFault()

void gem5::BaseSimpleCPU::traceFault ( )

protected

Handler used when encountering a fault; its purpose is to tear down the InstRecord.

If a fault is meant to be traced, the handler won't delete the record and it will annotate the record as coming from a faulting instruction.

Definition at line 262 of file base.cc.

References gem5::trace::InstRecord::setFaulting(), and traceData.

Referenced by gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), gem5::AtomicSimpleCPU::tick(), and gem5::TimingSimpleCPU::translationFault().

◆ unserializeThread()

void gem5::BaseSimpleCPU::unserializeThread	(	CheckpointIn &	cp,
		ThreadID	tid
	)

overridevirtual

Unserialize one thread.

Parameters

cp	The checkpoint use.
tid	ID of the current thread.

Reimplemented from gem5::BaseCPU.

Definition at line 240 of file base.cc.

References threadInfo.

◆ wakeup()

void gem5::BaseSimpleCPU::wakeup ( ThreadID tid )

overridevirtual

Implements gem5::BaseCPU.

Definition at line 251 of file base.cc.

References DPRINTF, gem5::BaseCPU::getCpuAddrMonitor(), gem5::AddressMonitor::gotWakeup, gem5::ThreadContext::Suspended, and threadInfo.

Referenced by gem5::AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), gem5::TimingSimpleCPU::DcachePort::recvFunctionalSnoop(), gem5::TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), gem5::TimingSimpleCPU::threadSnoop(), and gem5::AtomicSimpleCPU::threadSnoop().

◆ writeMem()

virtual Fault gem5::BaseSimpleCPU::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inlinevirtual

Reimplemented in gem5::TimingSimpleCPU, and gem5::AtomicSimpleCPU.

Definition at line 163 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::writeMem().

Member Data Documentation

◆ _status

Status gem5::BaseSimpleCPU::_status

protected

Definition at line 123 of file base.hh.

◆ activeThreads

std::list<ThreadID> gem5::BaseSimpleCPU::activeThreads

Definition at line 101 of file base.hh.

Referenced by gem5::AtomicSimpleCPU::activateContext(), gem5::TimingSimpleCPU::activateContext(), gem5::AtomicSimpleCPU::drain(), gem5::TimingSimpleCPU::drain(), gem5::AtomicSimpleCPU::drainResume(), gem5::TimingSimpleCPU::drainResume(), gem5::AtomicSimpleCPU::suspendContext(), gem5::TimingSimpleCPU::suspendContext(), and swapActiveThread().

◆ branchPred

branch_prediction::BPredUnit* gem5::BaseSimpleCPU::branchPred

protected

Definition at line 87 of file base.hh.

Referenced by advancePC(), and preExecute().

◆ checker

CheckerCPU* gem5::BaseSimpleCPU::checker

Definition at line 98 of file base.hh.

Referenced by BaseSimpleCPU().

◆ curMacroStaticInst

StaticInstPtr gem5::BaseSimpleCPU::curMacroStaticInst

Definition at line 105 of file base.hh.

Referenced by advancePC(), gem5::TimingSimpleCPU::fetch(), preExecute(), and gem5::AtomicSimpleCPU::tick().

◆ curStaticInst

StaticInstPtr gem5::BaseSimpleCPU::curStaticInst

Current instruction.

Definition at line 104 of file base.hh.

Referenced by advancePC(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), countCommitInst(), countFetchInst(), countInst(), gem5::TimingSimpleCPU::fetch(), postExecute(), preExecute(), swapActiveThread(), and gem5::AtomicSimpleCPU::tick().

◆ curThread

ThreadID gem5::BaseSimpleCPU::curThread

protected

Definition at line 86 of file base.hh.

◆ preExecuteTempPC

std::unique_ptr<PCStateBase> gem5::BaseSimpleCPU::preExecuteTempPC

protected

Definition at line 133 of file base.hh.

Referenced by preExecute().

◆ threadInfo

std::vector<SimpleExecContext*> gem5::BaseSimpleCPU::threadInfo

Definition at line 100 of file base.hh.

◆ traceData

trace::InstRecord* gem5::BaseSimpleCPU::traceData

Definition at line 97 of file base.hh.

The documentation for this class was generated from the following files:

cpu/simple/base.hh
cpu/simple/base.cc

Public Member Functions

Public Attributes

Protected Types

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Member Enumeration Documentation

◆ Status

Constructor & Destructor Documentation

◆ BaseSimpleCPU()

◆ ~BaseSimpleCPU()

Member Function Documentation

◆ advancePC()

◆ amoMem()

◆ checkForInterrupts()

◆ checkPcEventQueue()

◆ countCommitInst()

◆ countFetchInst()

◆ countInst()

◆ haltContext()

◆ initiateMemAMO()

◆ initiateMemMgmtCmd()

◆ initiateMemRead()

◆ postExecute()

◆ preExecute()

◆ readMem()

◆ resetStats()

◆ serializeThread()

◆ serviceInstCountEvents()

◆ setupFetchRequest()

◆ swapActiveThread()

◆ totalInsts()

◆ totalOps()

◆ traceFault()

◆ unserializeThread()

◆ wakeup()

◆ writeMem()

Member Data Documentation

◆ _status

◆ activeThreads

◆ branchPred

◆ checker

◆ curMacroStaticInst

◆ curStaticInst

◆ curThread

◆ preExecuteTempPC

◆ threadInfo

◆ traceData