gem5::RiscvISA::PCState Class Reference

#include <pcstate.hh>

Inheritance diagram for gem5::RiscvISA::PCState:

Public Member Functions
	PCState ()=default
	PCState (const PCState &other)=default
	PCState (Addr addr, RiscvType rv_type)
PCStateBase *	clone () const override
void	update (const PCStateBase &other) override
void	compressed (bool c)
bool	compressed () const
void	rvType (RiscvType rv_type)
RiscvType	rvType () const
bool	branching () const override
Public Member Functions inherited from gem5::GenericISA::UPCState< 4 >
void	output (std::ostream &os) const override
PCStateBase *	clone () const override
void	set (Addr val)
	UPCState (const UPCState &other)
	UPCState ()
	UPCState (Addr val)
UPCState &	operator= (const UPCState &other)=default
bool	branching () const override
void	uAdvance ()
void	uEnd ()
Public Member Functions inherited from gem5::GenericISA::SimplePCState< InstWidth >
	SimplePCState (const SimplePCState &other)
SimplePCState &	operator= (const SimplePCState &other)=default
	SimplePCState ()
	SimplePCState (Addr val)
void	set (Addr val)
	Force this PC to reflect a particular value, resetting all its other fields around it. More...
void	advance () override
Public Member Functions inherited from gem5::GenericISA::PCStateWithNext
Addr	pc () const
void	pc (Addr val)
Addr	npc () const
void	npc (Addr val)
MicroPC	upc () const
void	upc (MicroPC val)
MicroPC	nupc () const
void	nupc (MicroPC val)
void	uReset () override
void	setNPC (Addr val)
bool	equals (const PCStateBase &other) const override
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
Public Member Functions inherited from gem5::PCStateBase
virtual	~PCStateBase ()=default
template<class Target >
Target &	as ()
template<class Target >
const Target &	as () const
void	update (const PCStateBase *ptr)
Addr	instAddr () const
	Returns the memory address of the instruction this PC points to. More...
MicroPC	microPC () const
	Returns the current micropc. More...
Public Member Functions inherited from gem5::Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)

Private Attributes
bool	_compressed = false
RiscvType	_rv_type = RV64

Additional Inherited Members
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...
static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...
Protected Types inherited from gem5::GenericISA::UPCState< 4 >
typedef SimplePCState< InstWidth >	Base
Protected Types inherited from gem5::GenericISA::SimplePCState< InstWidth >
typedef PCStateWithNext	Base
Protected Member Functions inherited from gem5::GenericISA::PCStateWithNext
	PCStateWithNext (const PCStateWithNext &other)
PCStateWithNext &	operator= (const PCStateWithNext &other)=default
	PCStateWithNext ()
Protected Member Functions inherited from gem5::PCStateBase
	PCStateBase (const PCStateBase &other)
PCStateBase &	operator= (const PCStateBase &other)=default
	PCStateBase ()
Protected Attributes inherited from gem5::GenericISA::PCStateWithNext
Addr	_npc = 0
MicroPC	_nupc = 1
Protected Attributes inherited from gem5::PCStateBase
Addr	_pc = 0
MicroPC	_upc = 0

Detailed Description

Definition at line 57 of file pcstate.hh.

Constructor & Destructor Documentation

PCState() [1/3]

gem5::RiscvISA::PCState::PCState ( )

default

Referenced by clone().

PCState() [2/3]

gem5::RiscvISA::PCState::PCState ( const PCState &  other )

default

PCState() [3/3]

gem5::RiscvISA::PCState::PCState ( Addr  addr, RiscvType  rv_type  )

inline

Definition at line 66 of file pcstate.hh.

Member Function Documentation

branching()

bool gem5::RiscvISA::PCState::branching ( ) const

inlineoverridevirtual

Reimplemented from gem5::GenericISA::SimplePCState< InstWidth >.

Definition at line 88 of file pcstate.hh.

References _compressed, gem5::GenericISA::PCStateWithNext::npc(), gem5::GenericISA::PCStateWithNext::nupc(), gem5::GenericISA::PCStateWithNext::pc(), and gem5::GenericISA::PCStateWithNext::upc().

clone()

PCStateBase* gem5::RiscvISA::PCState::clone ( ) const

inlineoverridevirtual

Reimplemented from gem5::GenericISA::SimplePCState< InstWidth >.

Definition at line 70 of file pcstate.hh.

References PCState().

compressed() [1/2]

bool gem5::RiscvISA::PCState::compressed ( ) const

inline

Definition at line 82 of file pcstate.hh.

References _compressed.

compressed() [2/2]

void gem5::RiscvISA::PCState::compressed ( bool  c )

inline

Definition at line 81 of file pcstate.hh.

References _compressed, and gem5::RiscvISA::c.

rvType() [1/2]

RiscvType gem5::RiscvISA::PCState::rvType ( ) const

inline

Definition at line 85 of file pcstate.hh.

References _rv_type.

rvType() [2/2]

void gem5::RiscvISA::PCState::rvType ( RiscvType  rv_type )

inline

Definition at line 84 of file pcstate.hh.

References _rv_type, and gem5::RiscvISA::rv_type.

update()

void gem5::RiscvISA::PCState::update ( const PCStateBase &  other )

inlineoverridevirtual

Reimplemented from gem5::GenericISA::PCStateWithNext.

Definition at line 73 of file pcstate.hh.

References _compressed, _rv_type, gem5::PCStateBase::as(), and gem5::GenericISA::PCStateWithNext::update().

Member Data Documentation

_compressed

bool gem5::RiscvISA::PCState::_compressed = false

private

Definition at line 60 of file pcstate.hh.

Referenced by branching(), compressed(), and update().

_rv_type

RiscvType gem5::RiscvISA::PCState::_rv_type = RV64

private

Definition at line 61 of file pcstate.hh.

Referenced by rvType(), and update().

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The documentation for this class was generated from the following file:

• arch/riscv/pcstate.hh